SPFD-Based Effective One-to-Many Rewiring (OMR) for Delay Reduction of LUT-based FPGA Circuits

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1 SPFD-Based Effectve One-to-Many Rewrng (OMR) for Delay Reducton of LUT-based FPGA Crcuts Katsunor Tanaka Grad. School of Informatcs, Kyoto Unversty, 66-85, Kyoto, Japan Shgeru Yamashta Grad. School of Informaton Scence, NAIST Ikoma, Nara, 63-, Japan Yahko Kambayash Grad. School of Informatcs, Kyoto Unversty, 66-85, Kyoto, Japan ABSTRACT Ths paper proposes an nnovatve method for SPFD-based rewrng n Look-Up-Table-based (LUT-based) FPGA crcuts. The new method adds new nput wres to two or more LUT s n order to remove or to replace a target wre. There have been a few rewrng methods for FPGA crcuts so far, such as the orgnal SPFD-based optmzaton sometmes called Local Rewrng (LR), SPFD-based Global Rewrng (GR) and SPFD-based Enhanced Rewrng (ER). However, all of them replace one wre wth other new nput wre to one LUT but not wth those to two or more LUT s. Moreover, the LR removes or replaces nput wres wth new one to the same LUT only, and the GR and ER topologcally lmt the LUT s where new nput wres are added. Our new method, called One-to-Many Rewrng (OMR), loosens such topologcal constrants for more flexble FPGA crcut transformaton so that t s easer to mport constrants on physcal desgn to the logc optmzaton. The expermental results show our OMR can transform FPGA crcuts more flexbly than the LR, GR and ER, by ntroducng the new manpulaton, wre addton. The OMR can rewre.2 tmes as many wres as the exstng methods, especally, the ER. The computaton tme s as short as the exstng methods. Categores and Subject Descrptors B.6.3 [Logc Desgn]: Desgn Ads Optmzaton; B.7. [Integrated Crcuts]: Types and Desgn Styles Gate Arrays General Terms Algorthms, Desgn Keywords SPFD, LogcOptmzaton, One-to-Many Rewrng (OMR), Global Rewrng (GR), Collaboraton of Logcand Physcal Desgn Permsson to make dgtal or hard copes of all or part of ths work for personal or classroom use s granted wthout fee provded that copes are not made or dstrbuted for proft or commercal advantage and that copes bear ths notce and the full ctaton on the frst page. To copy otherwse, to republsh, to post on servers or to redstrbute to lsts, requres pror specfc permsson and/or a fee. GLSVLSI 4, Apr , 24, Boston, Massachusetts, USA Copyrght 24 ACM /4/4...$5... INTRODUCTION FPGA crcuts have been used manly for prototypng, but now are often employed for practcal mplementatons. Whle ther performance s stll lower than full/sem-customdesgned crcuts, the technology s adopted partally or fully n crcut desgn and producton due to ts advantageous feature, reconfgurable. Ths s expected to be the key feature of new computer models n the future. FPGA s classfed nto two types, Multplexer-based (MUXbased) and Look-Up-Table-based (LUT-based). The former type of crcuts consst of MUX s and are desgned somorphcally to the bnary decson dagrams (BDD s) for the functons to realze. The latter type of crcuts consst of logc blocks, called LUT s, and nterconnectons among them. Each LUT n an FPGA crcut can realze any functon wth respect to a specfed number of varables. When the number s K, then the FPGA crcut s sad to be K-feasble and the functon stored nsde of the LUT s called the nternal functon. In such a K-feasble crcut, each LUT can work smlarly to a K-nput gate. The functon realzed by the LUT s analogous to the logcoperatons realzed by the gate. Therefore, logcoptmzaton methods for gate networks have been appled or extended for LUT-based FPGA. One of the most powerful logcoptmzaton methods s the Transducton Method [], whch s based on the concept of permssble functons (PFs). Ths method utlzes the concept of permssble functons (PFs) n order to transform logc crcuts, whch can be represented by an drected acyclc graph. A set of PFs (SPF) s expressed wth an ncompletely specfed functon (ISF). The method was orgnally nvented for NOR logc crcuts and has been extended for more types of logc gate crcuts [2] and LUTbased FPGA logcoptmzaton [7]. The bggest advantage of the Transducton Method s to be easer to mport constrants on physcal desgn nto logc desgn. Thus, whle the physcal desgn lke placement and routng s gettng more mportant for hgh-performance FPGA crcut desgn, transformaton-based logcoptmzatons, such as the Transducton Method as well as ATPG (Automatc Test Pattern Generaton)-based ones [5] [6] [8] [9] [] [] [2], are also gettng more sgnfcant, snce such optmzaton methods can transform logc crcuts so flexbly that the crcuts satsfy the specfcatons, such as the speed and area. In the case of use for LUT-based FPGA, there s a great advantage of logcflexblty utlzed for logcoptmzaton: modfcaton of the nternal functon. When SPF s repre- 348

2 Intenal Functon Modfcaton (IFM) Prmary outputs vs w v t v d v t O Target Wre v Removal s2 w a Wre Addton v O2 v a Domnator vs Wre Addton wo ws w v t v t d Target Wre v s2 wa Removal ws 2 IFM w v a O 2 Prmary outputs v O v O2 Fgure : A Domnator consdered n GR and ER Fgure 2: Relaxaton of Topologcal Constrants by OMR sented as ISF s are used n the logcoptmzaton, the representaton takes an mplct undesred constrant that the nternal functon s not changed when the procedure s appled to manpulaton of nput wres of LUT s. Sets of pars of functons to be dstngushed (SPFD s) were derved for optmzaton of LUT-based FPGA logc networks [3] to take full advantage of the flexble change of the nternal functon, and are a more generalzed representaton of functonal permssblty than ISF s. At each tme n the logcoptmzaton, the orgnal SPFD-based transformaton s appled to one LUT as removal of nput wres and replacement of exstng nput wres wth new ones to the LUT. That s why ths transformaton s called SPFD-based Local Rewrng (LR) also. In order to take physcal desgn nto consderaton durng logcdesgn phase, SPFD-based Global Rewrng (GR) was proposed n [4]. The GR assumes the followng scenaro:. Netlsts are logcally syntheszed and optmzed. 2. They are technology-mapped, placed and routed onto a gven LUT-based FPGA archtecture. Then, delay nformaton of the desgned crcut s obtaned. 3. Based on the delay nformaton, rewrng procedure s appled to the netlsts. In order to explan the dea of GR n contrast to LR, we thnk of an example shown n Fg.. Let the delay of a wre, w t, be denoted by D(w). Suppose that D(w t) s crtcally long. In ths case, w s called the target wre. In the LR, w s just removed or replaced wth a new nput wre to v t, f the SPFD-based condton s satsfed. On the other hand, the GR takes a tral-and-error-lke strategy. Wthout any SPFD calculaton, w s removed temporarly at the frst step of the algorthm. As a consequence, the prmary output functons may be undesrably changed. In order to restore them, the GR looks for a new wre added to v d called the domnator, whch s shown by w a n Fg., and tres to modfy the nternal functon of v d. Thus, the GR s consdered to be -to- rewrng. IfD(w a) s far smaller than D(w t), then the total delay of the crcut s expected to be reduced. The enhanced SPFD-based rewrng (ER) was proposed n [5] and nherts the transformaton concept of the GR. In order words, the ER s also -to- rewrng. The advantage of the ER to the GR s that the functon at v d can be more flexbly changed, keepng the prmary output functons unchanged. Compared wth the tradtonal logcoptmzaton methods, the GR and ER have the followng undesrable constrants, whch are explaned by usng Fg. :. The wres substtuted for w are added to one of the domnators, such as v d, only. 2. w s removed only, but not replaced wth a new nput wre to v t wth addton of wres to other LUT s. In order to loosen the constrants, we propose, n ths paper, an nnovatve method, SPFD-Based One-to-Many (-to-m) Rewrng (OMR), where m may be equal to or larger than 2. The advantage of the OMR s llustrated n Fg. 2. Ths OMR performs rewrng by addng two or more wres for removal or replacement of the target wre. In the case of the example n Fg., w can be removed wth addton of two or more of new nput wres to v s, v s2, v O and v O2 as well as v d, whch are shown by w s, w s2, w O and w O2 as well as w a n Fg. 2, respectvely. Moreover, w t s not only removed but also may be replaced wth a new nput wre to v t. In other words, the constrants. and 2. are loosened. That s advantages of our OMR over the LR, GR and ER. Although the wre count s ncreased, f D(w t) s smaller than any of the added wres, then the total delay s expected to be reduced more than the LR, GR and ER. In fact, wre addton to an LUT appears not to be helpful, snce the nternal functon of the LUT can gnore the new varable for the added wre,.e., the varable can regarded as a dummy. However, there are several cases where wre addton affects transformaton of the FPGA crcut later than the addton. In ths paper, we present a suffcent condton to be satsfed for the helpful wre addton. The OMR exceeds the conventonal rewrng wth respect to two ponts; one pont s that any wre can be a canddate of rewrng ndependently of the topology and the other pont s that even f the wre can be a canddate of GR or ER, the removal of the target wre can be compensated for by addton of two or more new wres but of not only one. The expermental results show the above advantages over the LR, GR and ER, and that.2 tmes as many wres as the ER can be removed or replaced by the OMR. Wth respect to the computaton tme, the OMR copes wth the exstng rewrng methods. Ths results show that compared wth the conventonal methods, the OMR s enough useful for the delay-reducng rewrng by utlzng the nformaton mported from the results of placement and routng. Ths paper s organzed as follows: Secton 2 ntroduces termnologes and notatons to descrbe our OMR algorthm. Secton 3 descrbes the basc calculaton method of the conventonal SPFD s. Secton 4 proposes our OMR algorthm and condtons to perform the OMR effcently wth an example to llustrate the effects. Secton 5 shows expermental results to clam our OMR algorthm s beneft over GR and ER. Secton 6 concludes ths paper. 2. TERMINOLOGIES AND NOTATIONS Ths paper dscusses an LUT-based (Look-Up-Table-based) FPGA (Feld Programmable Gate Array) network. It s gven n prmary nput varables, x, x 2,...,x n, but snce the functon at any pont s wth respect to the varables, they are always handled as a vector, x. A network conssts 349

3 Table : Functonal Expresson for an m-par SPFD (h,,h,) x = =2 = m g (, ) (, ) (, ) a (, ) (, ) (, ) a 2 (, ) (, ) (, ) a m (, ) (, ) (, ) (, ) (, ) (, ) a 2 (, ) (, ) (, ) (, ) (, ) (, ) a (, ) (, ) (, ) a m W means m_ = (h, h,) of look-up-tables (LUT s) whch can realze any but only one functon wth respect to a lmted number of varables. In ths paper, the functon s called the nternal functon of the LUT. Although the number of nput wres s changed by logcoptmzaton, the number of varables s supposed to be K ntally. Each of the K nput wres are gven an ordnal number,, 2,..., K, and the correspondng varable of the nternal functon s denoted by y, y 2,...,y K. The functon at each nput wre of an LUT, v, wth respect to the prmary nput varables, x, x 2,..., x n, s denoted by f /v, f 2/v,..., f K/v. The nternal functon s denoted by u(y,y 2,...,y k ), and the argument, (y,y 2,...,y K), s often omtted. The functon at the output of the LUT s denoted by f /v. The K varables, y, y 2,...,y K, s handled as a vector, denoted as y. In ths paper, the logcand, OR and NOT operatons are denoted as, and an over-lne, respectvely. In the case of AND, also may be used as the operator. (For example, the K-nput OR nternal functon s represented by u = y y 2... y K.) The constant functon whose value s or for any prmary nput vector, x, s denoted as or, respectvely. 3. BASIC CALCULATION OF SPFD S An SPFD s the concept to represent a set of completely specfed functons (CSF s), correspondng to an ncompletely specfed functon (ISF), whch represents maxmum/compatble set of permssble functons (MSPF/CSPF) n the Transducton Method. An ISF s expressed wth a par of CSF s, for example, the ON-set and OFF-set functons. Let an ISF be f. The ON-set and OFF-set, f ON and f OFF, are defned as follows: f ON (x) = only for every x such that f(x) =. f OFF (x) = only for every x such that f(x) =. (f ON (x) =f OFF (x) = for every x such that f(x) = (don t-care).) Then, for every CSF, g, satsfyng the ISF, f, the followng relatonshp holds: f ON g f OFF () As an extenson of ISF-form representaton, an SPFD s expressed n the followng form: {(h,,h,), (h 2,,h 2,),...,(h m,,h m,)}. (2) where m s a non-negatve nteger, h, h, =, but h, and h, hold for every =, 2,...,m. For each, the correspondng set conssts of CSF s, g s, satsfyng the followng condton: h, g h, or h, g h, (3) When ths condton s satsfed, g s sad to dstngush h, and h,. Moreover, f g dstngushes all the m pars, g s sad to satsfy the SPFD. In the case of m =, the SPFD s very smlar to an ISF snce h, and h, are regarded as the on-set and off-set functons of the ISF, respectvely. However, unlke n the ISF, they can be regarded conversely. In other words, t represents a par of ISF s. If (h, h,)(h j, h j,) = holds for any (, j) where j, =,...,m and j =,...,m, then the SPFD represents 2 m ISF s. The ISF s can be represented a functonal expresson n Table where or can be assgned to a n g for each =, 2,...,m. Lke MSPF s and CSPF s n the Transducton Method, SPFD s are used to determne whether wres can be removed or replaced. In the case of SPFD s, ths removal and replacement consders the modfcaton of nternal functons, whch are analogous to gate types, such as AND or OR. Thus, SPFD s can be utlzed partcularly for optmzaton of LUT-based FPGA networks. In ths secton, we ntroduce how to calculate and use SPFD s for the optmzaton. 3. SPFD Calculaton at Input Wres Let us consder how to calculate SPFD s at all K nput wres of an LUT, v, whch are denoted as SPFD /v, SPFD 2/v,..., SPFD K/v. We suppose that SPFD at the output of an LUT s obtaned beforehand so as to consst of only one par,.e., SPFD /v = {(h /v,h /v )}, as wll be mentoned n Secton 3.4. Then, the SPFD s at the K nput wres, SPFD /v, SPFD 2/v,..., SPFD K/v, are computed as follows: 3.. Step : For every (y y 2...y k ) = (...),..., (...), the followng functon s calculated: h y/v = h y y 2...y k /v =(h /v h /v ) K^ = ˆf /v. (4) where ˆf s a CSF defned for each =, 2,...,K as follows: ρ f/v f y = ˆf /v = (5) f /v f y =. As a result, 2 K functons are obtaned n total Step 2: Pars of these CSF s are made up to be contaned n the SPFD s by constructng the followng two sets, H ON/v = {h yon /v h yon /v h /v, h yon /v }. H OFF/v = {h yof F /v h yof F /v h /v, h yof F /v }. and by calculatng the drect product as follows: (6) P v = H ON/v H OFF/v. (7) where P v s to be the unon of all the SPFD s at the nput wres to be computed n Step 3. 35

4 (a) Functons f /vs f /vs2 f /vt x Table 2: Example wthout Wre Addton (b) Expresson of Functons Satsfyng SPFD s g /vs g /vs2 g /vt x a a 2 a 3 a 4 a 5 a 7 a b 2 a 3 a 4 b 5 a 6 b b 2 b 3 b 4 b 5 a 7 a a 2 b 5 a 6 a 3 b 4 b 5 b 7 b a 2 b 3 a 4 b 5 a 7 b a 2 b 3 b 4 a 5 a 6 b Step 3: Each (h yon /v,h yof F /v ) P v s assgned nto SPFD j such that h yon /v f j/v h yof F /v or (8) h yof F /v f j/v h yon /v. holds. There may exst two or more j s such that Eq.(8) holds. In ths case, one can be chosen from them, based on the gven prortes set up by heurstcs. As a result of ths assgnment for all the pars, SPFD j/v s obtaned for every j =, 2,...,K. 3.2 Transformatons based on SPFD s at Input Wres 3.2. Removal of an nput wre The j-th nput wre of an LUT, v, can be removed f the followng condton s satsfed: SPFD j/v =. (9) Replacement of an nput wre Suppose that SPFD j s obtaned as {(h yon,hyof F ) =,...,m} where h yon s or hyof F s may be dentcal for some of the s. Then, the j-th nput wre can be replaced wth a new one from another LUT, v, whose output functon s f /v wth respect to x f the followng condton s satsfed: h yon /v f /v h yof F /v or h yof F /v f /v h yon /v for every =,...,m. () 3.3 Internal Functon Modfcaton The concept of SPFD assumes that the nternal functon can be changed wthn a specfed number of varables. Thus, after nput wres of an LUT, v, s removed or replaced, the nternal functon must be changed,.e., modfed, n order to keep all the prmary output functons unchanged. In ths secton, we show how to modfy the nternal functon. The modfed nternal functon s obtaned n a dsjunctve form (.e., a sum of products). Assume that f /v s replaced wth g /v for each =, 2,...,K by the FPGA crcut transformaton. Each term, T j/v, n the form s obtaned, correspondng to h yon j /v H ON/v for each j =, 2,...,p as follows, when H ON conssts of p pars contanng h yon /v, h yon2 /v,..., h yonp /v:. The term contans a lteral y f SPFD /v contans a par wth h yon j /v H ON/v such that h yon j /v g, 2. The term contans a lteral y f SPFD /v contans a par wth h yon j /v H ON/v such that h yon j /v g, 3. The term contans no lteral f SPFD /v contans no par wth h yon j /v H ON/v After T j/v s are obtaned for all j =, 2,...,p, the sum s assgned as the modfed nternal functon, u = T /v T 2/v... T p/v. 3.4 SPFD Calculaton at the Output Let us consder how to compute SPFD at the output of an LUT, v, gven SPFD s at all ts t output wres, SPFD /v, SPFD 2 /v,..., SPFD t/v. Frst, the unon of all the SPFD s s calculated as follows: t[ = SPFD /v () However, the unon s not used as SPFD at the output, SPFD /v, n the conventonal calculaton f the pars n the unon are not dsjont. If the functon at the output of v were changed from f /v to g /v, then g /v would have to satsfy the unon. In other words, all the pars n the unon would have to be dstngushed by g /v. Although the nternal functon would have to be modfed so that each par s dstngushed, v can realze only one nternal functon. If the unon conssts of p pars, the LUT would have to realze at most p nternal functons, but actually not. Hence, the unon s transformed nto one-par SPFD. Suppose that the unon conssts of p pars, (h,,h,), (h 2,,h 2,),..., (h p,,h p,) where h, f /v h, holds for every =, 2,...,p. SPFD at the output, SPFD /v,s calculated by usng the followng sum operatons: SPFD /v = (ψ t _ = h,, t_!) h, = = {(h /v,h /v )}. (2) It s mportant to notce that (h /v,h /v ), gven n Secton 3., s obtaned by ths calculaton. 4. SPFD-BASED ONE-TO-MANY REWIRING (OMR) In ths secton, we show a condton for effectve wre addton and an example of the applcaton. 4. Condton for Effectve Wre Addton Let us consder the addton of an nput wre from v to v j. The addton s possbly effectve f the followng condton 35

5 (a) Functons f /vs f /vs2 f /vt x Table 3: Example wth Wre Addton (b) Expresson of Functons Satsfyng SPFD s g /vs g /vs2 g /vt x a b 2 b 3 b 4 a 5 a 9 a c 3 b 4 a 6 b c 3 a 4 b 6 a a 2 a 3 a 7 b 4 b 6 b a 2 b 3 a 4 a 5 a 6 a 7 a 9 b b 2 a 3 a 4 b 6 a 7 a 9 s satsfed: Wre Removal w t 2 3 va vt va 2 Wre Addton 3 2 vs 2 v s 2 3 Wre Addton Fgure 3: An Example Network There s at least one h y such that h y f v or h y f v holds. (3) 4.2 An Example Let us consder an example network shown n Fg. 3 where v a or v a2 s not a successor of any LUT s, v s, v s2 and v t. Assume that the delay of w t, whch s the second nput wre of v t, causes long delay and that we have been obtaned nformaton on physcal desgn that the delay of w a,s and w a2,s 2 s lkely to be shorter than the delay of w t. The functons n the network s shown n the truth table n Table 2 (a), where s the pn number of LUT s n Fg. 3. SPFD s at the outputs of v s and v s2 are obtaned to represent the ISF s n the columns, g /vs and g /vs2, respectvely, n Tables 2 (b) and 3 (b), where or can be arbtrarly assgned to a, b or c for each =, 2,...,9 ndependently Wthout Wre Addton When no wres are added to v s or v s2, SPFD s are obtaned to represent the functonal expressons n Table 2 (b)., where or can be ndependently assgned to each a or b for =, 2,...,7. In ths calculaton of SPFD s at the nput wres of v s and v s2, we assgn the prorty to assgn nto SPFD 2/vs and SPFD 2/vs2, respectvely, as few pars as possble. As shown n the column of g /vt s for all =, 2, 3, no nput wre of v t can be removed, snce the expressons mean that the none of SPFD s s empty. Thus, w s not dsconnectable wthout wre addton Effects by Wre Addton Table 3 llstrates an example of effectve wre addton. Suppose that f /va and f /va2 are equal to f 3/vs and f 3/vs2 n Table 3 (a), respectvely. In the case of these functons, the followng relatonshps are satsfed: h /vs f /va,h /vs f /va, (4) h /vs2 f /va2,h /vs2 f /va2,h /vs2 f /va2. Hence, we determne that wre addton of w a,s and w a2,s 2 s lkely to be effectve. As a result of the wre addton, the new wres become the thrd nputs of v s and v s2, as shown n Fg. 3 and Table 3 (a). Based on these functons, we obtan SPFD s represented by expressons n Table 3 (b) where or can be assgned ndependently to a, b or c for =, 2,...,9. The expresson n the column g 2/vt means that SPFD at w t, whch s the second nput wre of v t, s empty and w t can be removed. Thus, the wre addton of w a,s and w a2,s 2 makes w t redundant. Snce the delay of these added wres s shorter then the delay of the removed wre, the total delay of ths FPGA crcut s expected to be reduced, or even n the worst case, to be kept unchanged. As shown n ths example, the condton n Eq.(3) s useful to determne whch new wres should be added for the target wre to be redundant. 5. EXPERIMENTAL RESULTS As descrbed n the prevous sectons, our rewrng method, OMR, allows to add two or more new wres substtuted for the target wre, and appears to be more powerful and flexble than GR and ER. In ths secton, we show the expermental results on MCNC benchmark crcuts [3]. The ntal crcuts are composed of LUT s so that each of them has fve or fewer nput wres, by applyng SIS commands developed at UCB [4]. Ths sequence of commands yelds 5-LUT FPGA networks. In order to compare our OMR wth the LR, GR and ER, we only counted successful rewrngs, snce a crcut may not be placed and routed well even f ts structure s compact at the logc desgn level. Especally, t s theoretcally clear that the OMR and ER cover the LR and GR, respectvely. Therefore, we compared the rewrng counts by the OMR and ER. The results are shown n Table 4, where Int. means the number of wres n an ntal benchmark crcut, ER and OMR mean the numbers of target wres successfully replaced wth new ones and the computaton tme s obtaned as seconds for each target wre. In Table 4, although the results for several benchmark crcuts are not shown, we present the average results. As shown n Table 4, the OMR can replace about.2 tmes as many target wres as the ER can. Snce the topologcal constrants on the ER are loosened, t s easer for the OMR to replace target wres. It appears not to be far 352

6 Table 4: Expermental Results: Successful Rewrng Counts # of Successful RW Tme/Wre Crcut Int ER OMR Adv. ER OMR C C alu alu apex apex b example f5m term ttt x x x (%) Adv.: Target Wres that are replaced by usng OMR but not by ER. enough to compare the number of successful rewrng, snce the concepts of the OMR and ER are very dfferent. The ER once changes the prmary output functons and fnally tres to restore them. On the other hand, the OMR always keeps the prmary output functons unchanged. In fact, comparng the results on each target wre, 5% of all wres n the ntal crcuts are successfully rewred by usng the OMR but cannot by usng the ER. Snce the ER and OMR rewre about 3% and 36% successfully, the percentage, 5%, s relatvely large. Hence, we can conclude that the OMR s another opton for rewrng after the physcal desgn, such as placement and routng. Wth respect to the computaton tme, the OMR takes about 82% as long as the ER does. However, benchmark crcuts, C432 and 9, take very long tme relatvely to the other ones. Wthout these crcuts, the computaton tme of the OMR s longer than that of the ER. Consderng the procedures of the ER and OMR, both need SPFD calculaton once. Snce the OMR looks for effectvely added wres, t s consdered to need addtonal tme proportonal to the number of LUT s n a crcut. On the other hand, the ER s appled only to domnators, whch are consdered to be far fewer than the LUT s n the crcut. Consderng the expermental results on the computaton tme, once the crtcally long target wre s determned, the computaton tme of the OMR s practcally short. Thus, when the ER cannot modfy the netlst well enough to satsfy the specfcatons, the OMR s useful as a logcdesgn level rewrng method collaboratng wth the physcal desgn. 6. CONCLUSION Ths paper proposed an nnovatve method for SPFDbased rewrng, the One-to-Many Rewrng (OMR). Topologcal constrants are not mposed on our OMR, although they are mposed on the exstng methods, the LR, GR and ER. Thus, the OMR provdes wth a more flexble transformaton than the exstng methods. From our expermental results, the OMR provdes wth.2 tmes as flexble transformaton as the exstng rewrng methods presents. By mportng the results on the physcal desgn, such as placement and routng, ths feature makes t easer to remove or replace wres causng long delay wth shorter-delay wres. The OMR s more useful for collaboraton of logc and physcal desgn. We are mplementng t to lnk wth placement and routng tools. 7. REFERENCES [] S.Muroga, Y.Kambayash, H.C.La, J.Nel, Cullney, The Transducton Method - Desgn of Logc Networks Based on Permssble Functons, IEEE Transactons on Computers, Vol.38, No., pp , Dec [2] X. Xang and S. Muroga, Synthess of Multlevel Networks wth Smple Gates, Int l Workshop on LogcSynthess, May [3] S.Yang, LogcSynthess and Optmzaton Benchmarks User Gude Verson 3., MCNC Internatonal Workshop on LogcSynthess, 99. [4] E. Sentovch, et. al., SIS: A System for Sequental Crcut Synthess, Memorandum of No. UCB/ERL M92/4, Dept. of EECS, UC Berkeley, 992. [5] W. Kunz and P. R. Meron, Multlevel Logc optmzaton by mplcaton Analyss, Proc. of Int l Conf. on Computer-Aded Desgn (ICCAD), pp. 6-3, Nov [6] L. A. Entrena and K. -T. Cheng, Combnatonal and Sequental LogcOptmzaton by Redundancy Addton and Removal, IEEE Trans. on CAD of ICS, Vol. 4, No. 7, pp.99-96, Jul [7] S. Yamashta, Y. Kambayash and S. Muroga, Optmzaton Methods for Lookup-Table-Based FPGAs Usng Transducton Method, Proc. of Asa and South Pacfc Desgn Automaton Conf. (ASP-DAC), pp , Aug [8] S. -C. Chang, M. Marek-Sadowska and K.-T Cheng, Perturb and Smplfy: Multlevel Boolean Network Optmzer, IEEE Trans. on CAD of ICAS, Vol. 5, No. 2, pp , Dec [9] Y. -M. Jang, A. Krtc, K. -T. Cheng and M. Marek-Sadowska, Post-layout rewrng for performance optmzaton, In Proc. of Desgn Automaton Conf. (DAC), pp , 997. [] S. -C. Chang, K. -T. Cheng, N. -S. Woo and M. Marek-Sadowska, Postlayout rewrng usng alternatve wres, IEEE Trans. on CAD of ICS, Vol. 6, No. 6, pp , Jun [] R. Huang, Y. Wang and K. -T. Cheng, LIBRA-a lbrary-ndependent framework for post-layout performance optmzaton, In Int l Symposum on Physcal Desgn, pp.35-4, 998. [2] S. -C. Chang, L. V. Gnneken and M. Marek-Sadowska, Crcut Optmzaton by Rewrng, IEEE Trans. on Computers, Vol. 48, No. 9, pp , Sep [3] S. Yamashta, H. Sawada and A. Nagoya, SPFD: A New Method to Express Functonal Flexblty, IEEE Trans. on CAD of ICAS, Vol. 9, No. 8, pp , Aug. 2. [4] J. Cong, Y. Ln and W. Long, SPFD-based Global Rewrng, Proc. of Int l Symposum on Feld Programmable Gate Arrays (FPGA), pp.77-84, Feb. 22. [5] J. Cong, Y. Ln and W. Long, A New Enhanced SPFD-based Rewrng Algorthm, Proc. of Int l Conf. on Computer-Aded Desgn (ICCAD), pp , Nov