DISTRIBUTION GRID STATE ESTIMATION USING LOAD PSEUDOMEASUREMENTS AND TOPOLOGY IDENTIFICATION TECHNIQUES

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1 3 rd Internatonal Conference on Electrcty Dtrbuton Lyon, 5-8 June 5 DISTRIBUTION GRID STATE ESTIMATION USING LOAD PUDOMEASUREMENTS AND TOPOLOGY IDENTIFICATION TECHNIQUES Theto XYGKIS Nolao MANOUSAKIS George KORRES No HATZIARGYRIOU NTUA Greece NTUA Greece NTUA Greece NTUA Greece txgg@hotal.co anoua_n@yahoo.gr gorre@c.ntua.gr nh@power.ece.ntua.gr ABSTRACT Th paper preent a jont tate and topology dentfcaton etaton algorth for dtrbuton grd. Key feature of the algorth are that the networ actve, wth dtrbuted generaton, and nal real-te eaureent are avalable. Due to the lac of real-te eaureent, the propoed approach ung load peudo-eaureent, whch are generated by a load etaton procedure. The developed algorth are thoroughly teted by ung approprate accuracy and perforance ndcator. Sulaton reult, ung data fro a real dtrbuton networ, for dfferent type of eaureent, wth dfferent te reoluton, and dfferent topology confguraton, are reported. INTRODUCTION Lac of real-te eaureent ha been the ot gnfcant ue n dtrbuton grd tate etator [], []. Durng the lat two decade, autoated eterng equpent ha been developed, located and teted n power grd, under actual operatng condton, wth atfactory outcoe. A evoluton of odern eterng yte contnue, dfferent type of technologe and level of ther penetraton are et, thu, new technque of anageent and proceng of avalable eaured data hould be ntroduced wth hgh flexblty and eay applcablty. Generally, the dtrbuton grd tate etator (D) at the top level of the control yte archtecture (HV/MV ubtaton), t nput nforaton beng gathered fro lower level of the archtecture []. In order to obtan content and qualfed tate etate, t neceary to ue a utable tate etaton () algorth [3]-[5] and all nforaton avalable fro dfferent eterng devce. Although voltage agntude and power njecton eaureent fro Dtrbuted Generator (DG) are uually avalable n real te, load eaureent are rarely avalable for all grd node [6]. In [7], htorcal and nonal data, along wth a lted nuber of near-real te eaureent, are proceed to generate load peudo eaureent. Wor [8] preent a Load Etaton (LE) ethod for MV/LV tranforer node, ung real-te load data. Concernng te lag, eaured data are categorzed a real-te, near realte, recent pat and htorcal [9]. In addton to ordnary proce, topology etaton, alo, a vtal functon dtrbuton utlte. The tatu of everal wtchng devce ay be unnown or upcou, due to frequent reconfguraton acton and lted nuber of teleetered data. Effcent technque for topology dentfcaton can be found n the lterature []-[4]. In th paper, a jont tate etaton and topology dentfcaton procedure wll be preented. It ha been developed aung that power flow at the top of the feeder along wth voltage agntude at HV/MV and DG node are the only real-te eaureent avalable. Τhe objectve of th paper to evaluate how load peudo-eaureent contrbute to the adaptablty of Weghted Leat Square (WLS) tate etator and deontrate the ue of a generalzed WLS tate etator for obtanng accurate networ confguraton. The propoed technque developed ung the MATLAB / MATPOWER oftware pacage [5]. It characterzed by plcty and low coputatonal burden and teted on a 374-bu porton of the dtrbuton networ of the Gree land of Rhode. PROBLEM FORMULATION The tate etaton eaureent odel []: z h( x) e () where z the eaureent vector, hx ( ) a vector-valued nonlnear functon of the tate, x the ( n ) true tate vector contng of the n phae angle and n agntude of nodal voltage, e the noe vector (Gauan rando varable wth T Ee () and E( ee ) R dag( σ ), where σ the varance of the th eaureent error), and n the nuber of bue. A WLS tate etator eployed for etatng the tate of the dtrbuton yte, whch aued to be balanced and repreented by the ngle phae odel. The proble forulated a: T n J x zhx ( ) R z hx ( ) () The LE ethod, whch wll cooperate wth the algorth, tae advantage of the lted real-te eaureent avalable, to provde relable load etate and t outlned brefly, a follow. Ung hourly DG generaton and hourly total feeder flow value, hourly power deand curve for the load bue can be obtaned. The general dea to ubtract the contrbuton of DG generaton fro the total feeder flow and get the total power conupton of each feeder a follow: flow DG tot de gen P P P (3) CIRED 5 /5

2 3 rd Internatonal Conference on Electrcty Dtrbuton Lyon, 5-8 June 5 flow Ptot where the power flow etered at the head of the feeder, P de the total power deand of the feeder and the power generaton of DG unt of the feeder. DG Pgen The calculated total hourly power deand allocated aong the et of MV/LV dtrbuton tranforer bue connected to the feeder, by ung the rato obtaned fro tranforer capacte, and gven by: for branch for generator or load P P ( δ,δ,v,v ) l l l Q Q ( δ,δ,v,v ) l l l P Q P l Q l (8) (9) where P NF TC TC P the power deand at node, P tot (4) TC the tranforer capacty at node and NF the nuber of node erved by the feeder. In th way, actve and reactve power conupton etate are generated for all load bue of the feeder on real-te ba and are ued a load peudo-eaureent for the proce. Concernng topology etaton, n order to exane the n/out operaton of a branch and a generator or a load connected at bu, a wtchng devce agned to t and explctly odeled by ntroducng a vrtual zero njecton node l. A probabltc procedure propoed by augentng the tate vector wth the probabltc tatu (contnuou rando varable) ( ) of each wtchng devce l, the power flow P, Q acro each wtchng devce l, and the bu voltage angle δ l and agntude V l of the fcttou node l. In th way the topology (wtchng tatue) wll be etated at the ae te wth analog nforaton. For each wtchng devce l, oft operatonal contrant (peudo eaureent wth oe uncertanty) are ntroduced a follow: +e V V +e l δ l V P e Q e P Q (5) (6) +e (7) where varable, l,, V, V l, V, repreent true value, and varable e repreent rando error. Supercrpt tand ether for anual or eaured value: ( ) for open (cloed) tatu. If the tatu nforaton unavalable, then t condered a unnown or uncertan and the aocated peudo eaureent (7) not ued. Snce node l ha zero njecton, the actve and reactve power flow on wtchng devce l wrtten a []: SIMULATION RESULTS The propoed algorth have been developed by odfyng and extendng MATPOWER [5], whch an open-ource pacage of MATLAB -fle for olvng teady-tate power yte analy proble. All networ and eaureent data are tored n ASCII fle wth the PTI PSS/E raw data forat [5]. Two feeder, fro the radal dtrbuton grd of Rhode land, Greece, are ued a the tet networ. The ulated 374-bu ubnetwor, a part of whch gven n Fg., cont of 54 DG node, ncludng wnd far (WF) and 5 photovoltac (PV), 35 PQ node, node wth capactor and 8 zero njecton (ZI) node. The eaureent et cont of 55 voltage agntude eaureent at the lac bu (real-te) and the DG node (delayed), par of P/Q flow eaureent at lne orgnatng at the lac bu (real-te), 54 par of P/Q njected generaton eaureent (delayed) at DG te, and 8 par of P/Q zero njecton (perfect). Detaled nforaton can be found n [6]. Snce no eaureent of load deand at the 35 P/Q node are avalable, load etate were produced va the propoed technque, aung a loadng level of 9% of the rated tranforer capacty, and a flat power factor of.9, and were ntroduced a peudo eaureent nto tate etator. Baed on etated load and delayed, actual WF and typcal PV daly power generaton curve, hourly power flow oluton were derved for the ret of eaureent. Norally dtrbuted rando error were added at the load flow reult, to ulate the eaured value. For a gven % of axu eaureent error about ean of the th eaureent, t tandard devaton coputed a [3]: error% z error% () 3 3 An error of % for voltage eaureent, 3 for power flow and njecton eaureent, and 5% for load peudo-eaureent, condered. State etaton wa carred out at hourly nterval on daly ba for a whole wee of July 3. The Relatve Percentage Error ( RPE ) deployed to quantfy the error n voltage agntude etate for each bu: ea V V RPE % () ea V ea where V and V et the eaured and etated voltage agntude of the th bu, repectvely. true et CIRED 5 /5

3 3 rd Internatonal Conference on Electrcty Dtrbuton Lyon, 5-8 June 5 Fgure A part of the ulated dtrbuton grd. The varaton of RPE per networ bu dplayed n Fg., where hourly curve of RPE fluctuaton (4 value per day) are plotted. Each curve cont of 374 value (one per bu). A oberved, RPE le n a range of ±%. RPE ( % ) Weey dtrbuton of error n hourly etate of voltage agntude entoned above, all load deand data are peudo eaureent and typcal olar power generaton curve were ued to create hourly PV power generaton value. In general, actual real-te or, even, htorcal data for power njecton at DG bue, lead to lower error than ung peudo eaureent or dervatve data. Table Stattcal reult for weey ulaton. Day Average MAPE per bu type PQ PV WF ZI CP SB Mon Tue Wed Thu Fr Sat Sun Furtherore, four qualty ndce wll be ued for accuracy and perforance evaluaton of the ethodology. The frt qualty ndex the Error Etaton Index ( EEI ), whch an accuracy ndex defned a: true et z z EEI ( ) (3) where true z and z et the true and etated value of the th eaureent, repectvely. It value, dplayed n Fg. 3, vary between 35 and Error Etaton Index (EEI) per hour EEI Bu nuber Fgure Error n etated bu voltage agntude Next, we defne the daly Mean Abolute Percentage Error ( MAPE ) per bu a follow: 4 MAPE RPE, j () 4 j where RPE, j the RPE of the th bu regardng at jth hour. The average value of MAPE per bu type, hown n Table, ndcate that reult are ore accurate nearby WF, capactor ban (CB) and ZI bue. On the contrary, hgher average error are oberved at load and PV bue. WF power generaton are baed on actual eaureent derved fro prevou day data, whle ZI eaureent are treated a perfect data. A 5 5 Fgure 3 Average hourly varaton of EEI Th ndex depend on the nuber of eaureent and the range of value of the tandard devaton. Aung that each eaureent ha a rando Gauan noe of 3σ devaton around the ean, the axu (threhold) value for the ndex EEI would be 3σ EEIax ( ) 9. In our cae, 87 σ eaureent have been ued for the proce, eanng that EEIax , and all tandard devaton are wthn the nterval [.,.]. Obvouly, CIRED 5 3/5

4 3 rd Internatonal Conference on Electrcty Dtrbuton Lyon, 5-8 June 5 the EEI value are very low copared to the threhold value, whch certfe the effcency of the algorth. The perforance of the algorth wa aeed by ean of three ndcator, related to the convergence of the algorth: Mconv obj, Mconv V, Mconv, gven a: Mconv Mconv obj ter J (4) ter J V ax,, n V ter V ter ter ter V ax,, n Mconv (5) (6) where ter denote the ternal teraton of the algorth, J the value of the objectve functon at th teraton, and V, the etated voltage agntude and angle of the th bu per each teraton, repectvely. Indce Mconv obj and Mconv V how alot dentcal varaton per (Fg. 4). Mconv tend to how the ae behavor for about 5% of the cae ( th to 3 th hour). All ndcator have relatvely low value, a t derable. The value of Mconv V ean that the rato of two lat ucceve voltage agntude etate alot one, whle the value of Mconv how that a precon of 3 rd decal pont fulflled concernng voltage angle etaton before the lat oluton teraton. Mconv, of Mconv, δ.5 Mconv, V Convergence PI: objectve functon value (Mconv, of) x -4 Convergence PI: voltage agntude (Mconv, V) 5 5 x -3 Convergence PI: voltage angle (Mconv, δ) Fgure 4 Average hourly varaton of PI Concernng the topology etaton proce, everal topology cae are ulated, aung an error of.5% for CB peudo-eaureent, a uarzed n Table, where the true, aued, and etated wtch tatue are hown. Cae and nvetgate a ultple confguraton change (connecton / dconnecton of load at bu and n / off ervce of DG at bue and 4). Fve fcttou bue, nubered a 3 to 34, are ntroduced n the networ and fve wtchng devce, naely 33, 3, 4 3, 3 34 and 38 3, are condered for wtchng operaton. Abence of bad analog eaureent aued for cae and. For cae 3, a gro error of and 8 added to the true value of actve ( P 33 ) and reactve ( Q 33 ) load peudo eaureent at bu 33. Table Swtchng devce tatue for ulated cae. Cae 3 Swtchng Statu devce True Aued Etated For dentfcaton of bad data, the noralzed redual tet appled []. The three larget noralzed redual for each bad data dentfcaton cycle are reported n Table 3-5, where the frt row gve the tatu of the wtchng devce at the begnnng of each cycle. Noralzed N redual r ˆax 3 correpond to bad data and are hown n bold. A can be oberved, the algorth perfor uccefully the noralzed redual tet, deternng the correct topology confguraton for each cae. CONCLUSIONS Th paper decrbe a copote load, tate, and topology etaton proce for dtrbuton grd characterzed by lac of real-te eaureent and ntene DG penetraton. Α load etaton ethod, whch feed the tate etator wth load peudo eaureent and a probabltc procedure for topology dentfcaton were ued. The advantage of the propoed ethodology that t ple, coputatonally effectve and baed on the wdely accepted WLS etaton. Tet reult ung a 374-bu part of the dtrbuton grd of a Gree land, verfy t perforance. Acnowledgent Th reearch ha been funded fro the European County 7th Fraewor Progra (FP7/7-3) under grant agreeent n the SuSTAINABLE project. CIRED 5 4/5

5 3 rd Internatonal Conference on Electrcty Dtrbuton Lyon, 5-8 June 5 Table 3 Noralzed redual tet for Cae. t nd Mea. r ˆN, Q Q Q 7. Q P 33.7 Q 85.5 Aued tatu Table 4 Noralzed redual tet for Cae. t nd 4th Mea. r ˆN, Q P 8.8 Q 3.6 Q 3.87 P 3.54 Q Aued tatu Table 5 Noralzed redual tet for Cae 3. t nd 4th Mea. r ˆN, P Q 33.9 P Q P 46.6 Q Q 3.89 P Q 3.64 P Q 4.64 Aued tatu REFERENCES [] V. Thornley, N. Jenn, and S. Whte, 5, "State etaton appled to actve dtrbuton networ wth nal eaureent", n Proc. 5-th PSCC Conference, Lege. [] I. Cobelo, A. Shafu, N. Jenn, and G. Strbac, 7, "State etaton of networ wth dtrbuted generaton", Euro. Tran. Electr. Power, vol. 7, -36. [3] R. Sngh, B.C. Pal, and R. A. Jabr, 9, "Choce of etator for dtrbuton yte tate etaton", IET Gener. Tran. Dtrb., vol. 3, [4] O. Chlard, S. Grenard, O. Devaux, L. Garca, 9, "Dtrbuton State Etaton Baed on Voltage State Varable: Aeent of Reult and Ltaton", CIRED, Prague, -4. [5] F. Plo, G. Pano, G. Soa, S. Tedde,, "Ipact of dtrbuton tate etaton n DMS operaton", CIRED, Franfurt, -5. [6] Α. Ghoh, D. Lubean, M. Downey, and R. Jone, 997, "Load odelng for dtrbuton crcut tate etaton", IEEE Tran. Power Del., vol., [7] H. Wang, and N. N. Schulz, 6, "Ung AMR data for load etaton for dtrbuton yte analy", Electrc Power Syte Reearch, vol. 76, [8] T. C. Xyg, G. D. Karl, I. K. Sdera, and G. N. Korre, 4, "Ue of near real-te and delayed art eter data for dtrbuton yte load and tate etaton", 9th MedPower Conference, Athen, Greece. [9] K. Saaraoon, J. Wu, J. Eanayae, and N. Jenn,, "Ue of delayed art eter eaureent for dtrbuton tate etaton", IEEE PES General Meetng, -6. [] A. Montcell, 999, State Etaton n Electrc Power Syte: A Generalzed Approach, Boton: Kluwer Acadec Publher. [] R. Sngh, E. Manta, B. C. Pal, and G. Strbac,, "A recurve Bayean approach for dentfcaton of networ confguraton change n dtrbuton yte tate etaton", IEEE Tran. Power Syt., vol. 5, [] G. N. Korre, and N. M. Manoua,, "A tate etaton algorth for ontorng topology change n dtrbuton yte", IEEE PES General Meetng, San Dego, USA, -7. [3] Y. Sharon, A. M. Annaway, A. L. Motto and A. Charaborty,, "Topology dentfcaton n dtrbuton networ wth lted eaureent", n Proc. IEEE PES ISGT, Wahngton, DC. [4] G. N. Korre, N. D. Hatzargyrou, and P. J. Kata,, State etaton n ult-crogrd, Euro. Tran. Electr. Power, vol., [5] R. Zeran, C. Murllo-Sanchez, and R. J. Thoa,, "Matpower: Steady-tate operaton, plannng and analy tool for power yte reearch and educaton", IEEE Tran. Power Syt., vol. 6, -9. [6] The SuSTAINABLE project, Delverable 3.3: "Advanced Local Dtrbuton Grd Montorng / State Etaton", June, 4. CIRED 5 5/5