Coding and Detection for Multi-track Digital Data Storage

Transcription

1 Coding and Detection for Multi-track Digital Data Storage Tom Conway ECE Dept, University of Limerick, Ireland 1

2 Outline Multi-track Digital Data Storage Detection Coding Performance Conclusions 2

3 Multi-track Digital Data Storage N R rows Multi row track Broad Spiral Read Heads Figure 1: (a) Optical (TwoDOS) (b) Magnetic 3

4 System Under Consideration Storage Medium Read Transducer Read Channel ECC Decode Servo Write Transducer Write Channel ECC Encode User Data User Data 4

5 Multitrack Read Channel r0(t) CTF ADC SRC r1(t) CTF ADC JOINT EQUALIZER SRC JOINT DETECTOR SRC r2(t) CTF ADC SRC r3(t) CTF ADC SRC r4(t) CTF ADC SRC F SAMPLE ADAPTION CONTROL/ Servo a0 k a1 k a2 k a3 k a4 k 5

6 TwoDOS PREAMBLE SYNC DATA Acquire Gain / Offset / Symbol Timing Acquire Bit Allignment Detect User Data Figure 2: TwoDOS Hexagonal 7 row data format 6

7 Parallel Read with multiple (split) beams Figure 3: 2D Intersymbol Interference 7

8 8 H(f_x,f_y) f_y f_x 1 Figure 4: Optical 2D freq response (Braat-Hopkins) Model fc = 2NA λ

9 Data Detection in Presence of 2D ISI Full Viterbi Detection Nstate = 2 2N R N branch/state = 2 N R i.e branches for NR = 7 STATE INPUT 9

10 One Option (2D Partial Response Detection) Equalize to 2D partial response target that is: Similar to channel response More practical for (suboptimal?) detector implementation Two Partial Responses proposed Hexagonal Duobinary Hexagonal Tribinary 10

11 Hexagonal Duobinary H(Dx, Du, Dv) = Du DxDu 1 2Dx D 2 x U or Dv Dv Dx X V 11

12 Hexagonal Duobinary Frequency Response H(f_x,f_y) f_y f_x 1 12

13 13 Fortunately 1+Du+Dv+2Dx+DxDu+DvDx+D 2 x = (1 + Du)(1 + Dv)(1 + Dx) Input Samples MAP -1 MAP π π 1+D v ε{ 0,1...8 } ε { 0,1...4 } 1 1+D u 2-1 Viterbi 1+D x ε ε { 0,1,2 } { 0,1 }

14 Iterative Detector (Soft Output) Input Samples π 1 MAP 1+D v - π -1 1 ε ε { 0,1...8 } π 2 MAP 1+D u - π -1 2 π 3 MAP 1+D x - π -1 3 { 0,1...8 } 14

15 SNR (db) 1E E-06 Ideal Detector Iterative detector Nr=7 Full Viterbi Nr=7 1E-05 BER 1E-04 1E-03 1E-02 1E-01 Coding and Detection for Multi-track Digital Data Storage AWGN Performance 15

16 16 Hexagonal Duobinary Summary Features: Nulls at Nyquist Freq in each direction. Soft Output Iterative detector. Complexity linear in NR. But 9 level output signal and sensitive to equalization and nonlinearities. Complex HW implementation. Detector 1dB loss. Suitable for highest densities.

17 Hexagonal Tribinary H(Dx, Du, Dv) = 1 D x Dv or

18 Hexagonal Tribinary Frequency Response H(f_x,f_y) f_y f_x 1 18

19 Hexagonal Tribinary Detection yr,c = ar,c + ar,c+1 + ar+1,c + nr,c a r,c a r,c+1 y r,c a r+1,c 19

20 20 Apply Sum Product Algorithm Define: F1(ar,c+1, ar+1,c, yr,c) = max( L k 0(ar,c+1) + L k 0(ar+1,c) (yr,c 1.0) 2, L k 0(ar,c+1) + L k 1(ar+1,c) (yr,c 2.0) 2, L k 1(ar,c+1) + L k 0(ar+1,c) (yr,c 2.0) 2, L k 1(ar,c+1) + L k 1(ar+1,c) (yr,c 3.0) 2 ) and F0(ar,c+1, ar+1,c, yr,c) = max( L k 0(ar,c+1) + L k 0(ar+1,c) (yr,c 0.0) 2, L k 0(ar,c+1) + L k 1(ar+1,c) (yr,c 1.0) 2, L k 1(ar,c+1) + L k 0(ar+1,c) (yr,c 1.0) 2, L k 1(ar,c+1) + L k 1(ar+1,c) (yr,c 2.0) 2 )

21 21 Iterate with: L k+1 1 (ar,c) = L k 1(ar,c) + F1(ar,c+1, ar+1,c, yr,c) +F1(ar 1,c, ar 1,c+1, yr 1,c) + F1(ar,c 1, ar+1,c 1, yr,c 1) and L k+1 0 (ar,c) = L k 0(ar,c) + F0(ar,c+1, ar+1,c, yr,c) +F0(ar 1,c, ar 1,c+1, yr 1,c) + F0(ar,c 1, ar+1,c 1, yr,c 1)

22 SNR (db) 1e e-07 Sliding Window Detector Nr=11 Ideal Detector Sum Prod detector Nr=11 Full Viterbi Nr=7 1e-06 BER 1e Coding and Detection for Multi-track Digital Data Storage AWGN Performance 22

23 Hexagonal Tribinary Summary Features: 4 level output signal. Robust to equalization and nonlinearities. Soft Output Iterative detector with good performance. Complexity linear in NR. But No Nulls in Freq Response. Suitable for moderate densities. 23

24 Bit Area (um^2) C/No (db) Hex MLSD Hex Duobinary Iterative Duobinary Hex Tribinary Iterative Tribinary 60 Coding and Detection for Multi-track Digital Data Storage Performance vs Areal Density 24

25 1D Time Varying Trellis 0 0 State N r rows time varying trellis α α 1 α 0 α (2N R +6) 2 states Input Output 2 branches/state 25

26 M-Algorithm Detection Canidate Path 0 Γ λ 0 λ... λ 1 8 λ 0 λ... λ 1 8 Σ Σ 2M metrics Top M Selected Canidate Path 1 Γ Σ Σ /Selector 2M Sorter λ 0 λ... λ 1 8 Γ Canidate Path M 1 Σ Σ 26

27 Experimental Results 27

28 28

29 Software Read Channel ADC Integer Allign Noise Filter Fine Allign VOL EQUALIZE SRC DETECT AGC PRE DET LMS GAIN OFFSET ERR CALC SYSTEM TIMING 29 SYNC

30 Tribinary Architecture with NTT 7 EQ Inputs 8 Eq Outputs Sample Rate Converter 8 Baud Samples Final Detected Bits 7 Input Rows Σ Σ Σ 2D Transform Domain Equalizer τ τ τ Tribinary Partial Resp Detector 7 Detected Bits Acquisition Control Tracking control Threshold Det Control Loops Early Preliminary Decisions Timing Sequencer 8 Errors 30

31 Coding and Detection for Multi-track Digital Data Storage 31 Experimental Perf. 35GB/disc BER Equalized Samples Time Index

32 1E M ber 1E 04 1E 03 Coding and Detection for Multi-track Digital Data Storage ber with Tribinary target and M detector 35GB/disc 32

33 Minimum Phase Equalization

34 1E M 1E 04 ber 1E 03 1E 02 SW FP M alg M alg Min Phase 1E 01 TwoDOS 50GB Performance w. Min Phase M-Detector Coding and Detection for Multi-track Digital Data Storage 34

35 35 Coding Work Require Sector ber of assuming 20Kbit Sector size and outer RS for major defect correction. Inner RS code LDPC Proposed Short Trellis Code + Inner RS code The allowable inner code rate is 0.9.

36 36 A High Rate Trellis Code for 2D Optical Storage Consider the Tribinary channel response: h = Let the channel input be xi,j {0, 1} The channel output yi,j is y = x h with denoting 2 dimensional convolution.

37 37 Let e denote an error event at the channel output e = y ŷ Let ai,j { 1, 0, 1} be the channel error input x ˆx e = a h (1) Minimum distance is d min = 3 with a = ±{1} with the corresponding channel output error event of e = ± 1 1 1

38 A computer search shows : a = ± 0 +1, +1 0, , e = ± {[ have channel output error events of ] [ ] [ , , all of which have a distance of d = 4 38, ] }

39 39 Principle: Design a short high rate soft decision code to detect most likely ( small distance ) events and combine with data detector. EG 1 The use of a single bit parity check code would increase the minimum distance from 3 to 4 or provide a coding gain of approximately 20 log = 1.24dB The rate of such a code is N 1 N

40 EG 2 40 If the 3 weigh 4 events could be detected and avoided, then a higher coding gain of 20 log = 2.22dB could be achieved. (Note that a larger number of weigh 5 error events exist). Proposed Code Consider a tiling of the hexagonal lattice with the tile 1 2 3,

41 Letting the tiling pattern be denoted Ti,j {1, 2, 3}. Note that with this tiling pattern, any three adjacent bits will have a different tiling value.

42 42 Now consider the code C such that a codeword c C if and only if ci,jti,j i j 4 = 0 (2) Given a received code word r which is corrupted with the error a, then ri,jti,j = (ci,j + ai,j)ti,j = ai,jti,j 4 4 i j i j i j 4

43 43 ai,jti,j { ± (1 2) 4, ± (1 3) 4, ± (2 3) 4} 4 sum will have the values Hence for each of the distance 4 input error patterns, the modulo i j i j or ai,jti,j 4 {1, 2, 3} Hence the use of the proposed code allows the detection of all weight 4 input error patterns as well as the single bit error patterns of weight 3.

44 44 Code Rate check bits Hence a code rate R = N 2 N is easily achieved. NB: Defining the code as i j i,jti,j c 4 = 1 with suitable N and NR can also guarantee a k run length constraint.

45 45 1 Decoding the Code Expanding the trellis of the channel state such that each original state has 4 states. Could use Sum Product algorithm. Here used M-algorithm with a time-varying trellis representing the two dimensional channel (M = 16*4 = 64 used here) ( Hard decision output). Alternatively, a post processor type implementations could be applied.

46 1E SNR (db) 1E 05 ber 1E 04 1E 03 Uncoded 22/24 46/48 62/64 78/80 94/96 1E 02 Coding and Detection for Multi-track Digital Data Storage Simulated Performance AWGN bit Error Rate 46

47 1E SNR (db) 1E 05 ver 1E 04 1E 03 Uncoded 22/24 46/48 62/64 78/80 94/96 1E 02 Coding and Detection for Multi-track Digital Data Storage Simulated Performance AWGN Event Error Rate 47

48 Code Rate 1E 05 1E 04 ber 1E 03 1E 02 Disc 5 Disc 3 Disc 4 Disc Dec centered Disc Dec off center Performance on Real data Coding and Detection for Multi-track Digital Data Storage 48

49 Tiled Trellis Code + Interleaved RS TriBinary + Tiled Code Constraint (M algorithm detector) Interleaved RS decoder (255,k) GF(256) N ~ (I =10) Overall Rate =

50 LDPC coding with Tribinary Sum Product Tribinary Detector with SOFT outputs LDPC Decoder N ~ Use Sum Product detector with soft output. 50

51 1E SNR (db) 1E 05 1E 04 ber 1E 03 1E 02 Uncoded RS 4K LDPC 62/64+RS 20K LDPC 20K LDPC itr 1E 01 Simulated Performance AWGN Coding and Detection for Multi-track Digital Data Storage 51

52 1E SNR (db) 1E 05 1E 04 ber 1E 03 1E 02 Uncoded RS 62/64+RS 20K LDPC 20K LDPC itr 1E 01 Simulated Performance + defects 1E-5 Coding and Detection for Multi-track Digital Data Storage 52

53 1E SNR (db) 1E 06 1E 05 ber 1E 04 1E 03 1E 02 Uncoded RS 62/64+RS 20K LDPC 20K LDPC itr 1E 01 Simulated Performance + defects 1E-3 Coding and Detection for Multi-track Digital Data Storage 53

54 Aspect Ratio Options 54

55 Perpendicular Recording line 1 h(x,y) x y Hexagonal Lattice Perpendicular Recording Similar to optical response! 1 55

56 Summary/Conclusions Multi-track Data Storage detection system demonstrated. Number of detection methods proposed. Implementation complexity should be feasible in near future. FPGA demonstrations of some key blocks. Would like to do full channel FPGA demonstrator. Some novel implementation concepts developed. 56

57 Summary/Conclusions (cntd.) Example high rate trellis coded system developed. Comparison with LDPC with AGWN plus defects. Potential for Optical Disc Multi-track Tape Magnetic Disk Holographic (Extend to 3D) 57

58 58 Project Teams (UL) Science Foundation Ireland (SFI) Grant 02/IN.1/I40. Principle Researcher: Tom Conway Academic Staff : Richard Conway Postgraduate Students Sebastien Tosi, Martin Power & Yann Mulero European IST-Project called TwoDOS (Project No. IST ). Principle Researcher: Tom Conway Academic Staff : Richard Conway Postgraduate Students Yann Mulero, Justin Hogan & Patrick Connolly

59 Acknowledgments 59 Some of this work is part of a European IST-Project called TwoDOS (Project No. IST ). All project members (Philips Research, University of Limerick, Eindhoven University of Technology, University of Lancaster, Philips ODTC and HW Communications) are acknowledged for their valuable contributions to this work. In particular: Wim Coene, Andre Immink, Andries Hekstra, Jan Bergmans, Jamal Riani, Steven van Beneden, Alexander van der Lee & Christopher Busch. Philips ODTC and Sony Corp for producing prototype discs. Some of this work is also supported by Science Foundation Ireland (SFI) under the grant 02/IN.1/I40.