A Precorrected-FFT Method for Simulating On-chip Inductance

Transcription

1 A Precorrected-FFT Method for Siulatig O-chip Iductace Haitia Hu, ECE Departet, Uiversity of Miesota, Mieapolis, MN David T. Blaauw, EECS Departet, Uiversity of Michiga, A Arbor, MI 4804 Vladiir Zolotov, Kaushi Gala, Mi Zhao, Rajedra Pada, Motorola, Ic., Austi, TX Sachi S. Sapatear, ECE Departet, Uiversity of Miesota, Mieapolis, MN Abstract The siulatio of o-chip iductace usig PEEC-based circuit aalysis ethods ofte requires the solutio of a subproble where a extracted iductace atrix ust be ultiplied by a curret vector, a operatio with a high coputatioal cost. This paper presets a highly accurate techique, based o a precorrected-fft approach, that speeds up this calculatio. Istead of coputig the iductace atrix explicitly, the ethod exploits the properties of the iductace calculatio procedure while iplicitly cosiderig the effects of all of the iductors i the layout. A optiized ipleetatio of the ethod has bee applied to accurately siulate large idustrial circuits with up to 2,000 iductors ad early 7 billio utual iductive coupligs i about 20 iutes. Techiques for tradig off the CPU tie with the accuracy usig differet approxiatio orders ad grid costructios are also illustrated. Coparisos with a bloc diagoal sparsificatio ethod i ters of accuracy, eory ad speed deostrate that our ethod is a excellet approach for siulatig o-chip iductace i a large circuit.. Itroductio The fast ad accurate siulatio of o-chip iductace is a growig proble as techologies shri further ad low- dielectrics are used to diiish capacitive effects. Iductive effects are iportat i deteriig power supply itegrity ad tiig/oise aalysis, especially for global cloc etwors, sigal buses ad supply grids for high-perforace icroprocessors. Oe of the ajor probles i deteriig iductace has bee associated with the fact that wire iductaces are defied over curret loops, ad that the curret loops are depedet o the circuit cotext of the switchig wires. The partial eleet equivalet circuit (PEEC) odel [] has bee developed to solve this chice-ad-egg proble ad does ot require the curret retur paths to be predeteried. The PEEC approach itroduces the cocept of partial iductace of a wire or a wire seget, correspodig to a retur path at ifiity. The partial selfiductace is defied as the iductace of a wire seget that is i its ow agetic field, while the partial utual iductace is defied betwee two wire segets, each of which is i the agetic field produced by the curret through the other. For two wire segets ad, the partial utual iductace is give by: r r 0 dl dl M v v A dl da dada () I a a µ = = l 4πa a a a l l r where l i ad a i (i= or ) are the legth ad cross sectio area of wire seget i. r is the distace betwee ay two poits o seget ad. A v is the agetic vector potetial alog seget due to the curret I i seget, give by: This research was supported i part by the SRC uder cotract 99- TJ-74 ad by the NSF uder award CCR v µ 0 I v A = (2) 4 dlda πa a l r Here, siplified closed-for forulae for partial self- ad utual iductaces of typical wire topologies that appear i itegrated circuit eviroets are available i [2]. Oe drawbac of usig the PEEC ethod directly is that it results i a dese iductace atrix that causes a high coputatioal overhead for a siulator. Although ay etries i this atrix are sall ad have egligible effects, zeroig the out ay cause the resultig iductace atrix to lose its desirable positive defiiteess property [3], which is a ecessary coditio for the atrix to represet a physically realizable iductor syste. Several efforts have bee ade to sparsify the iductace atrix while aitaiig this property, such as the shift-adtrucate ethod [3,4], retur-liited iductaces [5], bloc diagoal ethod [6] ad K atrix [7,8]. The shortcoigs coo to all of these ethods are twofold. First, all these ethods localize the agetic field by a widow size outside which coupligs ay be igored. The pricipal proble is that it is difficult to defiitively dearcate a regio such that a aggressor wire seget outside this local iteractio regio is too wea to have a sigificat effect o a victi wire seget withi it. Secod, although the idividual coupligs that are igored ay be sall, it is difficult to deterie the cuulative effect of igorig a larger set of such coupligs without ay owledge of the curret distributios. FastHery [9] is a ultipole-accelerated ethod for iductace extractio. However, it wors i frequecy doai ad igores the effects of capacitace o the estiatio of curret retur path. I order to obtai the tie doai siulatio, a accurate copact odel has to be costructed, which is ot a easy procedure. I this paper, we propose a precorrected-fft ethod that, istead of etirely droppig log-rage coupligs, approxiates the, thereby overcoig the two shortcoigs existig i the sparsificatio of iductace atrices. The ai idea of this ethod is to represet the log-rage part of the vector potetial by poit currets o a uifor grid ad earby iteractios by direct calculatios. The grid represetatio perits the use of the discrete Fast Fourier Trasfor (FFT) for fast potetial calculatios. Because of the decouplig of the short ad lograge parts of the potetials, this algorith ca be applied to probles with irregular discretizatios. The basic precorrected-fft ethod preseted i this paper is ispired by the ethod i [0] for capacitace extractio, which also deostrates that for ay realistic structures, the precorrected-fft ethod is faster ad uses less eory copared with the ultipole-accelerated ethod. I our wor, the precorrected-fft ethod is odified to be applied i a differet cotext that is specific to the requireets of siulatio of o-chip iductace, so that this wor is by o eas a ere icreetal iproveet. Ulie [0], we do ot focus o extractig a iductace atrix M, but rather, directly cosider how the iductace atrix is used i fast siulatio algoriths /02/$ IEEE

2 As described i Sectio 2, ay siulators do ot require M to be explicitly deteried, but istead, require the coputatio of the product of M with a curret vector I. The approach developed i this paper accelerates the procedure that is used to directly deterie the M I product without explicitly fidig M. Several cosideratios are icorporated to ae the algorith efficiet ad applicable to large idustrial circuits ad coplicated layouts. First, sice utually perpedicular segets do ot have ay iductive iteractios, it is possible to apply the precorrected-fft ethod to wire segets i the two perpedicular directios separately. This siplificatio is applicable to iductace systes ad ot to capacitace syste. Secod, differet fro the derivatio of 2D itegratio i the capacitace extractio, the applicatio of the precorrected-fft i iductace proble ivolves a coplicated derivatio of 3D itegratio. Sigificat effort has to be ade to obtai the exact ad copact closed for forulae for accurate ad efficiet siulatios. Third, sice IC chips typically have uch larger sizes i the two plaar diesios tha i the third (i.e., they ted to be flat ), we show that a two-diesioal grid ay be used istead of a three-diesioal grid. A coprehesive PEEC odel, as described i [6], is used i this paper. We deostrate the applicatio of the precorrected- FFT ethod withi a siulatio flow based o PRIMA [], o circuits of up to 2,000 iductors i PEEC odel ad early 7 billio utual iductive coupligs. It is the first ipleetatio that icorporates accelerated PEEC approach ad PRIMA to ivestigate idustrial sized probles ad give out tie doai siulatios. These experiets deostrate the speed, eory cosuptio ad accuracy of the precorrected-fft ethod as copared to the bloc diagoal ethod [6], that is a heuristic sparsificatio techique based o a siple partitio of the circuit topology, eglectig utual iductaces betwee partitios.. We also illustrate how tradeoffs ay be ade i order to obtai higher speed ipleetatios with a sall reductio i accuracy. 2. Motivatio ad proble forulatio It is well ow that the basic PEEC odel results i dese iductace atrices. The partial iductaces of a -wire seget syste ca be writte as a syetric, positive seidefiite atrix M R x, which ay be icorporated ito a circuit odel of R, L, C ad active eleets i the circuit. If the circuit is liear, it ca be solved efficietly usig odel order reductio techiques such as AWE [2] or PRIMA. I either ethod, we ust calculate oets, which requires fidig the product of M with a ow curret vector I R x : r r ( A dl da ) = M M2 L L L M I a r r ( ) M M L L L M I A dl da = a2 L L L L L L M M I = = ( 3) M I r M L L L L L r ( ) A dlda L L L L L L M = a M M2 L L L M I r M r ( ) A dl da = a Here, we assue that I is the fictitious curret i seget ad A r is the agetic vector potetial o wire seget due to I ad ca be deteried by the expressios i (2). Each etry M i atrix M is the partial iductace betwee wire seget ad, give by () ad ca be calculated usig epirical [2] or closed for [3] forulae. The th etry i the M I product, correspodig to the victi wire seget, is r r M I = ( A dl da ). It is the suatio of the = = a itegratio of the agetic vector potetial over wire seget caused by the curret i each aggressor wire seget. If the dese iductace atrix M is used, the coputatioal cost for the atrix-vector product is very high: for a syste with variables, this is O( 2 ). The larger the circuit, the larger ay be the uber of oets ad ports, ad the heavier is the overhead of calculatig this atrix-vector product. Therefore, ethods for sparsifyig the M atrix have bee widely uderstood as beig vital to solvig systes with iductaces i a efficiet aer. O closer exaiatio, we observe that i order to solve the circuit, it is ot M that eeds to be calculated, but the product of M with a give curret vector I. This otivates our wor, ad we preset a ethod to efficietly fid the product of M with a give curret vector, usig the precorrected-fft approach to accelerate the coputatio. I this wor, we use PRIMA as the siulatio egie to test the results of the algorith. This algorith ca also be icorporated i tie doai siulators. 3. Precorrected-FFT ethod The detailed explaatio of the precorrected-fft ethod ca be foud i [0] for capacitace extractio. Here, we preset a siple descriptio of this ethod i the agetic field eviroet. The precorrected-fft ethod is based o dividig the regio uder aalysis ito a grid. I the descriptio of the algorith, we will begi by usig a three-diesioal grid, although we will show i the ext sectio that i practice, a twodiesioal grid ca also wor well i a itegrated circuit eviroet. Cosider the three-diesioal topology of wires that represets the circuit uder cosideratio. After the wires have bee cut ito wire segets to be represeted usig the PEEC odel, the circuit ca be subdivided ito a l array of cells, each cotaiig a set of wire segets. The cotributio to the values of r r ( A dl da ) of wire segets withi a cell = a uder cosideratio (the victi cell ) that is caused by wires i other cells (the aggressor cells ) ca be classified ito two categories: log-rage iteractios ad short-rage iteractios. The cetral idea of the precorrected-fft approach is to represet the curret distributio i wire segets i the aggressor cell by usig a sall uber of weighted poit currets o the grid that ca accurately approxiate the vector potetial for faraway victi cells. After this, the potetial at grid poits caused by the grid currets is foud by a discrete covolutio that ca be easily perfored usig the FFT. There are four steps i the precorrected-fft approach to calculate M I:. Projectio: The first step i the precorrected-fft algorith is to costruct the grid projectio operator W. Usig W, the lograge part of the agetic vector potetial due to the curret distributio i a give cell ca be represeted by a sall uber of currets lyig o grid poits throughout the volue of the cell. Thus, the real curret distributio ca be replaced by a set of grid poit currets: I g = WI r (4) where I g ad I r are the grid curret vector ad real curret vector, respectively. The boudary coditio that is aitaied durig

3 projectio is that the vector potetials at a set of test poits o a sphere surroudig the cell should atch the vector potetials due to the actual wires. Sice the grid currets are a represetatio of the real curret distributio, the grid ca be coarser or fier tha the actual proble discretizatio. 2. FFT: Oce the real currets are projected to the grid, the grid potetials due to the grid currets are coputed through a ulti-diesioal covolutio, give by: A g = HI g ( 5) where A g is the grid potetial ad H is the cotributio to the grid potetial iduced by uit poit currets at grid poits. This covolutio ca be calculated very fast by a ulti-diesioal FFT coputatio, which proceeds by autoatically cosiderig all pairs of aggressor-victi cobiatios withi the grid. 3. Iterpolatio: After the grid potetial is calculated usig the FFT, the values of r r ( A dlda ) over victi coductors = a ca be obtaied through iterpolatio of the potetials o grid poits throughout the cell that the victi coductor lies i. This step is basically the iverse process of the projectio step, ad the iterpolatio operator is W T, which is the traspose of the projectio operator ad ca be obtaied by the theore, proved i [0]. 4. Precorrectio: The grid represetatio of the curret distributio i a cell is oly accurate for potetial calculatios that correspod to log-rage iteractios. I practice, earby iteractios have the largest cotributio to the total iduced potetials, ad therefore, these ust be treated directly ad accurately. Sice the earby iteractios have already bee icluded i the potetial calculatio after the above three steps, the last step costructs the precorrectio operator M ~ which subtracts this iaccurate part fro the result of the iterpolatio step before the accurate easure of earby iteractios is added i. Cobiig the above steps, the iduced voltages are: ~ T V = MI = ( M + W HW ) I (6) where W ad M ~ are both sparse atrices, ad H ca also be costructed as a sparse atrix for a efficiet ipleetatio of FFT. Sice VLSI chips are thi ad flat, we choose to use threediesioal grid but with oly oe cell i the ẑ (thicess) directio. There are three paraeters that eed to be deteried before the precorrected-fft algorith is applied to a circuit: p, q ad d. Here, paraeter p is the uber of grid poits o each edge of a cell, while paraeter q is the uber of earby cells which are cosidered i the precorrectio step. The first earest eighbors to each cell are defied as all cells that have a vertex i coo with the cosidered cell, icludig the cell itself. Paraeter d is the cell size, defied as the legth of a edge of a cell i the xˆ ad ŷ directios, which we will tae to be equal. If is the uber of wire segets i the circuit, the coputatioal coplexity of the etire precorrected-fft procedure is O( log ) [0]. If p ad q are fixed, there is a optial cell size that yields the iiu value of cost. I this sese, the ethod for choosig the cell size is soewhat easier ad ore reliable tha the ethods used i [4][6] to fid the local iteractio regio, because i the precorrected-fft ethod, we oly eed to loo for a iiu value of CPU or eory cost ad a cosideratio of accuracy is relatively easier to defie. 4. Experietal results A set of experiets is carried out o a 400MHz Su UltraSparc- II coputer server to test the accuracy of the respose fro the precorrected-fft ethod, ad to copare the results with those of the bloc diagoal ethod [6] i ters of accuracy, speed ad eory cost. The test circuit is a four etal layer coductor structure o layers M6, M7, M8 ad M9 of a ie-layer chip, as illustrated i the top view of the structure i Figure. It lies withi a area whose width is 330µ ad thicess is 5µ. The circuit cosists of three parallel sigal wires, each with 0.8µ width, 0.8µ spacig ad 0.5µ thicess. The power/groud wires are distributed desely i the four layers ad the sigal wires are o M8. The width of the test circuits is fixed throughout the experiets ad the legth chages alog with the legth of the sigal wires i differet experiets. The driver sizes for the three sigal wires are idetical ad are altered with the wire legth i order to set the ear-ed trasitio tie to 40ps. The drivers are ade to switch at the sae tie so that the iductace effect is axiized ad the error icurred by the precorrected- FFT ethod ca be deteried for a worst-case coditio. I the last part of this sectio, the experiets o a large idustrial cloc et are carried out the test the efficiecy of the precorrected-fft ethod i o-chip iductace siulatio. Receivers Dese supply lie distributio Drivers y Chip width Chip legth Three sigal lies x O Figure : Top view of the test chip with three parallel sigal lies o M8. The dar bacgroud represets the dese distributio of supply lies throughout the four etal layers. (Not to scale) 4. Accuracy of the precorrected-fft ethod I these experiets, p is set to 4, ad the earest eighbors ad the ext earest eighbors are icluded i the direct iteractio regio. The cell sizes i the x ad y directio are each chose to be 5µ, while i the thicess directio, it is set to 7µ, such that the test structure is at the ceter of the cell. The radius of the collocatio sphere is chose to be 2.5 ties the cell size. A siulatio for the sae circuit is also carried out with the bloc diagoal approxiatio. The partitio size i the bloc diagoal approach is 80µ 50µ, which is uch larger tha the direct iteractio regio of 75µ 75µ. Figure 2 shows a copariso of the results fro the precorrected-fft ad bloc diagoal ethods with the accurate wavefors for 900µ log wires, showig wavefors at both the driver ad receiver sides of the iddle wire. The accurate wavefors are obtaied by usig the full iductace atrix i PRIMA without ay approxiatio, while the approxiate wavefors usig the precorrected-fft or bloc diagoal ethod with the sae PRIMA siulator. I all the experiets i Sectio 4. ad 4.2, there are 3 ports ad the uber of oets per port i PRIMA ipleetatio is 5, as i [6], ad it has bee deostrated that the respose fro the reduced order odel coverges here eve if ore oets are used i the siulatio.

4 There are six wavefors i Figure 2, although oly four are clearly visible sice the wavefors fro the precorrected-fft alost copletely overlap with those fro the accurate siulatio. The bloc diagoal wavefors at the ear ad far eds are ared (a) ad (b), respectively. The largest error i the respose fro precorrected-fft is less tha V. With about 00V oscillatio agitude iduced by iductace, the relative error of the oscillatio agitude is 0.%. The relative error i the 50% delay for the respose fro precorrected-fft is eve saller. Eve though for a give victi lie seget, ore aggressor lie segets are cosidered i the direct iteractio regio i the bloc diagoal ethod tha i precorrected-fft, the error i the respose fro the forer is still larger tha that of the latter. The reaso for this is that the accuulated errors i the bloc-diagoal approach caused by the dropped utual iductace ters is sigificat. Near ed (a) Far ed (b) Figure 2: Copariso of wavefors fro the precorrected-fft ad the accurate siulatio at the driver ad receiver sides of the iddle wire. Wavefors fro the precorrected-fft ad the accurate siulatio are idistiguishable. Because of the high accuracy that ca be obtaied by the precorrected-fft ethod for this exaple, we observe that we ca sacrifice soe of the accuracy for higher speed. Differet orders of approxiatio are tested to study the relatio betwee speed, eory requireets ad accuracy. The layout tested is siilar to the above experiet but the legth of the sigal wires is exteded to 5400µ, which is the largest tested wire legth, so as to show the largest reductio i accuracy with the coarseig of the grid. Sice there are ore tha 3,000 iductors i this circuit, icludig all of the iductors of sigal wires ad supply wires, early oe billio utual iductaces are required for accurate siulatio. It is therefore ipossible to siulate for the accurate wavefors eve i PRIMA, let aloe i the tie doai, ad the use of a approach such as ours is essetial. To siulate the respose ost accurately, p is set to 4, the cell size is set to be 5µ, ad the first, secod ad third earest eighbors are cosidered i the precorrectio step. The respose obtaied fro this setup ca reasoably be cosidered as accurate. Other precorrected-fft siulatios are carried out with lower accuracy ad a coarser grid, where oly the earest eighbors are cosidered i the direct iteractio regio ad the cell size is 30µ, which is double that i the above experiet. The cell size ad the size of the direct iteractio regio are fixed i these experiets. The grids are variously chose to be threediesioal with p = 4, p = 3, p = 2, ad two-diesioal with p = 4, p = 3, p = 2. The two-diesioal grid is i the plae that is parallel to the x-y plae ad through the poit that correspods to the id-poit of the thicess of the test structure. There is oly oe grid poit i the thicess directio. I the two-diesioal case, the collocatio sphere reduces to a collocatio circle i the x-y plae. It is expected that reducig the proble to 2-D, usig larger cell sizes ad saller values of p, ad reducig the size of the direct iteractio regio will each cotribute to soe loss i accuracy, with a a faster coputatioal speed ad reduced eory requireets. The wavefors obtaied at the driver ad receiver sides of the iddle wire with differet levels of accuracy, correspodig to p = 2, 3 ad 4 are very close ad are ot show here. We fid that the error i the 50% delay is isigificat for the three cases, but the relative error correspodig to the overshoot/udershoot is discerible, ad is listed i the last colu of Table. This table also lists the eory requireets ad speed for each level of approxiatio. The setup tie is the ost tie-cosuig step i the etire algorith, ad is further divided ito two parts. The first part correspods to the calculatio of the iductace values eeded for the costructio of the precorrectio atrix, which is equal for each order of approxiatio, while the secod relates to the tie required for the calculatio of the W, H ad M ~ atrices. For p = 3 uder a 3-D grid, the error at the pea is less tha V. The relative error i the oscillatio agitude at that poit is %, while the speed is icreased by 45% as copared with the accurate result. If p is further reduced to 2 uder a 3-D grid, the error is 9V but the speed is iproved by a additioal 6% copared to the p = 3 case. The 2-D grid represetatio with p = 2 results i the largest error of about 0V ad a siilar relative error, but the speed is icreased oly by 6% as copared to its 3- D couterpart. The reaso for this relatively low iproveet is that i the case of p = 2, the precorrected-fft is rather fast ad the tie cosued i the calculatio of W, H ad M ~ atrices is oly a sall part of the total setup tie, so that eve a large icrease i the speed of calculatio of W, H ad M ~ atrices will ot yield a sigificat reductio of the total ru tie. Aother reaso is that the uber of grid poits per cell is oly reduced by half here by goig fro the three diesios to two. O the other had, if we reduce the 3-D grid to 2-D with p=4, the speed ca be icreased by 22% because the uber of grid poits per cell is reduced fro 4 3 =64 to 4 2 =6, ad the tie required for the calculatio of W, H ad M ~ atrices plays a ore iportat role i the total setup tie. I this case, the accuracy is still high eve uder a 2-D grid. The eory requireets show siilar treds. 4.2 Copariso with the bloc diagoal ethod I this sectio, the eory cosuptio ad speed of these two ethods are copared for structures of differet wire legths, usig a Matlab ipleetatio. Perforace results usig a optiized C++ ipleetatio are reported i Sectio 4.3. The legths of the sigal wires i differet experiets are set to 900µ, 800µ, 3600µ, 4500µ ad 5400µ. The bloc diagoal partitio size is chose to be 80µ 50µ, ad for the precorrected-fft ethod, a 2-D grid is iposed with p=2, ad the first earest eighbors are cosidered for the precorrectio step. The cell size is set to 30µ. Figure 3 shows the wavefors coputed by the two ethods at the receiver ed of the iddle wire for wire legths of 900µ ad 5400µ. The accuracy, eory requireets ad speed for differet wire legths for the bloc diagoal ad precorrected-fft ethods are listed i Table 2. For the wire legths of 900µ ad 800µ, the results of the precorrected-fft ad bloc diagoal ethods are

5 siilar to each other, ad the bloc diagoal ethod is faster. However, as the wire legth icreases, the differeces i the 50% delay ad oscillatio agitude are larger. For exaple, the 50% delay calculated by the precorrected-fft ad bloc diagoal ethods differ by about 5% for a wire legth of 3600µ. The differece icreases to 8% ad 2.5% for legths of 4500µ ad 5400µ, respectively. For wire legths that exceed 800µ, the precorrected-fft ad bloc diagoal ethods perfor their coputatios at approxiately the sae speed, but the forer has early half the eory requireets as the latter sice the partitio size for the bloc diagoal ethod is uch larger tha the direct iteractio regio i the precorrected-fft, due to which the uber of iductaces per wire seget to be calculated by the forer is uch larger tha that for the latter. As the circuit size icreases, the setup tie ad eory are see to icrease at a faster rate for the bloc diagoal ethod. iductace effect is greatly reduced. If the partitio legth is icreased fro 50µ to 300µ ad the to 600µ ad 900µ, with a 330µ partitio width, the overshoot icreases ad ears the result fro the precorrected-fft ethod. It is ipractical to icrease the partitio size further because the siulatio tie for 330µ 600µ partitio is 6hrs, ad icludes 26.6M utual iductaces, while the siulatio tie for 330µ 900µ partitio is 2hrs, ad uses up about 3Gb eory. O the other had, the precorrected-fft ethod requires less tha oe hour ad oly 0MB eory. We also test the sae circuit with a higher level of accuracy i the precorrected-fft ethod with the fifth earest cells icluded i the precorrectio step ad the overshoot is oly 2V differet. The treds i the overshoots ad ru tie fro the two ethods idicate that the precorrected-fft coverges easily, ad therefore is a better cadidate for fast siulatio of large iductive circuits for higher accuracy. The proble faced here by the bloc-diagoal ethod is coo to ost of the existig algoriths i o-chip iductace extractio. As the circuit size is icreased, the local iteractio regio should be larger to aitai the sae accuracy i the siulatio. However, it is hard to predict this iteractio regio a priori, ad for large circuits, icreasig the iteractio regio gradually is ipractical as it could result i very log siulatio ties. The precorrected-fft ethod, o the other had, overcoes this difficulty by icludig the calculatio of far away iductace iteractios usig the grid represetatio. y C A Figure 3: Siulatio results at the receiver side of the iddle wire fro the precorrected-fft ad bloc diagoal ethods for differet wire legths. (a) 900µ, PC-FFT (b) 900µ, bloc diagoal (c) 5400µ, PC-FFT (d) 5400µ, bloc diagoal. Siilar treds are see for the differeces i the oscillatio agitude as for 50% delay. The precorrected-fft ethod predicts a ore reasoable tred i the overshoot agitude for differet wire legths: the overshoot icreases as the wire legth is icreased fro 900µ to 800µ, ad the decreases gradually as the wires grow loger ad resistive effects tae over. However, the tred predicted by the bloc diagoal ethod is differet: the overshoot agitude icreases fro 900µ to 800µ log wires, ad the decreases if the wire legth icreases fro 800µ to 4500µ, as i the case of the precorrected-fft ethod. However, whe the wire legth icreases fro 4500µ to 5400µ, the overshoot is ot reduced but is icreased i the bloc diagoal ethod, which is clearly icosistet with expectatios. The differeces betwee the results fro the two ethods are larger for loger wires. Table 3 lists the overshoots ad the ru tie of the resposes at the receiver side of the 5400µ wire calculated by the precorrected-fft ad bloc diagoal ethods, with differet partitio sizes of 30µ 30µ, 80µ 50µ, 330µ 50µ, 330µ 300µ, 330µ 600µ ad 330µ 900µ. It is clear that the overshoots give by the bloc diagoal ethod do ot coverge as the bloc size is icreased, ad vary soewhat upredictably. Whe the partitio width icreases fro 80µ to 330µ, the 300V bup disappears: the reaso ay be that ore power/groud wires are icluded i each partitio, ad the B 7 8 O Global power/groud grid x Figure 4: Top view of the layout structure of a global cloc et (A: driver iput, B: driver output, C: receiver iput) 4.3. Applicatio of precorrected-fft with optiized ipleetatio o sigal lies ad a large cloc et I additio to a Matlab-based ipleetatio of the precorrected-fft ethod, a optiized versio usig C++ was also ipleeted. To deostrate the efficiecy of the precorrected-fft ethod, layout structures with differet legth of sigal wires, as depicted i Sectio 4.2, ad a large global cloc et of a idustrial giga-hertz icroprocessor are siulated usig this optiized ipleetatio of the precorrected-fft ethod. For layout structures with differet legth of sigal wires, the uber of resistaces, capacitaces ad iductors i circuits ad the total CPU ties of the siulatios i the precorrected- FFT ethod are listed i Table 4. A three-diesioal grid is iposed with p=3, ad the first earest eighbors are cosidered for the precorrectio step. The cell size is set to 30µ. The siulatios i the precorrected-fft ethod ca be very fast. For the circuit with 5400µ sigal wire, which icludes 32.3K resistaces, 64.5K capacitaces ad 32.3K iductors, the total CPU tie is about 6 is. The layout of the cloc et is show i Figure 4 ad has 4 ports, 2 sis ad 2065 iductors, which correspods to 7.3G

6 iductace ters. Usig optiized code that ipleets our ethod, the ru tie for PRIMA to geerate the reduced order odel is 2 iutes usig a three-diesioal grid, ad 2-D precorrected-fft is expected to be eve faster. The resposes fro the siulatio uder the RC odel, the precorrected-fft ad bloc diagoal ethods are show i Figure 5, ad the layout ad experietal paraeters are listed i Table 5. The partitio size i the bloc diagoal ethod ad the direct iteractio regio i the precorrected-fft procedure have approxiately the sae area. O-chip iductace is see strogly affect the respose. The 50% delay fro the precorrected-fft ethod is 30ps, copared with a 86ps delay predicted by the RC odel. Relative to the 50% delay poit for the far ed respose uder a RC-oly odel, the precorrected-fft ethod shows a shift of 7ps, while the shift fro the bloc diagoal ethod is oly 6ps. I additio, the differeces betwee the 0%-90% trasitio tie at the ear ad far ed resposes uder a RC siulatio ad uder the precorrected-fft based siulatio are 53ps ad 70ps respectively, while the correspodig results fro the bloc diagoal ethod are 20ps ad 90ps. Therefore, i this exaple, copared with the precorrected-fft results, the bloc diagoal ethod uderestiates the iductace effect o the trasitio tie at the ear ed by 62% ad overestiates the effect o the trasitio tie at the far ed by 28.5%. B A D F G Figure 5: Resposes fro siulatio uder a RC-oly odel, the precorrected-fft ethod ad the bloc diagoal ethod for the ear ad far eds. A: driver iput wavefor, B ad C: driver output ad receiver iput wavefor, respectively, uder a RColy odel, D ad E: driver output ad receiver iput wavefor, respectively, calculated usig the precorrected-fft ethod, F ad G: driver output ad receiver iput wavefor, respectively, calculated by the bloc diagoal ethod. 5. Coclusio A precorrected-fft algorith for fast ad accurate siulatio of iductive systes is proposed i this paper, i which log-rage copoets of the agetic vector potetial are approxiated by grid currets, while earby iteractios are calculated directly. All iductace iteractios are cosidered i coputig the product of the iductace atrix with a give curret vector, so that the iduced voltages as well as the wavefors at the odes of iterest are calculated accurately. The ethod is deostrated o large circuits ad is show to be faster, less eory itesive C E ad ore accurate tha the bloc diagoal algorith. Differet approxiatios i the ethod, icludig usig a two-diesioal grid structure, are tested ad show that lowerig the order of the approxiatio greatly iproves the speed ad eory cosuptio without a sigificat loss i accuracy. Refereces [] A. E. Ruehli, Iductace Calculatios i a Coplex Itegrated Circuit Eviroet, IBM Joural of Research ad Developet, pp , vol. 6, No. 5, Septeber 972. [2] F. W. Grover, Iductace calculatios: Worig Forulas ad Tables, Dover Publicatios, New Yor, NY, 946. [3] Z. He, M. Celi ad L. T. Pileggi, SPIE: Sparse Partial Iductace Extractio, Proc. of the ACM/IEEE Desig Autoatio Coferece, pp , 997. [4] B. Krauter ad L. T. Pileggi, Geeratig Sparse Iductace Matrices with Guarateed Stability, Proc. of the IEEE/ACM Iteratioal Coferece o Coputer-Aided Desig, pp , Noveber 995. [5] K. L. Shepard ad Z. Ta, Retur-Liited Iductaces: A Practical Approach to O-Chip Iductace Extractio, Proc. of the IEEE Custo Itegrated Circuits Coferece, pp , 999. [6] K. Gala, V. Zolotov, R. Pada, B. Youg, J. Wag ad D. Blaauw, O-Chip Iductace Modelig ad Aalysis, Proc. of the ACM/IEEE Desig Autoatio Coferece, pp , Jue [7] A. Devga, H. Ji ad W. Dai, How to Efficietly Capture O-Chip Iductace Effects: Itroducig a New Circuit Eleet K, Proc. of the IEEE/ACM Iteratioal Coferece o Coputer-Aided Desig, pp , Noveber [8] H. Ji, A. Devga ad W. Dai, KSPICE: Efficiet ad Stable RKC Siulatio for Capturig O-Chip Iductace Effect" Techical Report UCSC-CRL-00-0, Uiversity of Califoria Sata Cruz, Sata Cruz, CA, Available at [9] M. Kao, M. J. Tsu ad J. White, FastHery: A Multipole-Accelerated 3-D Iductace Extractio Progra, Proc. of the ACM/IEEE Desig Autoatio Coferece, pp , Jue 993. [0] J. R. Philips ad J. K. White, A Precorrected-FFT Method for Capacitace Extractio of Coplicated 3-D Structures, Proc. of the IEEE/ACM Iteratioal Coferece o Coputer- Aided Desig, pp , 994. [] A. Odabasioglu, M. Celi ad L. T. Pileggi, PRIMA: Passive Reduced-Order Itercoect Macroodelig Algorith, Proc. of the IEEE/ACM Iteratioal Coferece o Coputer-Aided Desig, pp , 997. [2] L. Pillage ad R.Rohrer, Asyptotic Wavefor Evaluatio for Tiig Aalysis, IEEE Tras. Coputer-Aided Desig, vol. 9, pp , April 990. [3] C. Hoer ad C. Love, Exact Iductace Equatios for Rectagular Coductors with Applicatios to More Coplicated Geootries, J. Res. Nat. Bureau of Stadards, pp , vol. 69C, No. 2, April-Jue 965.

7 Table : A copariso of the accuracy, eory requireets ad CPU tie for differet paraeter settigs for the precorrected-fft i the siulatio of three 5400µ log sigal wires. Here, 2-D ad 3-D correspod to the two-diesioal ad three-diesioal cases, respectively. The total CPU tie correspods to the tie required for the etire siulatio, icludig the tie required by the precorrected- FFT coputatios. Setup tie (s) Total CPU tie (s) Iductace W, H, M ~ Meory requireets Relative error of over/udershoot values atrices (Mb) p=2 2-D % 3-D % p=3 2-D % 3-D <% p=4 2-D <% 3-D <% Table 2: A tabulatio of the accuracy, eory requireets ad CPU tie for differet circuit sizes usig the bloc diagoal (BD) ad precorrected-fft (PCFFT) ethods. The total CPU tie correspods to the tie for the etire siulatio, icludig the tie required by the bloc diagoal or precorrected-fft ethods. Total CPU tie (s) Setup tie (s) Meory requireet (Mb) Relative differeces BD PCFFT BD PCFFT BD PCFFT 50% delay Over/Udershoot 900µ <0.% 4% 800µ % 0.5% 3600µ % 0% 4500µ % 9% 5400µ % >50% Table 3: Overshoots ad ru ties at the receiver side of the iddle wire with the legth of 5400µ fro the precorrected-fft ethod (PCFFT) ad the bloc diagoal ethod (BD) with differet partitio sizes varyig fro 30µ 30µ to 330µ 900µ. BD PCFFT 30µ 30µ 80µ 50µ 330µ 50µ 330µ 300µ 330µ 600µ 330µ 900µ Overshoot 5V 20V 300V 20V 23V 42V 6V Ru tie 297s 68s 3235s 5032s 9700s 6hrs. 2hrs. Table 4: Circuit paraeters ad ru ties for layouts with differet legth of sigal wires fro the precorrected-fft ethod. Legth of sigal wires No. of resistaces No. of capacitaces No. of iductors Total CPU tie (s) 900µ 7.3K 4.7K 7.3K ~ µ 2.3K 24.7K 2.3K µ 22.3K 44.6K 22.3K µ 27.3K 54.6K 27.3K µ 32.3K 64.5K 32.3K 358 Table 5: Layout ad experietal paraeters (X, Y, Z: x, y ad z directios i Figure 4) No. of sis/ports No. of R/L/C No. of M No. of odes Rutie 2/4 60K/2K/400K 7.3G 245K 2is Cell size i X/Y/Z No. of cells i direct No.of grid poits i No. of cells i X/Y No. of collocatio iteractio regio X/Y/Z per cell poits 74.97/74.50/ /3/2 64/64 44