Balance the Battery life and real-time issues for portable Real-time embedded system by applying DVS with battery model

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1 Balance the Battery life and real-time issues for portable Real-time embedded system by applying DVS with battery model Chen Tianzhou, Huang Jiangwei, Xiang Lingxiang, Wu Xinliang Intel Embedded technology Center, College of computer science and technology, Zhejiang University, Hang Zhou, Zhejiang, 3007, P R China Abstract-Power consumption and real-time have been two of the major constraints in the mobile computing system design Much work has been done to study the relationship between power, performance and real time issues Many of existing studies assumed that the energy of the battery is a constant parameter In fact, the energy of the battery is affected by the load current This paper presents a battery model driven power aware real-time software system design In this paper we take the characteristics of battery into account And our work is applying DVS to Hard Real time embedded system with Battery model This new approach is more accurate to reflect the tradeoff between battery life and real-time performance I INTRODUCTION Many wireless and portable devices are driven by the battery In portable system, the electric current, which is generated by the battery, is consumed by the system hardware Power resource has emerged as a major resource constraint in the design of portable systems DVS (Dynamic Voltage Scaling) is one of the effective techniques Usually There are two purposes for applying DVS to real time systems: extern the battery life and reduce the power consumption Many of existing studies assumed that the energy of the battery is a constant parameter But actually, the energy capacity of the battery is affected by the load current The rate capacity effects and recovery effects are two important effects that make battery performance sensitive to the profile of the discharge current These phenomena can significantly affect the battery capacity and the lifetime of it [] A study which does not consider these effects could be misleading in some cases [] In this paper we present method to design a real-time power aware system driven by battery model Our work incorporates the battery behavior model with the DVS technology, and add the battery characteristics into real-time The rest of the paper is organized as follows: In section, we give an overview of related works Section 3 describes how to incorporate the battery model with the DVS technology In section 4, we add the real-time issue into the system design Section 5 presents the experiment setup and the results Finally, we give a summarization in Section 6 II RELATED WORKS A lot of works have been done in order to save the energy dissipated in embedded systems [3, 4, 5, 6] They gave many ideas on how to improve the power efficiency of software There are three areas related to the topic of energy saving There are low power software, low power hardware, and battery modeling In this paper we only care about low power software and battery modeling Several battery models have developed to analyze the battery s discharge behavior [7, 8, 9] These models are using expressions to calculate actual battery capacity and lifetime [] Peukert s formula is one of these models [0] Peukert s α formula states the energy capacity of a battery is C = k/i, where k is a constant determined by the electro-chemical properties, I is the discharge current, and α is a constant which is determined by the electro-chemical properties as the k [0] For ideal battery, the value α equals 0 means the capacity is constant For a real battery, the value of α range up to 07 for most loads [] Many software-based solutions have been implemented to reduce the energy of embedded systems in recent years DPM and DVS are the two primary ways DPM technique has been used to minimize the power consumptions of resources by shut down the devices such as LCD and Disks [,, 3, 4] If resources will not be used any more, the DPM will shut them down to reduce the power consumption Recently many processors support DVS (Dynamic Voltage Scaling) technique DVS achieves CPU power reduction through lowering the core voltage and clock frequency at runtime [5] The DVS technique is more effective than DPM in reducing the power consumption of processors [6] The energy consumed by the processor per clock cycle scales quadratically with the operating voltage Change voltage is more power efficient than DFM In previous paper [], they developed a power metric for

2 embedded system It presented a class of system-level metrics intended to make a systematic study more feasible and it can more accurately reflect the tradeoff between battery life and performance They used the DFM to show the usefulness of their new metric But that paper didn t consider the relationship between CPU frequency and core voltage They assumed that the core voltage would not change when the CPU frequency changed In this paper, we add the relationship between CPU frequency and core voltage to the existing metric which was presented in the paper [] This new metric would help the mobile computing system designers to solve the power consumption constraint We also design a power aware scheduler for real-time system using this metric III BALANCE THE BATTERY LIFE AND PERFORMANCE ISSUE A CPU Power model CPU is built on CMOS circuits So the power consumption of the CPU could be represented by the following equation: Power V DD f C EFF [7] C EFF is the switching capacitance, V DD is the operating voltage and the f is the clock frequency In a DVS enabled processor, if the V DD is determined, the max frequency of CPU could be determined theoretically by the following equation: VDD Vt f [8] max VDD But a real processor does not use this equation to determine the frequency [9] The frequency is approximate to be linearly proportional with the operating voltage, namely f max K f V DD where K f is the proportion factor [9] Many works done before assumed that the processor can change its voltage continuously Actually, most of the commercial processors only provide several power modes: Turbo-mode, Sleep-mode, Run-mode 0, Run-mode, Run-mode n In this study we describe each mode by two parameters: v and f v is the core voltage of processor, and f is the frequency In the Turbo-mode mode, the processor runs at its peak frequency, the power is also at its peak When the processor is in the Sleep-mode, the speed is 0, and we assume the power is 0 We also ignore the speed switching overhead which in general is small There are n different working modes: Run-mode 0, Run-mode Run-mode n Each working mode has different speed and core voltage which means different working mode has different power B The battery life model for the system For a battery, we assume that the current is I, then the α + lifetime of the battery is L = C/(IV) = k/(i V ) If we let the current be I =ni (0<n ), then the lifetime of the battery is ( α + ) ( α + ) ( α + ) L' = ( / n ) k/(i V ) The ratio is L' /L == ( / n ) We assume that the performance of system is P when the current is I, and the performance is P =xp when the current is I The performance here means the amount of work could be completed in the limited time measured in unit And the system s performance would be represented by the CPU frequency If we assume that: the CPU frequency is F when the current is I, and the CPU frequency is F when the current is I Then P /P=x~ F /F The total jobs could be completed in the lifetime is W=PL when the current is I, and W =P L when the current is I Then the ratio of W/W' is W/W =(/x)n -(α+) If we want the new setting is more power-efficient than the old one, W must be bigger than W: (/x)n -(α+) < C Add the DVS factor into the battery life model The current of the whole system can be divided into two components: S and DV DD f [] S is the current that is independent of the CPU frequency f and CPU operating voltage V DD DV DD f is the component that depends on the CPU frequency f and CPU operating voltage V DD So the current of the system is: I = S + DV DD f Then the power of the whole system is: P = V ( S + DV DD f ) Lifetime of the battery could be represented by the following equation: K L = α + V ( S + DVDD f ) ' Let f = nf, than the P /P=n The work ratio ( S + DV f ) W' /W + α + DD = n ' ' α ( S + DVDD f ) fmax K f V DD, and f / n, ' f then S + D VDD K f + W' /W = n ( ) S + n DV K DD f α Using the work ratio ρ = S /( S + D V DD K f ) mentioned in the paper [], then the α + W' /W = n ( ) ρ + n ( ρ ) D Maximize the performance In order to complete as more as possible work in the battery life, we should maximize the value of W' /W When the system has been designed, ρ (0<ρ<) and α (0<α<07) are constants Take the partial derivative to the speedup factor n, and set it to 0, then we could find: n = ( α + )(/ ρ ) Any change on n will result in a decrease in W' /W So the CPU frequency is optimal The system software designer who wants to complete the most work in the battery life would use the equation n = to select an optimal CPU (α + )(/ ρ ) frequency for the system For an ideal battery, α is zero The optimal n is ρ /( ρ) The optimal n is only related to the work ratio But actually, the electro-chemical properties of the battery would impact the selection of the optimal n So if we don t consider the behavior of the battery, there could be some misleading in same cases If the system designers need the system to complete the most work in battery life at the max frequency, we need to find the optimal point for ρ: ( α + ) ρ = This metric could ( α + ) help the hardware designers to evaluate their selection of the electronic components

3 IV OPTIMAL LONG BATTERY LIFE FOR REAL TIME SYSTEM In this section, we consider a set of n periodic or sporadic tasks T= τ 0, τ, τ τ n that have to be scheduled on a single processor with voltage control capabilities Each task τ i in the task set is characterized by a number C i of worst-case execution Time (WCET), a minimum task period P i, and a relative deadline D i P i And for a real time system, every task in the task set should be guaranteed to finish before deadline In this study, we use RM and EDF schedule algorithm to illustrate how to extending battery life by applying DVS to hard real time embedded system with Battery model A Task model We use the well known Liu and Layland periodic task model in our approach [] A task set denoted by T= τ 0, τ, τ τ n- is set of n periodic or sporadic tasks which are periodic, preemptive, and mutually independent A task τ i is characterized by a number C i of worst-case execution Time (WCET), a minimum task period T i, and a relative deadline D i T i As an example, the first task in the task set T= τ 0 (4,30,0), τ (5,40,0), τ (7,60,0), τ 3 (0,80,0) has the worst-case execution Times 4, task period 30 and relative deadline 0 We use the J i,k to denote the kth job of the task τ i J i,k starts at time T i *k and is deadline is D i +T i (k+) For a task set, we can find a lowest common multiple (LCM) H for all the task periods B real time schedule analysis Rate-monotonic scheduling [] is a scheduling algorithm with a static-priority task set RM scheduling algorithm assign the priority of each task according to its period, so that the shorter the period the higher the priority EDF (Earliest-Deadline-First) is a dynamic priority scheduler that sorts tasks by deadlines and always gives the highest priority to the released task with the shortest deadline [3] C Extending the task model In the Liu and Layland periodic task model [] a task τ i is characterized by a number C i of worst-case execution Times (WCETs), a minimum task period T i, and a relative deadline D i In order to add DVS into task model, we add a stretching factor SF i into task model Now a task is defined by four parameters: C i, T i, D i and SF i The stretching factors SF i is used to describe the task execution time stretching For example, a task T q =4,30,0, has the worst-case execution Time 4, task period 30, relative deadline 0, and stretching factors Then task τ q s stretched-worst-case execution Time (swcet) is: C q *SF q =8 The power consumption of a task τ q from time 0 to H is: W i =P i C i SF i H/T i P i is determined by formula 3 So the power consumption of a task set T from time 0 to H is: n W T = W i 0 D The Energy Optimization Problem The worst-case execution cycle for a task is a constant If the execution time for a task is stretched, the frequency will be reduced We define the max CPU frequency is F max, than the frequency needed for the task who s execution time is stretched is: F i = F max /SF i According to the formula, we can determine the core voltage V i =F i /K f In this part, we assume all tasks in task set have the same speed, which means that all tasks have the same stretching factor SF So CPU frequency for all tasks is F=F max /SF, and the core voltage V=F/K f When there is no task running on the CPU, we assume that the power consumption is zero We have proved there is an optimal speedup factor n, if we want the complete as more as possible work in the battery life So the optimal frequency for task set could be selected by speedup factor And the deadline guarantee should be kept We can take the well-known schedulability tests for EDF and RM schedulers By using the extended worst-case computation needs of the tasks, can test for the schedulability at a particular frequency The schedulability test for RM and EDF come from paper 0 And we add an optimal frequency function to select the optimal frequency Fig illustrates the frequency select mechanism RM_TEST and EDF_TEST are used to select the power efficiency frequency And the frequency_select function tries to find the optimal frequency f opt with battery effects The frequency_select function assumed that the processor can change its voltage and frequency continuously Actually, most of the commercial processors only provide several power modes Suppose the processor has four power modes: P 0 (f 0, v 0 ), P (f, v ), P (f, v ), and P 3 (f 3, v 3 ) The f opt may be not in the above power mode list There are many different way to map the f opt to power mode Some researches use upper bound mapping method For example if P i f <f opt <P i+ f, they choose P i+ as the optimal power mode So the power consumed is bigger than optimal power mode In our algorithm we map the f opt to two power models For example if P i f <f opt <P i+ f, we choose P i and P i+ as the optimal power modes And we share the task running time between these two modes We use the follow two formulas to split the task running time: T i+ /P i+ f+ T i /P i f =T/f opt T i +T i+ =T T i is the time CPU running on power mode P i, and T i+ is the time CPU spending on power mode P i+ V EXPERIMENT SETUP AND THE RESULT

4 A Platform introduction The Sitsang Evaluation Platform will serve as an example [0] The Sitsang Evaluation Platform provides a development system for the Intel XScale application-specific processor The PXA55 processor which the Sitsang Table : The possible combinations of the CPU frequency and core voltage CPU frequency Core voltage(v) 99 MHZ MHZ 0 99 MHZ 398 MHZ 3 Table : θ ja and Maximum Power Ratings for the PXA55 Processor θ ja Max Power PXA55 33 /W 3W Evaluation Platform uses is designed for high performance and low power The PXA55 processor supports various CPU frequencies, ranging from 99MHz to 398MHz and core voltage ranging from 08V to 3 V The 4 possible combinations of the CPU frequency and core voltage are listed in Table And the power consumption of the PXA55 is shown in the Table This evaluation board offers a CompactFlash slot, an infrared receiver, a LCD and a slot for Secure Digital memory card The operating system which is used on this evaluation platform is a patched version of the Linux 49 kernel In this experiment, we do our tests with the LCD backlight off and no network connection enabled B Battery life model for the system Table 3: power consumption for the whole evaluation platform CPU Frequency Core Voltage Power Consumption 99 MHZ 085V 0W 99 MHZ 0V 5W 99 MHZ V 38W 398 MHZ 3V 64W The power consumption of the whole evaluation platform, which is read from an oscilloscope, is shown in Table 3 The power of the evaluation platform is calculated as ( Core Voltage ) Watts Suppose the current system operates at the frequency of 398 MHZ, then ρ = S /( S + D V DD K f ) 697/ 64 = 0643 The Evaluation Platform contains An 37 VDC, 500mAh LI-ION type battery So the α of this battery is about 04 If the designers want to know whether other frequencies are more power-efficient, we could calculate the work ratios The work ratio can be calculated as: 4 W' /W = n ( ) n 0357 We could find that the contour plot of the work ratio has an inflexion when n 006 When n 006, decreasing the frequency will decrease the work ratio and increasing the frequency will increase the work ratio When n>006, increasing the frequency will decrease the work ratio The designers then would decide to keep the processor run at the 398MHZ If we use the ideal battery for calculating, the work ratio is W' /W = n ( ) The inflexion of the work n 0357 ratio contour plot is found when n 34 bool EDF_TEST(SF) SF=/(C 0 /P 0 + C /P + C n /P n ); if(sf<) return false; else return true; bool RM_TEST(SF) long sf[n]; for(try T i in task set) sf [i ] = P /( P / P + P / P + P / P ) i i 0 i + SF=min(sf[i]); if(sf<) return false; else return true; frequency_select() if(edf_test(sf) RM_TEST(SF)) return Fmax /SF; optimal_f(f) double n=/ ( α + )(/ ρ ) ; if(f<n*f max ) return n*fmax; else return f; frequency_map(opt_f,tup,tdown, t,fup,fdown) if(opt_f<f0 opt_f>fmax) return -; for(int i=0;i<n;i++) //n is the available frequency number if(opt_f==f i ) return 0; else if(opt_f<f i ) fdown=f i-; fup=f i ; tup=t* (opt_f-fup)/(fdown-fup); tdown=t-tup; return ; Fig Task set level speed decision Suppose that the designers want to choose the optimal static portion of the power consumption when the CPU is running at frequency 398MHZ Then the designers could use the equation (α + ) ρ = to calculate the optimal ρ: (α + ) ρ=0643 It s just a coincidence that the optimal ρ is equal to the ρ calculated at the frequency of 398MHZ for the Evaluation Platform For an ideal battery the optimal ρ is / i i

5 In order to test the useful of the work ratio, we modified the Sitsang board to run in a continuous loop The number of loops executed is measured as the total works completed in the lifetime The numbers of loops were counted by a remote collector An I/O signal will be triggered once by a loop The remote collector gathers this signal to count the numbers of the executed loops The Sitsang board runs the loops until the battery were fully discharged Table 4: The experiment result with the Sitsang evaluation platform Core Voltage 085 V 0 V V 3 V Iterations 79 ± 3067 ± 387 ± 435 ± Experimental work 04 ± 074 ± 094 ± ratio, W /W Ideal work ratio, W /W, ( α = 04) Ideal work ratio, W /W, ( α = 0) The experiment result is shown in the Table 4 The result shows that if we didn t consider the electro-chemical properties of battery, there would be some misleading C Power aware Real-time schedule Table 5: The experiment result with the Sitsang evaluation platform WCET Deadline Period WCET Deadline Period We created a task set by random The task set is shown in the Table 5 The lowest common multiple (LCM) H for this task set is 00 We test the task set during H If we only use the EDF_TEST shown in the Fig to select Fig 3 the power consumption and dispatched times for tasks with DVS and upper and low bound mapping Fig the power consumption and dispatched times for every task using frequency_select method VI CONCLUSION AND SUMMARY This paper presents a new approach to the performance-power trade-off at system level for portable Real-time embedded system by applying DVS with battery model We model the power source using the Peukert s formula, and add the DVS characteristic to the model Then we use this model in real-time system designthe result shows that the work ratio is a good metric for DVS enabled system designing The experiment also shows that not considering the characteristics of the battery can lead designers to make wrong design decisions REFERENCE Fig 4 the power consumption and dispatched times for tasks with DVS and Upper bound mapping optimal frequency for the system, the optimal frequency for this task set is 76477MHZ Using the upper bound mapping the optimal frequency is 99MHZ The power consumption is shown in Fig If we use our frequency_map method, the power consumption for this task set is shown in Fig 3 At last, we add our frequency_select() function into scheduler The speed decision chooses the 398MHZ as the optimal frequency The power consumption and dispatched times for each task is shown in Fig 4 [] Lahiri K, Raghunathan A, Dey S, Panigrahi D Battery-Driven system design: A new frontier in low power design In: IEEE, ed Proc of the ASP-DAC/7th Asia and South Pacific and the 5th Int l Conf on VLSI Design Washington: IEEE Computer Society Press, [] Martin, TL, Balancing Batteries, Power, and Performance: System Issues in CPU Speed-Setting for Mobile Computing 999, The Graduate School In Partial Fulfillment Of The Requirements: Pittsburgh, Pennsylvania p 8 [3] Kistler, T And Franz, M Continuous program optimization: A case study ACM Trans Program Lang Syst 5, 4, [4] Qureshi, MK and YN Patt, Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches, in 39th Annual IEEE/ACM International Symposium on Microarchitecture 006 [5] Vasanth Venkatachalam And Michael Franz, Power Reduction Techniques For Microprocessor Systems ACM Computing Surveys, Vol 37, No 3, September 005, pp [6] Zhuang, X and S Pande, Power-efficient prefetching for embedded processors ACM Transactions on Embedded Computing Systems, 007 6() [7] K C Syracuse and W D K Clark, A statistical approach to domain performance modeling for oxyhalide primary lithium batteries, in Proc Annual Battery Conference on Applications and Advances, 997

6 [8] M Pedram and Q Wu, Design considerations for battery-powered electronics, in Proc Design Automation Conf, pp , June 999 [9] D Rakhmatov and S B K Vrudhula, Time to failure estimation for batteries in portable systems, in Proc Int Symp Low Power Electronics & Design, pp 88 9, Aug 00 [0] Linden, D Handbook of Batteries and Fuel Cells New York: McGraw-Hill, 984 [] V Delaluz, M Kandemir, N Vijaykrishnan, A Sivasubramaniam, andm Irwin Hardware and software techniques for controlling dram power modes IEEE Transactions on Computers, 50():54 73, 00 [] S Irani, S Shukla, and R Gupta Online strategies for dynamic power management in systems with multiple power-saving states Trans on Embedded Computing Sys, (3):35 346, 003 [3] Cai, L and Y-H Lu, Power reduction of multiple disks using dynamic cache resizing and speed control, international symposium on Low power electronics and design, 006 [4] Chen Tianzhou, Huang Jiangwei, Dai Hongjun, The dynamic power management for embedded system with poisson process, Journal of Zhejiang University Science, Vol6A Suppl Aug 005 [5] C Hsu Compiler-Directed Dynamic Voltage and Frequency Scaling for CPU Power and Energy Reduction PhD thesis, Rutgers, The State University of New Jersey, New Brunswick, October 003 [6] H Aydin, R Melhem, D Moss e, and P M Alvarez Determining optimal processor speeds for periodic real-time tasks with different power characteristics In Proceedings of EuroMicro Conference on Real-Time Systems, Jun 00 [7] T Burd and R Brodersen, Energy Efficient CMOS Microprocessor Design, Proc 8th Hawaii Int l Conf on System Sciences, Vol, Jan 995 [8] T Pering, T Burd, and R Brodersen Dynamic voltage scaling and the design of a low-power microprocessor system In ISCA, 998 [9] S Gochman, R Ronen, I Anati, A Berkovits, T Kurts, A Naveh, A Saeed, Z Sperber, and R C Valentine The Intel Pentium M Processor: Microarchitecture and Performance Intel Technology Journal, Volume 07, Issue May 003 [0] Intel CorpSitsang-PXA55 Evaluation Platform Users Guide003 [] J W S Liu Real-time Systems Prentice Hall, 000 [] Liu, CL & Layland, J Scheduling algorithms for multiprogramming in a hard real-time environment, Journal of the ACM 0 (): 46 6, (973) [3] Krishna, c M, and shin, k G Real-time systems Mcgraw-hill, 997 [4] Pillai, P and Shin, K G 00 Real-time dynamic voltage scaling for low-power embedded operating systems In Proceedings of the Eighteenth ACM Symposium on Operating Systems Principles (Banff, Alberta, Canada, October - 4, 00) SOSP '0 ACM, New York, NY, 89-0