Noise Estimation Due To Signal Activity For Capacitively Coupled CMOS Logic Gates

Transcription

1 Noise Estimation Due To Sinal Activit Fo Capacitivel Coupled CMOS Loic Gates Kevin T Tan and Eb G Fiedman Depatment of Electical and Compute Enineein Univesit of Rocheste Rocheste, New Yok Abstact The ect of inteconnect couplin capacitance on neihboin CMOS loic ates divin coupled inteconnections stonl depends upon the sinal activit A tansient analsis of two capacitivel coupled CMOS loic ates is pesented in this pape fo diffeent combinations of sinal activit The uncetaint of the ective load capacitance and popaation dela due to the sinal activit is addessed Analtical expessions chaacteizin the output voltae and popaation dela ae also pesented fo diffeent sinal activit conditions The popaation dela based on these analtical expessions is within % as compaed to SPCE, while the estimated dela nelectin the diffeence between the load capacitances can exceed % The loic ates should be popel sized to balance the load capacitances in ode to minimize an uncetaint in the sinal dela The peak noise voltae on a quiet inteconnection detemined fom the analtical expessions is within % of SPCE 1 ntoduction On-chip couplin noise in VLS cicuits, until ecentl consideed a second ode ect, has become an impotant issue in deep submicomete VLS cicuits [1], [2] With deceasin featue sizes and the aveae lenth of on-chip inteconnections inceasin, the inteconnect capacitance has become compaable to o lae than the ate capacitance [] nteconnections in VLS cicuit ae conductos on dielectic insulation laes The mutual electic field flux between neihboin inteconnect lines esults in a couplin capacitance [4] The couplin (o finin) capacitance inceases if the spacin between the inteconnect lines is educed and/o the aspect atio of the inteconnect thickness-to-width inceases The couplin capacitance ma become compaable to the line-to-ound inteconnect capacitance Theefoe, couplin has emeed as one of the pima issues in evaluatin the sinal inteit of VLS cicuits [5], [6] The impotance of inteconnect couplin capacitances depends upon the behavio of the CMOS loic ates f the loic ates divin the coupled inteconnections ae in tansition, the couplin capacitance can affect the popaation dela and the wavefom shape of the output voltae sinal f one of these loic ates is in tansition and the othe loic ate is quiet, the couplin capacitance can not onl chane the popaation dela of the active loic ate, but can also induce a voltae chane on the quiet line The voltae chane ma cause exta cuent to flow thouh the CMOS loic ate divin the quiet inteconnect line, esultin in additional powe dissipation Futhemoe, a chane in voltae ma cause oveshoots (the sinal ises above the voltae suppl) o undeshoots (the sinal falls below ound) The oveshoots and undeshoots ma cause caie injection o collection within the substate [7] f the voltae chane is eate than the theshold voltae This eseach was suppoted in pat b the National Science Foundation unde Gant No MP , the Semiconducto Reseach Copoation unde Contact No 99-TJ-67, a ant fom the New Yok State Science and Technolo Foundation to the Cente fo Advanced Technolo Electonic main Sstems, and b ants fom Xeox Copoation, BM Copoation, ntel Copoation, Lucent Technoloies Copoation, and Eastman Kodak Compan of the followin loic ates, cicuit malfunctions and excess powe dissipation ma occu n ode to educe both desin cost and time, couplin ects should be estimated at the sstem level The couplin noise voltae on a quiet inteconnect line has been analzed b Shoji usin a simple linea cicuit in [1] The ects of the couplin capacitance have also been addessed b Sakuai usin a esistive-capacitive inteconnect model in [], in which the CMOS loic ates ae appoximated b the ective output esistance and simila inteconnect lines ae assumed An estimate of the peak couplin noise voltae based on a coupled tansmission line model has been pesented b the authos in [9] The nonlinea behavio of the MOS tansistos is nelected in these analses [1], [], [9] The maximum ective load capacitance, ie, the intinsic load capacitance plus two times the couplin capacitance ( ), is tpicall used to estimate the wost case popaation dela of an active loic ate [1], [] n this pape, a tansient analsis of two capacitivel coupled loic ates is pesented based on the sinal activit The inteconnect-to-ound capacitance (o self capacitance) and the ate capacitance of the followin loic stae ae included in the intinsic load capacitance ( o ) An analsis of the in-phase tansition, in which two coupled loic ates tansition in the same diection, demonstates that the ective load capacitances ma deviate fom the intinsic load capacitances if the loic ates and intinsic load capacitances ae diffeent The same conclusion can also be obseved fo an out-of-phase tansition, whee the tansition chanes in the opposite diection, makin the ective load capacitances deviate fom o f one loic ate is active and the othe is quiet, the couplin capacitance ma cause the ective load capacitance of the active loic ate to be less than o when the active loic ate tansitions fom hih-to-low and the quiet state is at loic low (ound) Howeve, if the quiet state is hih ( ), the ective load capacitance of the active loic ate can exceed o f the active loic ate tansitions fom hih-to-low and the quiet state is at loic low, the couplin noise voltae causes the quiet state to dop below ound (undeshoots) Oveshoots occu when the invete tansitions fom low-to-hih and the quiet state is at a loic hih ( ) Oveshoots o undeshoots ma cause cuent to flow thouh the substate, possibl couptin data in dnamic loic cicuits [7] This issue is also of sinificant concen in the loic elements within a bistable latch stuctue [10] Analtical expessions chaacteizin the output voltaes fo each condition ae pesented hee based on an assumption of a fast amp input sinal Dela estimates based on the analtical expessions ae within % as compaed to SPCE, while the estimate based on (o ), (o ), and! (o ) fo in-phase, out-of-phase, and one active tansition can each #" %, $&% %, and $& %, espectivel, if the sinal activit is not consideed The peak noise voltae based on the analtical pediction is within % of SPCE The dependence of the couplin capacitance on the sinal activit is discussed in Section 2 Analtical expessions chaacteizin the ective load capacitance, output voltae, and popaation dela duin an in-phase and out-of-phase tansition ae addessed in Sections and 4, espectivel, as well as a compaison between the analtical estimates and SPCE An analtical expession chaacteizin the couplin noise voltae of a quiet loic ate is pesented fo both step and amp input sinals The accuac of these analtical expessions ae compaed to SPCE in Section 5 Stateies to e-

2 duce the ects of couplin capacitance ae discussed in Section 6, followed ' b some concludin emaks in Section 7 2 Sinal Activit n VLS cicuits, inteconnect lines ae tpicall diven b CMOS loic ates The loic ates divin these inteconnect lines ae capacitivel coupled A cicuit diaam of two capacitivel coupled CMOS invetes is shown in Fi 1(a) (a) (b), - Fiue 1 Cicuit model of two capacitivel coupled invetes (a) A cicuit diaam of two capacitivel coupled CMOS invetes (b) An equivalent cicuit of the two coupled CMOS invetes n ode to simplif this analsis, the inteconnection is modeled as a capacitive load whee includes both ( )/*, the inteconnect capacitance of line 1 and the ate capacitance of includes both the inteconnect - capacitance of line 2 and the ate capacitance of The equivalent cicuit and the cuent diections ae shown in Fi 1(b) The output voltaes of ( )/* and ae and, espectivel The diffeential equations chaacteizin the behavio of this capacitivel coupled sstem ae (&021 (&021!54 76 #<; 9 #>= (1) # ; #>? 9 (2) The ects of the couplin capacitance on the tansient esponse of these two coupled invetes also depend on the behavio of each invete, ie, the sinal activit Thee ae thee possible conditions fo each invete, a hih-to-low tansition, a low-to-hih tansition, and a quiet state in which the output voltae of the invete emains at eithe the voltae suppl ( ) o ound Both the hih-to-low and low-to-hih tansitions ae included in the dnamic tansition f the sinals at the input of each invete ae puel andom and uncoelated, thee ae nine diffeent combinations which can occu fo a sstem composed of two capacitivel coupled invetes These combinations ae listed in Table 1 Assumin equal pobabilit fo each condition, the pobabilit of an in-phase tansition, in which both invetes have the same dnamic tansitions, The pobabilit of an out-of-phase tansition, in which these two invete have diffeent dnamic tansitions, is The pobabilit of no dnamic tansition is $C@BA The Table 1 Combinations of the sinal activit fo a sstem of two capacitivel coupled invetes EDGF EDHF to hih-to-low to Hih-to-low J to low-to-hih o quiet to hih-to-low to Low-to-hih J to low-to-hih o J quiet to hih-to-low J o Quiet J to low-to-hih o J quiet condition in which one invete is quiet and the othe is in tansition has the hihest pobabilit, #@A n the followin analsis, if both invetes ae in tansition, it is assumed that these invetes ae tieed at the same time with the same input slew ate Duin a loic tansition, onl the active tansistos ae consideed in the development of the analtical expessions The MOS tansistos ae chaacteized b the ) LK powe law model in the satuation eion and the ective output esistance in the linea eion [11] n-phase Tansition The in-phase tansition is an optimistic condition in tems of the ect of the couplin capacitance on the popaation dela of a CMOS invete With an in-phase tansition, both invetes ae assumed to tansition in the same diection, fo example, hih-to-low at the output The PMOS tansistos ae nelected based on an assumption of a fast amp input sinal [12] NMOS and NMOS ae the active tansistos in each invete fo this tansition and ma have diffeent eometic sizes The shape of the input sinals divin both invetes is chaacteized b a amp wavefom, EDGF EDHF M N&O 1 Wavefom of the Output Voltae QP P NRO? () An assumption of a fast amp input sinal suppots the assumption that both invetes opeate in the satuation eion duin a complete input tansition When the input voltae exceeds the theshold N&O, both of the NMOS tansistos voltae EST U, ie, N F WVCXZY ae ON and bein opeatin invc the satuation eion Afte the input tansition is completed, the input voltae is fixed at and both of the NMOS tansistos emain in the satuation eion The times at which NMOS and NMOS leave the satuation eion ae N F]_^&` and N F]_^&`, espectivel Fo the condition whee these NMOS tansistos ae not equall sized, NMOS and NMOS ma leave the satuation eion at diffeent times f NMOS leaves the satuation eion fist afte a time N F]_^&`, NMOS opeates in the linea eion and the dain-to-souce cuent can be appoximated b azf 021, whee azf is the ective output conductance Afte N F]_^R`, both of these tansistos opeate in the linea eion Both of the NMOS tansistos ae modeled b the ective output conductances, azf and azf A eneal solution of the output voltaes is obtained b solvin the linea diffeential equations, (1) and (2), with the initial conditions of 9 and Both b9 and b descibed b (6) and (7), espectivel, include the ects of the couplin capacitance and the intinsic load capacitances, and f the atio of is the same as that ie, these MOS tansistos have the same atio of

3 n n t h p p 6 Table 2 Analtical expessions chaacteizin the output voltae fo an in-phase tansition Opeatin eion Output voltae and 4 #hjik [[mlon GsutMvxw\ p\q 2z t tu{ h (4) p q 2l XZY Eik p\q e N F = N&O7f [[mlon GsutMvxw\ 2z t tu{ h (5) p q 2l XZY hji~} L t v } v } t h } } h v } (6) Ei } L t h v } h v } t } } h v } (7) e NRO = NEƒ DHF ]_^&` f #hji h t t sut v 2lon!l XZY z l Gs t [[ v w XZY p\q () Ei t t sut v 2lon!l XZY z l GsZtMv w [[ XZY p\q (9) p m ˆ_ \Š i min p t ˆ_ \Š h7 t ˆ_ \Š (10) p ˆ_ \Š Œ i max p t ˆ_ \Š h t ˆ_ \Š (11) output cuent dive to the coespondin intinsic load capacitance, the couplin capacitance has no ect on the wavefom of and (note that is eliminated fom the expessions fo b and b ) n pactical CMOS VLS cicuits, this condition cannot be satisfied due to the size diffeence amon the MOS tansistos, inteconnect eometic paametes, and ate capacitances of the followin loic staes Theefoe, the couplin capacitance affects the wavefom shape of the output voltaes, 9 and t is theefoe necessa to conside the inteconnect capacitance when deteminin the pope size of the MOS tansistos Assumin cdf is equal to cdf, ie, both NMOS tansistos have the same eometic sizes (o, moe pecisel, output ain), the ective load capacitance of each invete is F F C4 & = (12)? (1) The solid lines shown in Fi 2 depict the atio of F to and the dotted lines epesent the atio of F to The hoizontal axis epesents the atio of to, which chaacteizes the diffeence between the intinsic load capacitances Ratios of the couplin capacitance, to, of?,?, and? Ž ae consideed Note that the deviation of the ective load capacitances fom the intinsic capacitances ( and ) inceases if the diffeence between the intinsic load capacitances inceases The deviation also inceases with inceasin couplin capacitance fo the same atio of R@ Note in Fi 2 that the ective load capacitance of one invete inceases above the coespondin intinsic load capacitance while the ective load capacitance of the second invete dops below the coespondin intinsic load capacitance The deviation of the ective load capacitances fom the intinsic load capacitances esults in diffeent popaation delas 2 Popaation Dela Time A compaison of the popaation dela based on these analtical expessions with SPCE is listed in Table The dela is estimated based on the intinsic load capacitances, and, fo the no couplin condition Note that the eo # of the dela based on the intinsic load capacitance can exceed while the dela based on the analtical equations is within 1% as compaed to SPCE Effective load capacitance (C1/C1, C2/C2) C1/C1 Matched condition C1@Cc/C1=0 C1@Cc/C1=05 C1@Cc/C1=07 C2@Cc/C1=0 C2@Cc/C1=05 C2@Cc/C1=07 C2/C Ratio of the intinsic load capacitances (C2/C1) Fiue 2 The atio of the ective load capacitances, F and F to and, espectivel, fo an in-phase tansition assumin c F c F 4 Out-of-Phase Tansition The out-of-phase tansition has the same pobabilit as the in-phase tansition The out-of-phase tansition is a pessimistic condition in tems of the ect of the couplin capacitance on the popaation dela of a CMOS invete t is assumed that tansitions fom hih-to-low while tansitions fom low-to-hih NMOS and PMOS ae the active tansistos in each invete The initial states of and ae and ound, espectivel 41 Wavefom of the Output Voltae n ode to develop analtical expessions chaacteizin the output voltae, it is assumed that the absolute value of the theshold voltaes of the NMOS and PMOS tansistos ae appoximatel equal n the followin analsis, all of the paametes descibin the PMOS voltaes ae absolute values When is eate than N F, both NMOS and PMOS ae ON and opeate within the satuation eion Note in (14) and (15) that the couplin component Z in (14) causes to decease slowl while the couplin component EFZ in (15) causes to incease slowl The solutions of the out-

4 e t 6 Table Compaison of the in-phase tansition with SPCE Size of nv Load Capacitance SPCE No Couplin Analtic N&O F F N N N N C N N C (ns) ( m) ( m) (pf) (pf) (pf) (ns) (ns) (ns) (ns) % % (ns) (ns) % % Table 4 Analtical expessions chaacteizin the output voltaes fo an out-of-phase tansition Opeatin eion e N F 4 N 6 = N O f e N&O = NEƒ DHF ]_^&` f Output voltae C4 6 and 4 hi } v } tu h 2l l } C h } } h v } (14) i } h v } h l } tu h } } h v } (15) tu hzi t h Gs t v w p\q z t t { h (16) pq 2l XjY hzi s vxw p\q z t { h (17) p\q 2l XZ h i } v } t l l } } } h v } (1) Ei } h v } C l } t } } h v } (19) t i t h t t s t v 2l XjY z l sutmv w XZY p q (20) C i t s v l Xj z l s v w Xj p q (21) p m ˆ_ \Š i min p t ˆ_ \Š h7 p ˆš Š (22) p ˆ_ \Š Œ i max p t ˆ_ \Š h7 p ˆ_ \Š (2) put voltaes, and, ae listed in Table 4 These solutions ae appopiate until one of the two tansistos beins to opeate in the linea eion Assumin EFu is equal to Z, the ective load capacitances of NMOS and PMOS ae F = (24) 4 &6? (25) f is identical to, F and! ae equal to o & The solid lines shown in Fi descibe the atio of F to 9 œ, and the dotted lines depict the atio of F to The hoizontal axis in Fi epesents the atio of to, and atios of to of 0, 05, and 07 ae consideed fo each condition Note that the ective load capacitance of ( ) ma not be equal to ( ) due to the diffeence between the load capacitances t is assumed in this discussion that the situation, 4 > 76 EFZ L ; Z f e o 4 < J6 Z ; EFu f, does not occu This situation can occu if one tansisto has a much hihe output dive cuent than anothe, ie, FZ Ÿž o EFu Z, while is compaable to o Unde this condition, and ma be eate than J o less than ound, pemittin oveshoots o undeshoots to occu When the input sinal eaches at N&O, both NMOS and PMOS continue to opeate in the satuation eion Fo a nonideal condition in which NMOS and PMOS ae not sized equall, NMOS and PMOS ma leave the satuation eion at diffeent times The analsis afte min4 N F]š^&` = N &]_^R` R6 is the same as that of the in-phase tansition 42 Popaation Dela Time A compaison of these analtical expessions with SPCE simulations is listed in Table 5 The dela is estimated based on the intinsic load capacitance plus two times the couplin capacitance, ie, m and 2, espectivel, fo the no couplin condition Note that the eo of the dela based on and can each $&% % while the dela based on the analtical equation listed in Table 4 is within % as compaed to SPCE 5 One nvete is Active and the Othe is Quiet The condition whee one invete is active and the othe is quiet has the hihest pobabilit of occuence f one invete is active and the othe is quiet, the active tansition can induce a voltae chane on the quiet inteconnect line thouh the couplin capacitance The couplin noise voltae ma theefoe seiousl affect

5 c ± ` 4 ) $ `,, a $ 4 ± Table 5 Compaison of the out-of-phase tansition with SPCE Size of nv Load Capacitance SPCE No Couplin Analtic N&O F F N N N N C N N C (ns) ( m) ( m) (pf) (pf) (pf) (ns) (ns) (ns) (ns) % % (ns) (ns) % % Effective load capacitance [C1/(C1+2Cc), C2/(C2+2Cc)] C1/(C1+2Cc) Matched condition C1@Cc/C1=0 C1@Cc/C1=05 C1@Cc/C1=07 C2@Cc/C1=0 C2@Cc/C1=05 C2@Cc/C1=07 C2/(C2+2Cc) Ratio of the intinsic load capacitances (C2/C1) Fiue The atio of the ective load capacitances, F and F to and +, espectivel, fo an out-of-phase tansition assumin cdf cm the cicuit ( )/* behavio and powe dissipation n the followin analsis, ( )/* is assumed to tansition fom hih-to-low while the input of is fixed at Theefoe, the initial voltae of and ae and ound, espectivel When the input voltae exceeds EST, NMOS is ON and stats opeatin in the satuation eion NMOS stats opeatin in the linea eion due to the voltae chane at the output The diffeential equations, (1) and (2), theefoe chane to 4 6 # ; # ; c F 4 N&O ; ST 6 F t = (26) 4 J6 # ; # 9 ; azf = (27) whee N F P P N O Thee ae no tactable solutions to these coupled diffeential equations n ode to deive a tactable solutions, it is theefoe necessa to make cetain simplifin assumptions 51 Step nput Appoximation f the tansition time of the input sinal is assumed to be small as compaed to the dela of the CMOS invetes and the output tansition time, the input can be appoximated as a step input The output voltaes ae J ; c F 4 ; EST 6 F t = (2) ; 4 6 a F c F 4 ; ST 6 F t t 4 $ ; # E ` 6 = (29) whee F 4 &6 azf? (0) The time N F]š^&` when NMOS leaves the satuation eion can be detemined fom (2) b usin a Newton-Raphson iteation Afte N F]_^&`, NMOS opeates in the linea eion The popaation dela of can be appoximated usin (2) and a Newton-Raphson iteation Since the cuent thouh NMOS dischaes the capacito, the popaation dela is less than the dela estimated based on a load of œ Afte N F]_^&`, both of the NMOS tansistos opeate in the linea eion Note that deceases exponentiall in the linea eion The peak noise occus at N F]š^&`, 4ª &«Z 6 ; Jc F 4 JM; SET 6 F t t J t 4 76 azf 4 $ ; E ˆš Š h 6? (1) 52 Appoximation of the Dain-to-Souce Cuent n ode to deive tactable solutions, the dain-to-souce cuent of NMOS can be appoximated usin a second ode polnomial expansion, c F 4 N O J ; SET 6 F t d± d± whee ² q ; V XjY and, V [[ ³² \² = (2), and ae detemined b a polnomial expansion The solutions of the diffeential equations epesented b (26) and (27) ae whee and ; c ²M c ² 4 $ ; c cf N&O F $ 6 = () t Cµ 6 E ` tu = (4) NRO J ; ESET 6 F tz = (5) ; d± ` 4 6 a F 4 6 a F N O ; 4 6 F N O = (6) c ` 4 R6 a F N&O ; 4 76 azf = (7) ç ; 4 6 a F = () whee ` C4 R6 and N F P P N&O Afte the input tansition is completed, NMOS still opeates in the satuation eion The output voltaes ae 2 J ; ; š¹ = (9) ; 4 4 N&O t Rµ 6 6 E ` q = (40)

6 4 ; ) 4 ) Table 6 Compaison of nv1 active and nv2 quiet with SPCE Dela of nv1 Peak voltae of nv2 Size of nv Load Capacitance nitial SPCE No Couplin Analtic SPCE Analtic NRO F F state N N N C (ns) ( m) ( m) (pf) (pf) (pf) of nv2 (ns) (ns) % (ns) % (V) (V) % Low Hih Low Hih Low Hih Low Hih whee º4 ; EST 6 F t FE EST NRO F $ 6 J 6 = (41) š¹ 4 R6 azf cdf C4 J ; ESET 6 F t = (42) 4 6 a F c F 4 J ; SET 6 F t? (4) 4 N&O 6 can be detemined fom (4) N F]_^&` ±7» ¼ and can also be detemined fom (9) usin a Newton-Raphson iteation exhibits an exponential deca when both tansistos opeate in the linea eion Theefoe, the peak couplin noise can be appoximated at N F]_^&` A compaison of the analtical expessions with SPCE simulations is listed in Table 6 The dela is estimated based on the intinsic load capacitance plus the couplin capacitance, ie, # x o, fo the no couplin condition Note that the eo of the dela based on o can each $&% while the dela based on the analtical equation is within % as compaed to SPCE The peak noise based on the analtical expession is within % as compaed to SPCE 6 Minimizin Couplin Effects Couplin ects can be minimized o even eliminated if the cicuit elements ae appopiatel sized fo an in-phase tansition, as discussed in Section 1 An uncetaint can be eliminated when both of the invetes and load capacitances ae the same, ie, cdf cf and d To educe the popaation dela of the coupled invetes, the pobabilit of an out-of-phase tansition should be minimized because of the lae ective load capacitance n ode to minimize an dela uncetaint, all of these cicuit elements should be desined as simila to each othe as possible The couplin noise voltae is popotional to and, as descibed in (1) f the ective output conductance of the quiet invete is inceased, the peak noise voltae can be educed This conclusion suests that the size of the MOS tansistos within the quiet invete should be inceased, contadictin the obsevation fo the popaation dela Theefoe, a tadeoff exists between the peak noise and the popaation dela when choosin the appopiate size of the tansistos fo capacitivel coupled invetes The optimal size of these tansistos is also elated to the sinal activit and othe cicuit constaints 7 Conclusions An analsis of capacitivel coupled CMOS invetes is pesented in this pape The uncetaint of the ective load capacitance and the popaation dela is noted fo both in-phase and out-of-phase tansitions if the cicuit elements ae not sized the same The couplin noise voltae on the inteconnect line diven b the quiet invete is also analzed Finall, some desin stateies ae suested to educe the noise and dela caused b the inteconnect couplin capacitance Refeences [1] M Shoji, Theo of CMOS Diital Cicuits and Cicuit Failues Pinceton Univesit Pess, Pinceton, New Jese, 1992 [2] D Cho, Y S Eo, M Seun, and N Kim, nteconnect Capacitance, Cosstalk, and Sinal Dela fo 05 m CMOS Technolo, Poceedins of the EEE ntenational Electon Devices Meetin, pp , Decembe 1996 [] H B Bakolu, Cicuits, nteconnections, and Packain fo VLS Addison-Wesle Publishin Compan, 1990 [4] S Won et al, nteconnect Capacitance Models fo VLS Cicuits, Solid-State Electonics, Vol 42, No 6, pp , June 199 [5] K Lee, On-Chip nteconnects-giahetz and Beond, Solid State Technolo, No 5-9, Septembe 199 [6] R Patton, The Wa on Noise New Tools Needed to Attack the Noise Poblem in Deep-Submicon Desin, Electonics Jounal, pp 14 17, Octobe 199 [7] W J Bowhill et al, Cicuit mplementation of a 00-MHz 64-bit Second-Geneation CMOS Alpha CPU, Diital Technical Jounal, Vol 7, No 1, pp , 1995 [] T Sakuai, Closed-Fom Expession fo nteconnection Dela, Couplin, and Cosstalk in VLS s, EEE Tansactions on Electon Devices, Vol ED-40, No 1, pp , Janua 199 [9] K T Tan and E G Fiedman, nteconnect Couplin Noise in CMOS VLS Cicuits, Poceedins of the ACM/EEE ntenational Smposium on Phsical Desin, pp 4 5, Apil 1999 [10] E G Fiedman, Latchin Chaacteistics of a CMOS Bistable Reiste, EEE Tansactions on Cicuits and Sstems Fundamental Theo and Applications, Vol 40, No 12, pp , Decembe 199 [11] T Sakuai and A R Newton, A Simple MOSFET Model fo Cicuit Analsis, EEE Tansactions on Electon Devices, Vol ED-, No 4, pp 7 94, Apil 1991 [12] N Hedenstiena and K O Jeppson, CMOS Cicuits Speed and Buffe Optimization, EEE Tansactions on Compute- Aided Desin of nteated Cicuits and Sstems, Vol CAD-6, No 2, pp , Mach 197