On the Escape Routing of Differential Pairs

Transcription

1 On he Escpe Rouing of Differenil Pirs Tn Yn Pei-Ci Wu Qing M Mrin D. F. Wong Synopsys, Inc., Mounin View, CA 943, USA Deprmen of ECE, Universiy of Illinois Urn-Chmpign, Urn, IL 61801, USA Emil: nyn@synopsys.com, peiciwu1@illinois.edu, qingm1@illinois.edu, mdfwong@illinois.edu Asrc As n imporn sep in PCB design, he escpe rouing prolem hs een exensively sudied in lierure. However, few sudies hve een done on he escpe rouing of differenil pirs. In his pper, we sudy he differenil pir escpe rouing prolem nd propose wo lgorihms. The firs one compues he opiml rouing for single differenil pir while he second one is le o simulneously roue muliple differenil pirs considering oh rouiliy nd wire lengh. We hen propose wo-sge rouing scheme sed on he wo lgorihms. Experimenl resuls show h our rouing scheme efficienly nd effecively solves he differenil pir escpe rouing es cses we oined from indusry I. INTRODUCTION As he scle of modern elecronic sysems ecomes lrger nd lrger, he design of prined circui ords (PCBs) ecomes more nd more complex. Nowdys, dense PCB hoss ens of housnds of pins. Mnully rouing such lrge numer of pins, which is wh he indusry hs een doing so fr, is edious nd error-prone jo. Therefore, design uomion of PCB rouing ecomes necessiy. An imporn prolem in PCB rouing is he escpe rouing prolem, which is o roue cerin pins inside pin grid o he oundry of he grid. Mny sudies hve een done on his prolem [1] [8]. Since he ordering of he escpe wires is no considered, we lso cll i he unordered escpe rouing prolem. There re lso sudies on he ordered escpe rouing prolem, in which he escped wires round he grid oundry re required o follow some ordering consrins [9] [13]. Boh ordered nd unordered prolems hve mny pplicions in PCB design. In his pper, we focus on he unordered escpe rouing prolem nd escpe rouing refers o unordered escpe rouing herefer. In PCB designs, high frequency signls re usully rnsmied hrough differenil pirs. A differenil pir is pir of wires rnsmiing wo complemenry signls. Once one signl flips he driver, he oher flips simulneously, resuling in rpid chnge in heir difference. Such differenil signl is hen mplified nd deeced he receiver end. A differenil pir hs he dvnge of higher olernce of ground offses, eer noise immuniy nd higher resisnce o elecromgneic inerference. However, o chieve hese dvnges, he differenil pir mus e crefully roued. They should e roued s close s possile o ech oher so h hey receive he sme noise nd perurion from he This work ws prilly suppored y he Nionl Science Foundion under grn CCF nd grn from he Fujisu Lorories. Fig. 1. An exmple of differenil pir escpe rouing. Pins wih he sme prefix (e.g. 1 nd 1) re differenil pir. Rouing from lck pins re preroued pirs nd re reed s oscles. environmen. A ypicl pin grid on PCB llows wo wiring rcks eween djcen pins. Therefore, we would like he wires of differenil pir o occupy such djcen rouing rcks s much s possile. Figure 1 gives n exmple of differenil pir rouing. I cn e seen h wo wires of differenil pir ry o mee ech oher s soon s possile nd hen sy on djcen rcks fer hey mee. Previous works on escpe rouing [1] [8] did no ke differenil pirs ino considerion. A work on chip-pckgeord codesign y Fng e l. [14] considered differenil pir u i ssumes h he rouing syle is monoonic, which migh no e he cse in mny prcicl designs. If he wo pins of differenil pir re djcen, hen rouing hem would e esy. However, prcicl designs conin differenil pirs wih pins fr pr from ech oher. Figure 2 shows he hisogrms of he disnce eween wo pins of differenil pir in wo indusril ords we hve. I cn e seen h even hough he mjoriy of he differenil pirs hve djcen pins, lrge porion of he differenil pirs sill hve significn disnces eween heir wo pins. Mny of hem hve Mnhn disnce 4 eween heir wo pins. Even such smll disnce cn lredy imply non-rivil prolems. Figure 3 shows such cse. This prolem is difficul o solve if we use he ne-y-ne pproch. If we roue pir {2,2} firs, hen we would roue hem o he righ, locking pir {1,1}. However, if we roue pir {1,1} firs, hen in order o mee s soon s possile, heir roue will cu eween 2 nd 2. Similr issue will lso occur eween pir {2,2} nd //$26.00 IEEE 614

2 % Mnhn disnce % Mnhn disnce Fig. 2. Hisogrms of he disnces eween he wo pins of differenil pir in wo indusril ords. The x-xis is he Mnhn disnce eween he wo pins of differenil pir in erms of pin pich. For exmple, if wo pins re djcen, hen heir disnce is 1 (pich). The y-xis is he percenge of he differenil pirs h hve he corresponding disnce. Noice h design usully hs hundreds of differenil pirs, so even smll percenge mens mny nes Fig. 3. A non-rivil cse. The Mnhn disnce eween ny pir of pins is no lrger hn 4. {3,3}. To solve his kind of prolem, we need n pproch h hs he glol view of ll he differenil pirs. In his pper, we sudy he differenil pir escpe rouing prolem nd propose wo lgorihms. Firs, we propose n lgorihm h compues he opiml roues for single differenil pir. This lgorihm cn e considered s he mze rouer for differenil pir escpe rouing. We hen propose n lgorihm o simulneously roue muliple differenil pirs. I firs compues se of cndide locions for wires of ech differenil pir o mee nd hen uses nework-flow pproch o choose he meeing poin of ech differenil pir from he cndides nd compue he escpe phs from he meeing poin o he grid oundry. Our min-cos mx-flow formulion is le o gurnee h he opiml meeing poin is chosen o mximize he rouiliy while minimizing he wire lengh eween he meeing poins nd he oundry. However, since he cndide locions i compue he firs sep migh no e idel, i my fil o produce good resuls for complex prolems. Therefore, we propose wo-sge rouing scheme sed on he wo lgorihms we propose: Firs, we use he simulneous rouing lgorihm o consruc iniil rouing of ll he differenil pirs. Then, we rip-up nd reroue ech differenil pir using our opiml single pir rouing lgorihm o furher improve he rouiliy nd wire lengh. Experimenl resuls show h our rouing scheme is very powerful in solving prcicl prolems merging ile () doule rck wires single rck wire () spli fer merging Fig. 4. Idel differenil pir escpe rouing () cn e viewed s wo shor single rck wires from he wo pins merging ino doule rck wires. Spliing of he wires fer merging () is illegl. The res of his pper is orgnized s follows: Secion II riefly inroduces he rouing consrins for differenil pirs nd hen formules he differenil pir escpe rouing prolem. Our wo lgorihms re presened in secion III nd secion IV. Secion V gives our overll rouing scheme sed on he wo lgorihms. Experimenl resuls re hen presened in secion VI. Finlly, secion VII gives he concluding remrks. II. BACKGROUND In his secion, we will firs inroduce he rouing consrin of differenil pirs nd hen we will formule he differenil pir escpe rouing prolem nd discuss is mjor difficulies. A. Differenil Pir Rouing Consrin As menioned in he inroducion, we need o crefully roue he differenil pirs in order o ke full dvnge of is enefis. The mos criicl requiremen for differenil pir rouing is h he wo wires need o e roued s close o ech oher s possile. Typiclly, pin grid on PCB hs wo wiring rcks eween djcen pins. So in he conex of escpe rouing, we expec he wo wires from differenil pir o e roued long such djcen rcks s much s possile. Therefore, idel escpe rouing of differenil pir cn e viewed s wo single rck wires from he wo pins merging ino doule rck wires nd sying ogeher ill hey rech he oundry (see Figure 4 ()). We oserve from indusril ords h mnul rouing ll follow his merging syle. We cll he ile where he wo wires merge heir merging ile ( ile is he squre ounded y four djcen pins in he grid). If he escpe rouing of differenil pir follows he ove pern, we cll he rouing legl. Oherwise, if wo wires never merge, or hey merge nd hen spli gin (see Figure 4 ()), we cll he rouing illegl. The mjor ojecive of differenil pir escpe rouing is o find legl rouing such h he single rck rouing lengh is minimized. This is ecuse if he wo wires of differenil pir re no ogeher, he noise hey receive from he environmen migh e differen nd his cn cuse perurion in he differenil signl. On he oher hnd, we lso wn he ol wire lengh o e minimized s well. Therefore, he rouing cos of differenil pir is weighed sum of is single rck rouing lengh nd doule rck rouing lengh wih more weigh on he single rck lengh: cos = s lengh + α d lengh (1) 615

3 s s () () (c) Fig. 5. Rouing single differenil pir. (): rouing grph G D for doule rck wires; hick ph shows he shores ph eween s nd. (): nework grph G S for single rck wires; hick rrows indice he flow resul. (c): rouing resul y comining he resuls of () nd (). Here, s lengh nd d lengh re respecively he lengh of he single rck wires nd doule rck wires nd α is prmeer o conrol he prioriy of single rck wires. For simpliciy, lengh is evlued s he numer of iles he wire rverses. For exmple, for he rouing in Figure 4 (), we hve s lengh = 1 (single rck wire from psses no ile nd single rck wire from psses one ile efore hey mee) nd d lengh = 4 (he doule rck wires pss hrough 4 iles). Therefore, cos = 1 + 4α. If α = 0, only he single rck lengh is considered in he cos. Therefore, y minimizing his cos, we minimize only he single rck rouing lengh. If α = 2, hen we minimize he ol wire lengh. (Rememer doule rck wires conins wo wires, so we need o muliply is lengh y 2 o ge ol wire lengh.) Any vlue eween 0 nd 2 is rde-off eween he ol wire lengh nd he single rck wire lengh. Usully, α is se o e smll consn o minimize he single rck wire lengh in firs prioriy while keeping he ol wire lengh smll. B. Differenil Pir Escpe Rouing Prolem Now wih his cos funcion, we cn formule he differenil pir escpe rouing prolem s follows: Prolem 1. Given k pirs of pins {(1,1),...,(k,k)} in r row y c column pin grid nd se of preroued wires s oscles, he differenil pir escpe rouing (DPER) prolem is o find rouing phs from he pins o he oundry of he grid such h he rouing is legl for every differenil pir nd heir ol cos is minimized. There re wo mjor difficulies of his rouing prolem: 1) Where o merge ech differenil pir is ig issue. The locion of he merging ile ffecs he rouiliy nd lengh of oh he doule rck wires nd he single rck wires. However, if we re deling wih muliple differenil pirs, choosing he es merging locion for one differenil pir my increse he wire lengh of noher differenil pir or even mke i unroule. How o wisely choose he merging iles so h ll he differenil pirs cn e roued nd he ol cos cn e minimized is he key o solving he DPER prolem. 2) Even if we know good merging ile for differenil pir, i is sill difficul o deermine how he single rck wires nd he doule rck wires should e roued. If we roue he single rck wires firs, hen hey ecome oscles for he doule rck wires. Bd rouing of single rck wires my led o longer doule rck wire lengh or even unroule cses. The opposie is lso rue: rouing doule rck wires firs my lso ffec he rouing of single rck wires. How o roue hem so h oh re roule nd heir ol cos in Eq. (1) is minimized is noher key issue. In he nex wo secions, we will presen wo lgorihms. The firs one is le o roue single differenil pir opimlly while he second one uses nework-flow pproch o simulneously roue muliple differenil pirs. The difficulies ove re resolved y he wo lgorihms. III. ROUTING ONE DIFFERENTIAL PAIR Le us firs consider he mos sic cse of he DPER prolem: rouing only one differenil pir. In his secion, we propose n lgorihm h finds he opiml rouing phs for one differenil pir in O(n 2 log n) ime, in which n denoes he ol numer of iles in he grid. For only one differenil pir, finding he es merging ile is no difficul sk ecuse we cn fford o enumere ll O(n) iles o find he es one. However, he second difficuly menioned in he previous secion is sill here. We need o crefully roue he single rck wires nd doule rck wires so h he cos in Eq. (1) is minimized. Suppose we lredy know he merging ile for differenil pir (,) is. We cn hen view he whole rouing s wo prs: (1) single rck wires from nd o nd (2) doule rck wires from o he oundry of he grid. And we compue he wo prs seprely. To compue he doule rck roues, we consruc n undireced rouing grph G D s follows (see Figure 5 ()): Ech empy ile is ssigned ile node. 616

4 Adjcen ile nodes re conneced y edges of cos 1. All he nodes of he oundry iles re conneced o super source s y edges wih cos 0. By compuing shores ph from s o in G D, we cn oin he rouing ph for he doule rck wires. We hen consruc nework grph G S for single rck roues. The grph is consruced s follows (see Figure 5 ()): Ech empy ile is ssigned ile node. Ech ile wih oscle wires re priioned ino regions y hose wires. Ech region is ssigned region node (he smlles nodes in he figure). Undireced edges re dded eween djcen ile/region nodes if here exiss n ville wiring rck eween he wo nodes. All he edges hve cpciy 1 nd cos 1. Noice h in flow-nework, n undireced edge llows flow in oh direcions. Such n edge cn e implemened y wo direced edges nd, oh wih cpciy 1 nd cos 1. To preven he single rck wires from merging efore hey rech, we enforce cpciy 1 on ll ile nd region nodes. Two pin nodes re ssigned o he wo pins of his differenil pir. Direced edges re dded from ech pin node o is four djcen ile/region nodes. These edges hve cpciy 1 nd cos 1. Finlly, we cree super source s nd dd direced edges from i o he wo pin nodes. Ech edge hs cpciy 1 nd cos 0. By compuing he min-cos 2-flow from s o in his nework, we cn oin he rouing phs from he wo pins o he merging ile wih he shores ol lengh. Finlly, we cn comine he shores ph resul of G D (which represens he doule rck wires) nd he min-cos flow resul of G S (which represens he single rck wires) o compose he rouing soluion. In Figure 5, (c) is he resuln rouing soluion y comining he resul of () nd (). Noice h his is he opiml soluion ssuming ile is he merging ile. To oin he glol opiml, we need o enumere ll iles in he grid nd choose he es one. Now le us nlyze he ime complexiy of his lgorihm. Le n e he ol numer of iles in he grid. We cn compue he shores ph lenghs from s o ll ile nodes in G D y Dijksr s lgorihm [15] in O(nlog n) ime ecuse G D conins O(n) nodes nd O(n) edges. For ech possile merging ile, we cn oin he he min-cos 2-flow of G S y compuing he shores ph in he residul grph of G S wice [15]. Agin, since he residul grph of G S conins O(n) nodes nd edges, his cn e done in O(nlog n) ime. We hve o compue he min-cos flow for ll O(n) possile merging iles. So he ol ime complexiy on he flow compuion is O(n 2 log n). Finlly, we need o compre ll O(n) choices. As resul, he ol ime complexiy of our lgorihm is O(nlog n + n 2 log n + n) = O(n 2 log n). Noice h in our lgorihm, we consruc he single rck wires nd doule rck wires independenly wihou considering ech oher. One nurl quesion is wheher he soluion () c Fig. 6. A crossing eween he doule rck wires nd single rck wires () cn e resolved, resuling in even shorer wire lengh (). produced y our lgorihm will hve crossings eween he single rck wires nd he doule rck wires. The following lemm shows h his cnno hppen. Lemm 1. The opiml rouing soluion oined y our lgorihm does no hve wire crossings. Proof: Firs of ll, doule rck wires will no cross hemselves ecuse ny shores ph in G D (which hs nonnegive edge coss) does no hve self-inersecions. Since we enforce uni cpciy on he ile/region nodes in G S, single rck wires cnno hve crossings wih hemselves eiher. Therefore, crossing cn only hppen eween single rck wires nd doule rck wires. Suppose we hve such crossing in our soluion. Wihou loss of generliy, we ssume he single rck wires from he wo pins nd merge ile nd he single rck wire from crosses he doule rck wires ile c s shown in Figure 6 (). By chnging he wo single rck wires o c nd c, we move he merging ile o c nd resolve he crossing (see Figure 6 ()). The new rouing is crossingfree nd hs he sme single rck wire lengh s he originl rouing. Moreover, he doule rck wire lengh is reduced. This mens c is eer merging ile hn. In his cse, our lgorihm will no choose s he opiml soluion nd will choose c insed. Therefore, in he opiml rouing produced y our lgorihm, here exis no wire crossings. Wih he ove lemm nd he opimliy of he shores ph in G D nd he opimliy of he min-cos 2-flow in G S, we hve he following clim: Theorem 1. Our lgorihm compues he legl rouing soluion wih minimum cos for one differenil pir. In prcice, we do no wn he single rck roues o e oo long. Therefore, we cn define smll consn λ s he mximum olerle disnce from he pin o he merging ile. When we enumere he merging iles, we only consider hose wih Mnhn disnce less hn λ o oh pins. By doing his, we cn reduce he ime complexiy down o O(nlog n). The lgorihm we jus presened cn e regrded s he mze rouer for differenil pirs. I cn e used s surouine for more compliced rouing lgorihms. () c 617

5 s () () (c) (d) Fig. 7. Rouing muliple nes. (): rouing grph G S for single rck wires; hick phs show he single wire rouing phs for ech differenil pir. (): nework grph G D for doule rck wires; some edges re omied for clerer illusrion; (c): flow soluion of (). (d): rouing resul y comining he resul of () nd (c). IV. ROUTING MULTIPLE PAIRS For muliple differenil pirs, we cnno fford o enumere ll possile cominions of he merging iles ecuse here re ( n k) of hem (n is he numer of iles nd k is he numer of differenil pirs). In his secion, we presen nework-flow sed lgorihm h simulneously deermines he merging iles for ll differenil pirs. Recll h he primry ojecive is o minimize he single rck wire lengh nd noice h he single rck wires of differenil pir cn e viewed s ph from one pin o he oher pin of he sme differenil pir. (See Figure 4 () for n exmple. Is single rck wires cn e viewed s ph from o vi he merging ile.) Therefore, o minimize he single rck wire lengh, plnning he merging iles long he shores phs eween he wo pins is plusile choice. However, for muliple differenil pirs, we cnno simply use heir shores phs ecuse hey my hve inersecions. This essenilly ecomes generl rouing prolem: find disjoin phs connecing pirs of pins in grid nd minimize he ol lengh of he phs. This prolem hs een sudied exensively nd populr soluions included mze rouer [16], [17] nd negoied congesion sed rouer [18]. In our scheme, we firs consruc n undireced rouing grph G S s follows (see Figure 7 ()): A ile node is ssigned o ech ile h conins no oscles. Two ile nodes re conneced y n edge if heir iles re djcen. Ech differenil pir pin is ssigned pin node. A pin node is conneced o is four djcen ile nodes y four digonl edges (could e less hn four if djcen iles hve oscles). All he edges in G S hve cpciy 1 nd cos 1. We hen pply negoied congesion sed rouer [18] on G S o find disjoin phs connecing he pin pirs wih minimum lengh. In he rouing soluion of he previous sep, ech ph corresponds o he single rck wires of differenil pir nd every ile node long he ph is is cndide merging ile. Our sk now is o choose one merging ile from he cndides for ech differenil pir nd roue doule rck wires from he chosen merging iles o he oundry. Noice h he choices of he merging ile nd he rouing of doule rck wires ffec ech oher s discussed in secion II-B. To oin he glol 618

6 opiml, we use nework-flow pproch o simulneously choose he merging ile nd roue he doule rck wires. We consruc he nework grph G D y he following modificion on he rouing grph G S consruced in he previous sep (see Figure 7 ()): All he undireced edges eween ile nodes remin in G D. These edges hve cpciy 1 nd cos 1. (Recll h n undireced edge llows flow in oh direcions.) The digonl edges eween pin nodes nd heir neighoring ile nodes re removed. For every ile node long he disjoin phs compued in he previous sep (which re cndide merging iles), he edges inciden o i re oriened such h flow cn only flow ou of i. Th is, he undireced edge ecomes direced from he cndide merging ile node o oher nodes. If oh ends of n edge re cndide merging ile nodes, we remove he edge. The purpose is o preven he flow, which represens he doule rck wires, from inersecing wih he roued single rck wires. We inroduce super source s s well s k represenive nodes represening he k differenil pirs. We dd direced edges wih cpciy 1 nd cos 0 from s o ech represenive node nd lso from ech represenive node o he cndide merging ile nodes of he corresponding differenil pir. Finlly, we dd direced edge from every oundry ile node o super sink for ech opening eween wo djcen pins long he oundry (see he dshed edges in he figure). Such edges hve cpciy 1 nd cos 0. These edges collec ll he flows from s h escpe ou of he pin rry nd send hem o. By compuing he min-cos mx-flow [15] of his nework, we cn essenilly choose he opiml merging iles so h he rouiliy of he doule rck wires is mximized nd heir wire lengh is minimized. This resolves he firs difficuly menioned in secion II-B. In Figure 7, (c) shows he flow soluion o he nework in (). Noice h since he flow soluion is for doule rck wires, ech flow represens wo wires occupying djcen rcks. Now we cn comine he rouing soluion in G S h represens single rck wires nd he flow soluion in G D h represens doule rck wires o compose he complee rouing soluion. We do so y rcing disjoin ph compued in G S from is wo end pins unil hey mee he merging ile seleced y he flow lgorihm. Then we merge he wo wires nd follow he flow soluion o he grid oundry. In Figure 7, (d) shows he rouing resul y comining he ph soluion in () nd he flow soluion in (c). V. OVERALL ROUTING SCHEME A. Two-Sge Rouing Scheme One possile issue of he flow-sed lgorihm in he previous secion is h we do no consider he impc of single rck wires on doule rck wires. When we connec he pin pirs, we my produce single rck rouing h locks ler doule rck wires. To overcome his issue, we propose wo sge rouing scheme for he DPER prolem: 1) An iniil soluion for ll differenil pirs is consruced y he simulneous rouing lgorihm presened in secion IV. 2) Then, he single differenil pir lgorihm in secion III is clled o rip-up nd reroue ech differenil pir o improve he rouiliy nd he rouing cos (he comined wire lengh in Eq. (1)). This rouing scheme hs he following dvnges: 1) The firs sge is nework-flow sed. I gurnees opimliy when he single rck rouing is fixed. 2) The rip-up nd reroue lgorihm is le o find he opiml phs for one differenil pir (considering oher differenil pirs s oscles). Therefore, if he iniil rouing sge fils o roue ll he differenil pirs in complex design, he rip-up nd reroue engine is le o efficienly find opiml phs for unroued differenil pirs nd resolve he issue. Moreover, i is lso le o reduce he wire lengh of he iniil rouing produced y he firs sge. Our rouing scheme is shown y experimens o e very effecive nd efficien. B. Single Ne Considerion The es enchmrks we oined from indusry consis of only differenil pir nes. However, one migh wn o roue differenil pirs ogeher wih single nes on some occsions. In his cse, we propose o solve he prolem using negoied congesion sregy sed on our rouing scheme. Firs, we roue he differenil pirs using he wo-sge rouing scheme proposed in he previous susecion. We hen oin he congesion informion from he rouing soluion. Second, we consruc flow nework whose edge coss reflec he congesion informion oined from differenil pir rouing resul. We hen pply he nework-flow lgorihm o oin he rouing resul for single nes. Agin, we cn oin he congesion informion of he single ne rouing. We cn hen repe he firs sep, using such informion o upde he edge cos. By repeing he differenil pir sep nd he single ne sep, he rouing scheme will evenully converge o soluion h is resonle for oh differenil pirs nd single nes. VI. EXPERIMENTAL RESULTS We implemen our rouing scheme in C++ nd es i on es cses derived from indusril d. The experimens re performed on Linux worksion wih 3GHz Inel Xeon CPU nd 4GB memory. Deiled informion ou he es cses s well s he experimenl resuls is shown in Tle I. Noice h he vg. len. column shows he verge numer of iles rversed y single rck wires (ST) nd doule rck wires (DT) of differenil pir. The ls column gives he runime of our lgorihm. From he le, i cn e seen h our rouer cn chieve very shor single rck wire lengh (less hn 1) for ll he 619

7 TABLE I EXPERIMENTAL RESULTS es diff pin grid vg. len. runime cses pir # #row #col ST DT (s) ex ex ex ex ex ex ex ex ex ex minimum rouing cos. The second lgorihm is neworkflow sed lgorihm h simulneously roues muliple differenil pirs. Becuse of is min-cos mx-flow formulion, i is le o chieve mximum rouiliy nd minimum wire lengh of he doule rck wires. The wo lgorihms re hen comined ino rouing scheme h cn effecively nd efficienly solve he DPER prolem. Alhough we ssign uni cos o every ile in our formulion, we could cully ssign ny posiive cos wihou ffecing he opimliy nd effeciveness of our lgorihms. For exmple, we cn le he cos of rversing ile depend on he congesion of he ile. REFERENCES Fig Rouing resul of ex. d, which is idel for differenil pirs. The doule rck wire lengh is lso shor, mening h he ol wire lengh is minimized oo. The overll runime for he es cses is very shor ( few seconds) excep for wo es cses ex7 nd ex. In ex7, he pins of differenil pir re no loced closely, resuling in longer single rck wire lengh nd more compliced rouing perns. Therefore, our rouer spen more ime on i. The pin rry of ex is cully very lrge nd so is he numer of differenil pirs o e roued. One would expec such es cse o e he lrges in rel designs. The rouing resul of ex is shown in Figure 8. I cn e seen h he rouing is very dense, indicing h our rouer is good hndling difficul designs. VII. CONCLUDING REMARKS In his pper, we sudied he differenil pir escpe rouing (DPER) prolem nd proposed wo lgorihms. The firs lgorihm is essenilly he differenil pir version of mze rouer. I compues he roues for differenil pir wih [1] J.-W. Fng, I.-J. Lin, Y.-W. Chng, nd J.-H. Wng, A neworkflow-sed RDL rouing lgorihm for flip-chip design, IEEE Trns. Compuer-Aided Design, vol. 26, no. 8, Aug. 07. [2] J.-W. Fng nd Y.-W. Chng, Are-I/O flip-chip rouing for chippckge co-design, in Proc. In. Conf. on Compuer-Aided Design, 08, pp [3] M.-F. Yu nd W. W.-M. Di, Single-lyer fnou rouing nd rouiliy nlysis for ll grid rrys, in Proc. In. Conf. on Compuer-Aided Design, 1995, pp [4] R. Wng, R. Shi, nd C.-K. Cheng, Lyer minimizion of escpe rouing in re rry pckging, in Proc. In. Conf. on Compuer-Aided Design, 06, pp [5] D. Wng, P. Zhng, C.-K. Cheng, nd A. Sen, A performnce-driven I/O pin rouing lgorihm, in Proc. Asi nd Souh Pcific Design Auomion Conf., 1999, pp [6] M.-F. Yu, J. Drnuer, nd W. W.-M. Di, Inerchngele pin rouing wih pplicion o pckge lyou, in Proc. In. Conf. on Compuer- Aided Design, 1996, pp [7] M.-F. Yu nd W. W.-M. Di, Pin ssignmen nd rouing on singlelyer pin grid rry, in Proc. Asi nd Souh Pcific Design Auomion Conf., 1995, pp [8] T. Yn nd M. D. F. Wong, A correc nework flow model for escpe rouing, in Proc. Design Auomion Conf., 09, pp [9] J.-W. Fng, C.-H. Hsu, nd Y.-W. Chng, An ineger liner progrmming sed rouing lgorihm for flip-chip design, in Proc. Design Auomion Conf., 07, pp [] Y. Kuo nd A. Tkhshi, Glol rouing y ierive improvemens for wo-lyer ll grid rry pckges, IEEE Trns. Compuer-Aided Design, vol. 25, no. 4, Apr. 06. [11], A glol rouing mehod for 2-lyer ll grid rry pckges, in Proc. In. Symp. on Physicl Design, 05, pp [12] Y. Tomiok nd A. Tkhshi, Monoonic prllel nd orhogonl rouing for single-lyer ll grid rry pckges, in Proc. Asi nd Souh Pcific Design Auomion Conf., 06, pp [13] L. Luo nd M. D. F. Wong, Ordered escpe rouing sed on Boolen sisfiiliy, in Proc. Asi nd Souh Pcific Design Auomion Conf., 08, pp [14] J.-W. Fng, K.-H. Ho, nd Y.-W. Chng, Rouing for chip-pckgeord co-design considering differenil pirs, in Proc. In. Conf. on Compuer-Aided Design, 08, pp [15] R. K. Ahuj, T. L. Mgnni, nd J. B. Orlin, Nework Flows: Theory, Algorihms, nd Applicions. Prenice Hll, Fe [16] C. Y. Lee, An lgorihm for ph connecions nd is pplicions, IRE Trnscions on Elecronic Compuers, vol. EC-, no. 2, pp , Sep [17] J. Soukup, Fs mze rouer, in Proc. Design Auomion Conf., 1978, pp [18] L. McMurchie nd C. Eeling, Phfinder: negoiion-sed performnce-driven rouer for FPGAs, in Proc. In. Symp. on Field- Progrmmle Ge Arrys. ACM, 1995, pp