Similar documents
EE 527 MICROFABRICATION. Lecture 25 Tai-Chang Chen University of Washington

EE C245 ME C218 Introduction to MEMS Design Fall 2007

E SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam

Etching Issues - Anisotropy. Dry Etching. Dry Etching Overview. Etching Issues - Selectivity

SUPPLEMENTARY INFORMATION

Regents of the University of California

Reactive Ion Etching (RIE)

EE 527 MICROFABRICATION. Lecture 24 Tai-Chang Chen University of Washington

Etching: Basic Terminology

ETCHING Chapter 10. Mask. Photoresist

Wet and Dry Etching. Theory

CHARACTERIZATION OF DEEP REACTIVE ION ETCHING (DRIE) PROCESS FOR ELECTRICAL THROUGH-WAFER INTERCONNECTS FOR PIEZORESISTIVE INERTIAL SENSORS

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Fall Exam 1

Dry Etching Zheng Yang ERF 3017, MW 5:15-6:00 pm

Development of Lift-off Photoresists with Unique Bottom Profile

4FNJDPOEVDUPS 'BCSJDBUJPO &UDI

EE C245 ME C218 Introduction to MEMS Design

Figure 1 below shows the generic process flow of an LELE method of double patterning.

Section 3: Etching. Jaeger Chapter 2 Reader

Etching Capabilities at Harvard CNS. March 2008

EE C245 ME C218 Introduction to MEMS Design Fall 2007

Lecture 6 Plasmas. Chapters 10 &16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/68

LECTURE 5 SUMMARY OF KEY IDEAS

Tool- and pattern-dependent spatial variations in silicon deep reactive ion etching

Proceedings Silicon Sacrificial Layer Technology for the Production of 3D MEMS (EPyC Process)

EFFECT OF OXYGEN ADDITION ON SIDEWALLS OF SILICON SQUARE MICRO-PIT ARRAYS USING SF 6 BASED REACTIVE ION ETCHING

Numerical Simulation of Bosch Processing for Deep Silicon Plasma Etching


UNIT 3. By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun

Lecture 0: Introduction

Device Fabrication: Etch

Optical Measurements of Critical Dimensions at Several Stages of the Mask Fabrication Process

Advances in Back-side Via Etching of SiC for GaN Device Applications

IC Fabrication Technology

Lecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen

Defining an optimal plasma processing toolkit for Indium Phosphide (InP) laser diode production

Ion Implant Part 1. Saroj Kumar Patra, TFE4180 Semiconductor Manufacturing Technology. Norwegian University of Science and Technology ( NTNU )

EE C245 ME C218 Introduction to MEMS Design Fall 2010

1. Narrative Overview Questions

The Stanford Nanofabrication Facility. Etch Area Overview. May 21, 2013

Title: ASML Stepper Semiconductor & Microsystems Fabrication Laboratory Revision: B Rev Date: 12/21/2010

Mater. Res. Soc. Symp. Proc. Vol Materials Research Society

DQN Positive Photoresist

EE-612: Lecture 22: CMOS Process Steps

3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004

SURFACE TENSION POWERED SELF-ASSEMBLY OF 3D MOEMS DEVICES USING DRIE OF BONDED SILICON-ON-INSULATOR WAFERS INTRODUCTION

Supplementary Information Our InGaN/GaN multiple quantum wells (MQWs) based one-dimensional (1D) grating structures

MICROCHIP MANUFACTURING by S. Wolf

DEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13

CHAPTER 6: Etching. Chapter 6 1

HSG-IMIT Application AG

Lecture 15 Etching. Chapters 15 & 16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/76

CVD: General considerations.

MICROMECHANICAL TEMPERATURE SENSOR

Competitive Advantages of Ontos7 Atmospheric Plasma

Introduction to Photolithography

SUPPLEMENTARY FIGURES

MSN551 LITHOGRAPHY II

Lecture 18: Microfluidic MEMS, Applications

Table of Content. Mechanical Removing Techniques. Ultrasonic Machining (USM) Sputtering and Focused Ion Beam Milling (FIB)

Henri Jansen, Meint de Boer, Rob Legtenberg and Miko Elwenspoek

EE C247B / ME C218 INTRODUCTION TO MEMS DESIGN SPRING 2016 C. NGUYEN PROBLEM SET #4

Plasma Enhanced Chemical Vapor Deposition (PECVD) of Silicon Dioxide (SiO2) Using Oxford Instruments System 100 PECVD

b. The displacement of the mass due to a constant acceleration a is x=

Lithography and Etching

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

Supplementary Figure 1 Detailed illustration on the fabrication process of templatestripped

Chapter 2. The Well. Cross Sections Patterning Design Rules Resistance PN Junction Diffusion Capacitance. Baker Ch. 2 The Well. Introduction to VLSI

NNCI ETCH WORKSHOP - STANFORD NNCI PLASMA ETCH OVERVIEW. Usha Raghuram Stanford Nanofabrication Facility Stanford, CA May 24, 2016

EECS C245 ME C218 Midterm Exam

Chapter 3 Basics Semiconductor Devices and Processing

Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor

Tolerance analysis for comb-drive actuator using DRIE fabrication

ELEC 7364 Lecture Notes Summer Etching. by STELLA W. PANG. from The University of Michigan, Ann Arbor, MI, USA

Modeling of MEMS Fabrication Processes

EE C245 ME C218 Introduction to MEMS Design Fall 2007

MODELING OF T-SHAPED MICROCANTILEVER RESONATORS. Margarita Narducci, Eduard Figueras, Isabel Gràcia, Luis Fonseca, Joaquin Santander, Carles Cané

Lecture 11. Etching Techniques Reading: Chapter 11. ECE Dr. Alan Doolittle

p s s Recombination activity of iron boron pairs in compensated p-type silicon solidi physica status Daniel Macdonald * and An Liu

Plasma Deposition (Overview) Lecture 1

Photolithography II ( Part 1 )

Plasmonic Hot Hole Generation by Interband Transition in Gold-Polyaniline

Ion Implantation. alternative to diffusion for the introduction of dopants essentially a physical process, rather than chemical advantages:

Feature Profile Evolution during Shallow Trench Isolation (STI) Etch in Chlorine-based Plasmas

Simulation and characterization of surface and line edge roughness in photoresists before and after etching

Fabrication Technology, Part I

Figure 1: Graphene release, transfer and stacking processes. The graphene stacking began with CVD

Supplementary Information. Atomic Layer Deposition of Platinum Catalysts on Nanowire Surfaces for Photoelectrochemical Water Reduction

Simulation of Ion Beam Etching of Patterned Nanometer-scale Magnetic Structures for High-Density Storage Applications

UNIVERSITY OF CALIFORNIA. College of Engineering. Department of Electrical Engineering and Computer Sciences. Professor Ali Javey.

Correction of the electric resistivity distribution of Si wafers using selective neutron transmutation doping (SNTD) in MARIA nuclear research reactor

Chapter 7. Plasma Basics

Introduction to Electron Beam Lithography

Lecture 8. Photoresists and Non-optical Lithography

Nanostructures Fabrication Methods

Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications

UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices

Chapter 3 : ULSI Manufacturing Technology - (c) Photolithography

Hydrodynamics of Diamond-Shaped Gradient Nanopillar Arrays for Effective. DNA Translocation into Nanochannels. (Supplementary information)

Transcription:

Citation Bram Lips, Robert Puers, (2016), Three step deep reactive ion etch for high density trench etching Journal of Physics: Conference Series, 757, 012005. Archived version Author manuscript: the content is identical to the content of the published paper, but without the final typesetting by the publisher Published version https://doi.org/10.1088/1742-6596/757/1/012005 Journal homepage http://iopscience.iop.org/journal/1742-6596 Author contact Bram.lips@esat.kuleuven.be, Robert.puers@esat.kuleuven.be your phone number + 32 (0)16327986 (article begins on next page)

Three step deep reactive ion etch for high density trench etching B Lips and R Puers Department ESAT-MICAS, KU Leuven, Kasteelpark Arenberg 10, 3000 Leuven, BE E-mail: bram.lips@esat.kuleuven.be, robert.puers@esat.kuleuven.be Abstract. A three step Deep Reactive Ion Etch (DRIE) process is developed to etch trenches of 10 µm wide to a depth of 130 µm into silicon with an etch rate of 2.5 µm min 1. The aim of this process is to obtain sidewalls with an angle close to 90. The process allows the etching of multiple trenches with high aspect ratios that are closely placed together. A three step approach is used as opposed to the more conventional two step approach in an attempt to improve the etching selectivity with respect to the masking material. By doing so, a simple AZ6632 positive photoresist could be used instead of the more commonly used metal masks which are harder to remove afterwards. In order to develop this process, four parameters, which are the bias power, processing pressure, step times and number of cycles, are evaluated an optimized on a PlasmaPro 300 Cobra DRIE tool from Oxford Plasma Technology. 1. Introduction Deep reactive ion etching (DRIE) is used to create deep, steep sided features in silicon wafers with aspect ratios (etch depth/feature width) beyond 10:1. The technique is developed and licensed by Robert Bosch GmbH [1] and relies on the repeated alternation of isotropic silicon etching and passivation steps to obtain anisotropic profiles. F-based plasmas such as SF 6 are generally used for fast isotropic silicon etching. whereas F-based inhibitor plasmas such as C 4 F 8 are generally used to obtain directionality. Figure 1 shows the general process flow. Classically, the selective removal of the fluorcarbon and the isotropic etching is combined into one step: the etching step. However as indicated by others [2], a higher etch selectivity with respect to the masking material can be obtained by subdividing the etch step in two parts. The first part is then optimized towards selective removal of the fluorcarbon film deposited at the bottom of the trench, whereas the second part is optimized towards fast isotropic etching. This gives rise to a so called three step DRIE process. Such a process is a big advantage when used in combination with CMOS processing. Because of the higher etch selectivity with respect to the masking material, photoresists can now be used as masking material even for through wafer trenches and holes. This in contrast to the more conventional materials used for that, such as oxides or metals, which are harder to remove afterwards without damaging useful oxides or metals in the CMOS stack underneath. The main considerations when developing a DRIE process include side-wall verticality, bottom roughness and etching rate of both silicon and masking material. All of these are affected by process parameters such as plasma power, pressures, gas flows, bias power, cycle times and substrate cooling. This is a wide set of processing parameters that are all interconnected and

(a) (b) (c) (d) Silicon Photoresist Fluorcarbon Figure 1. DRIE process. (a)isotropic silicon etch. (b)fluorcarbon film deposition. (c)selective fluorcarbon film removal. (d)isotropic Silicon etch. thus need careful optimization for each specific etching job. This paper will mainly focus on four of these parameters, which are bias power, processing pressure, step times and number of cycles. All the experiments are conducted on a PlasmaPro 300 Cobra DRIE tool from Oxford Plasma Technology. 2. Experimental details For the experiments, 500 µm thick <100>boron doped Si-wafers with a resistivity of 10-20 W cm are used. These are spincoated with the positive photoresist AZ6632 at a speed of 2000 rpm for 30 s. The soft bake is conducted at 120 C for 4.5 min. Before developing in an 4:1 diluted 351-solution, the resist is UV-exposed with a dose of 100 mj cm 2. The development is finished with a hard bake of 4.5 min at 125 C. This is done in order to improve the etch resistivity of the resist during the DRIE processing. The actual patterns are parallel grooves with a length of 5000 µm, a width of 10 µm and a pitch of 18 µm. Grooves with equal length but smaller widths and pitches are also patterned and etched alongside but are not further discussed in this paper. In order to save costs and reduce the etch mask variability of different experiments, only small pieces ( 4 cm 2 ) of the patterned wafer are processed. This is done through manual diamond cleaving. However, a carrier substrate is still needed to properly clamp and cool the pieces in the DRIE tool. The carrier also functions as a protection for the bottom electrode. In this work SiOx was used as carrier and reused across the different experiments. Fomblin -oil or thermal grease was used to temporarily bond the two. A three step process provided by the DRIE tool manufacturer was used as a starting point. The effect of parameter changes on the output will be discussed next. After DRIE processing, samples were again cleaved with a diamond to inspect the cross section with a FEI XL30 secondary ion emission microscope. Photoresist thicknesses before and after processing were measured with a Dektak XL stylus profilometer. 3. Results and discussion The initial parameters of the three step process are given in table 1. Due to the addition of the extra breakthrough step as compared to the more conventional two step DRIE process, it is now possible to alter process parameters after fluorcarbon removal at the bottom of the trench. Main parameters altered here are: SF 6 -flow, pressure and bias power. After 100 cycles, the process of table 1 resulted in a 68 µm deep trench with a Si to mask etch selectivity of 52:1. The profile is severely negative tapered with a sidewall angle of 91.9. This limits the usability of the process if one wants to etch trenches with a small pitch, especially if the trenches needs to be very deep. Therefore the effect of several parameters is studied in order to straighten the trench profile without compromising on the etch selectivity in the existing three step process.

Table 1. Three step process parameters and their initial values. Step Time SF 6 C 4 F 8 Pressure Plasma power Bias power (s) (sccm) (sccm) (mbar) (W) (W) Deposition 2 10 200 0.033 2500 0 Breakthrough 2 200 10 0.040 2000 35 Etch 2 400 10 0.093 2500 0 3.1. Bias power The first parameter under study is the bias power. According to [3], sidewall angles become more positive tapered by lowering the bias power in the etch step of a two step process. As can be seen in figure 2, similar results are obtained in this paper with the three step process by lowering the bias power during the breakthrough. An interesting side effect is the increase of the etch selectivity with respect to the resist mask. Which confirms that resist mask erosion is mainly caused by ionic impact. Switching off the bias power after fluorcarbon removal, as is done in a three step process, is thus a viable route to enhance the Si to resist etch selectivity. Figure 2. Effect of bias power during the breakthrough on the Si to resist etch selectivity and sidewall angle. One drawback however of decreasing the breakthrough power is the reduced overall etch rate, which dropped from 6.8 µm min 1 at 35 W to 5.9 µm min 1 at 9 W. This is due to the reduced contribution of the breakthrough step to the actual silicon etching. Similar results should thus be found by keeping the bias power constant and reducing the breakthrough step time. Unfortunately a 2 s step time is already close to the minimal switching time of the machine, which is limited by the response time of the mass flow controllers. Another limiting factor in this experiment was the accuracy of the automatic matching unit. If bias power was lowered to 4 W, matching became impossible, resulting in total power reflection and almost no silicon etching. 3.2. Breakthrough pressure With bias power adjusted to 9 W the effect of breakthrough pressure is investigated. Lowering the pressure from 40 µbar to 30 µbar further improved the sidewall angle to 90.4. This is most probably due to the longer mean free path of SF 6 -ions which in term leads to a lower ion dispersion in the dark region between the substrate and the plasma [2]. Thus causing less etching of the sidewall polymer. However both selectivity and overall etch rate dropped to 84.6:1 and 5.5 µm s 1 respectively. Due to the limited pump capacity and the chosen flow rates, the minimal attainable pressure is 25 µbar. Yet this pressure is never experimented with since the

pressure in the subsequent etching step, which is 3.7 times higher, was already difficult to reach in the 2 s time slot. 3.3. Deposition time A natural parameter to tune in order to change the sidewall angle, is the deposition step time. The longer this step lasts, the more polymer is deposited and the harder it becomes to remove it from the sidewalls in the subsequent step. As a consequence more positive tapered slopes are obtained [4]. Doubling the deposition time to 4 s resulted in a perfect sidwall slope of 90 and a 1.4 times better conservation of the mask material. But due to overpassivation, the etch rate severely dropped to 2.25 µm s 1. As stated before, the sidewall angle of deep trenches is the main focus of this research. Therefore further optimization of the deposition time is omitted at this point. But it is important to mention that reducing the deposition time to overcome overpassivation will lead to higher overall etch rates, without affecting both sidewall angle and mask removal rate. Testing the process developed so far to check if the observations still hold with more cycles is now more interesting in achieving deep straight walled trenches. 3.4. Number of cycles By doubling the number of cycles to 200 and keeping all the other parameters the same, trenches were, as expected, twice as deep. However the sidewall angle slightly increased to 90.4. This is due to an effect called imaging force. As explained in [2] and [5] imaging force is the deflection of ions entering a trench towards the sidewalls due to the negative potential of these conducting silicon sidewalls with respect to the plasma glow. As trenches become deeper, more deflection will occur which in term leads to the observed profile. As the number of cycles is increased (a) (b) Figure 3. Etching result after (a)200 cycles and (b)400 cycles. even further to 400 cycles the observed profile changes completely. As can be seen in figure 3: sidewalls become positive tapered with an angle of 89.1 and grassing is observed at the bottom of the trench. The formation of the grass and the positive sloped sidewalls are due to an imbalance in polymer removal and deposition [6]. Too much polymer is deposited with respect to breakthrough and etch step. The reason why it only appears in deeper trenches is because the polymer removal at the bottom becomes less effective at higher aspect ratios. This is a consequence of imaging forces and dispersion of ions due to collisions in the plasma glow [2], basically the same mechanisms that are thought to cause the aspect ratio dependent etching (ARDE) [2].

Figure 4. Result after 400 cycles with 9 W bias power in the first half and 14 W in the second half. Trench widths from left to right are 6, 8 and 10 µm. To prevent grassing from occurring, more directional ions during the breakthrough are thus needed. Since pressure is already minimized, bias power should therefore increase. However an increase in bias power also leads to faster mask removal and worse selectivity as indicated in figure 2. Because the higher bias power is only needed at high aspect ratios one can first etch trenches with a low bias power and later on switch to a higher bias power. The result of this approach, where the first 200 cycles are etched at 9 W and the subsequent 200 cycles at 14 W, is shown in figure 4. These trenches have sidewall angles of 89.7 and are 130 µm deep. The sidewall damage seen at 80 % of the trench depth is most probably due to mask erosion as explained in [7]. Conclusion By analysing the effect of bias power, breakthrough pressure, deposition time and number of cycles on etch characteristics in a three step DRIE process. A recipe is developed to etch 130 µm deep trenches in silicon with a width of 10 µm. The sidewalls are almost vertical with an angle of 89.7, which is a strict requirement for high density deep trench etching. Excellent silicon to photoresist etch selectivity of 50:1 is achieved due to limited usage of high energy ions during breakthrough. This obviates the use of metal or oxide masks for through wafer etching applications such as: comb drives, springs and through wafer vias. Which is a big advantage when combined with CMOS processing. Currently the proposed 400 cycle process with an etch rate of 2.45 µm min 1 is used to etch mechanical structures with thicknesses starting from 100 µm. Acknowledgement This research was made possible by the Hercules Foundation for heavy equipment (AKUL 034 and ZW1115), and received funding from the European Research Council under the European Union s Seventh Framework Programme (FP7/2007-2013) / ERC grant agreement n o 340931. References [1] Robert Bosch GmbH 1994 Pat. 4,855,017 and 4,784,720 (USA) and 4241045C1 Germany [2] Jansen H V, De Boer M J, Unnikrishnan S, Louwerse M C and Elwenspoek M C 2009 J. Micormech. Microeng. 19 033001-41 [3] Ayón A A, Braff R, Lin C C, Sawin H H and Schmidt M A 1999 J. Electrochem. Soc. 146 339-49 [4] Abdolvand R and Ayazi F 2008 Sens. Actuators A 144 109-16 [5] Elwenspoek M and Jansen H V 2004 Silicon Micromachining (Cambridge: Cambridge University Press) [6] Ayón A A, Chen S, Lohner A, Spearing S M, Sawin H H and Schmidt M A 1998 Proc. Material Research Society (Cambridge) vol 546 Heuer A H and Jacobs S J (Cambridge: Material Research Society) p51 [7] Meng L and Yan J 2015 J. Micormech. Microeng. 25 035024-32