33 Lecture 3 asic aplifier architectures
asic plifier Structures MOS and ipolar Transistors oth have 3 priary terinals MOS transistor has a fourth terinal that is generally considered a parasitic D terinal G S D G S Transistors as 3-terinal Devices D G S Sall Signal Transistor Models as 3-terinal Devices
asic plifier Structures Observation: OUT OUT IN M IN These circuits considered previously have a terinal (eitter or source) coon to the input and output in the sall-signal equivalent circuit For JT, is coon, input on, output on For MOSFT, S is coon, input on G, output on D Tered oon itter Tered oon Source
asic plifier Structures D G plifiers using these devices generally have one terinal coon and use reaining terinals as input and output Since devices are unilateral, designation of input and output terinals is uniquely deterined Three different ways to designate the coon terinal S Sall Signal Transistor Models as 3-terinal Devices Source or itter Gate or ase Drain or ollector tered oon Source or oon itter tered oon Gate or oon ase tered oon Drain or oon ollector
asic plifier Structures D G S Sall Signal Transistor Models as 3-terinal Devices MOS oon Input Output JT oon Input Output oon Source or oon itter oon Gate or oon ase oon Drain or oon ollector S G D G S D D G S
asic plifier Structures D G oon Source or oon itter oon Gate or oon ase oon Drain or oon ollector S Sall Signal Transistor Models as 3-terinal Devices Objectives in Study of asic plifier Structures. Obtain key properties of each basic aplifier 2. Develop ethod of designing aplifiers with specific characteristics using basic aplifier structures oon Gate oon Source INPUT OUTPUT oon Drain oon Drain oon Source Overall plifier Struture
haracterization of asic plifier Structures D G S Sall Signal Transistor Models as 3-terinal Devices Observe that the sall-signal equivalent of any 3-terinal network is a two-port Thus to characterize any of the 3 basic aplifier structures, it suffices to deterine the two-port equivalent network Since sall signal odel when expressed in ters of sall-signal paraeters of JT and MOSFT differ only in the presence/absence of g π ter, can analyze the JT structures and then obtain characteristics of corresponding MOS structure by setting g π = D G D G S S GS g GS g O g π g g O
The three basic aplifier types for both MOS and bipolar processes oon itter oon Source oon ase oon Gate oon ollector oon Drain Will focus on the perforance of the bipolar structures and then obtain perforance of the MOS structures by observation
The three basic aplifier types for both MOS and bipolar processes in L OUT oon itter in g π be g be OUT L v g v v OUT L be IN v v v be OUT IN g L in oon ase OUT L in be g π g be OUT L v g v v OUT L be IN v v v be OUT IN g L in OUT L in be g π g be OUT v g g v OUT bel IN be bel v v g g v oon ollector L g v g OUT L v g g IN L Significantly different gain characteristics for the three basic aplifiers There are other significant differences too ( IN, OUT, ) as well
The three basic aplifier types for both MOS and bipolar processes in L oon itter oon Source oon itter OUT OUT in L oon ase oon Gate oon ase OUT in L oon ollector oon Drain oon ollector More general odels are needed to accoodate biasing, understand perforance capabilities, and include effects of loading of the basic structures Two-port odels are useful for characterizing the basic aplifier structures How can the two-port paraeters be obtained for these or any other linear two-port networks?
Two-Port Models of asic plifiers widely used for nalysis and Design of plifier ircuits Methods of Obtaining plifier Two-Port Network i in v2 o v 2. TST : i TST Method (considered in last lecture) 2. Write : 2 equations in standard for = i + IN 2 = i + 2 2 O 3. Thevenin-Norton Transforations 4. d Hoc pproaches ny of these ethods can be used to obtain the two-port odel
test : itest Method for Obtaining Two-Port plifier Paraeters SUMMY fro PIOUS LTU test i in v2 o v 2 out-test out-test test test i TST i i in v2 in v2 o o v v 2 2 i TST test in test test test i test i If Unilateral = out-test i in v2 o v 2 test out-test test
Will now develop two-port odel for each of the three basic aplifiers and look at one widely used application of each oon itter oon Source oon ase oon Gate oon ollector oon Drain
onsider oon itter/oon Source Two-port Models oon itter oon Source oon ase oon Gate oon ollector oon Drain Will focus on ipolar ircuit since MOS counterpart is a special case obtained by setting g π =
asic /S plifier Structures OUT OUT M IN IN oon itter plifier oon Source plifier OUT OUT IN M IN oon itter plifier oon Source plifier an include or exclude and in two-port odels (of course they are different circuits) The and S aplifiers are theselves two-ports!
Two-port odel for oon itter onfiguration It can be readily shown that the coon-eitter configuration is unilateral oon itter Thus it is characterized by the paraeters { in, and } i in o v 2 Two-Port /S plifier
Two-port odel for oon itter onfiguration oon itter be g π g be g O? i in v o 2 { i, and }
Two-Port Models of asic plifiers widely used for nalysis and Design of plifier ircuits Methods of Obtaining plifier Two-Port Network i in v2 o v 2. TST : i TST Method 2. Write : 2 equations in standard for = i + IN 2 = i + 2 2 O 3. Thevenin-Norton Transforations 4. d Hoc pproaches
Two-port odel for oon itter onfiguration oon itter be g π g be g O i in v o 2 y Thevenin : Norton Transforations in g g g g
Two-Port Models of asic plifiers widely used for nalysis and Design of plifier ircuits Methods of Obtaining plifier Two-Port Network i in v2 o v 2. TST : i TST ethod 2. Write : 2 equations in standard for = i + IN 2 = i + 2 2 O 3. Thevenin-Norton Transforations 4. d Hoc pproaches
Two-port odel for oon itter onfiguration lternately, by TST : i TST Method To obtain in i test oon itter test be g π g O g be i in v o 2 in in i test test g { in, and }
Two-port odel for oon itter onfiguration lternately, by TST : i TST Method To obtain test be g π g O g be out-test oon itter out-test test i in v o 2 outtest test g g g g { in, and }
Two-port odel for oon itter onfiguration lternately, by TST To obtain g : i TST Method i test be g π g be g O te oon itter i test i test test test i g in v o 2 g { in, and }
Two-port odel for oon itter onfiguration i in v o 2 oon itter In ters of sall signal odel paraeters: in i g I t Q g g F g In ters of operating point and odel paraeters: Input ipedance is id-range oltage Gain is Large and Inverting Output ipedance is large Widely used to build voltage aplifiers t F IQ
oon itter onfiguration onsider the following application DD (this will also generate a two-port odel for this application) out in oon itter inc Two-port including in o in v out Two-Port Model out g g g in out= o// in out in = r = i n g g g g g g π g g = // out o g g g g g
oon itter onfiguration onsider the following application (this will also generate a two-port odel for this application) This circuit can also be analyzed directly without using 2-port odel for configuration oon itter inc out in be g π g be g O g g g out in = out g g g g g g g out= g g g = r in π in
oon itter onfiguration onsider the following application (this is also a two-port odel for this application) Sall signal paraeter doain oon itter inc Operating point and odel paraeter doain g g g out = r in g g π g g out g g g g I = I in Q t Q t Input ipedance is id-range oltage Gain is large and Inverting Output ipedance is id-range Widely used as a voltage aplifier
oon Source/ oon itter onfigurations in in g I t Q oon itter oon Source g g g g in g In ters of operating point and odel paraeters: F F F in IDQ IDQ t IQ 2 2 F Q Q g Input ipedance is id-range (infinite for MOS) oltage Gain is Large and Inverting Output ipedance is large Widely used to build voltage aplifiers
oon Source/oon itter onfiguration D g g g oon itter inc out g g out in = r in g g I g g Q π t = I Q t g g g g D g g D Input ipedance is id-range (infinite for MOS) oltage Gain is Large and Inverting Output ipedance is id-range Widely used as a voltage aplifier out oon Source inc D in In ters of operating point and odel paraeters: in g g D g D g g D 2I DQ D out Q g g D D D
onsider oon ollector/oon Drain Two-port Models oon itter oon Source oon ase oon Gate oon ollector oon Drain Will focus on ipolar ircuit since MOS counterpart is a special case obtained by setting g π =
Two-port odel for oon ollector onfiguration It can be readily shown that the coon-collector and the coon base configurations are not unilateral Thus a 4-paraeter two-port odel is needed to characterize these structures oon ollector i g π g g O g r 2 2 Or, equivalently oon ase i ox ix v 2 vr2
Two-port odel for oon ollector onfiguration be g π g be g O oon ollector? i ox ix vr2 v 2 { ix,, r and X }
Two-Port Models of asic plifiers widely used for nalysis and Design of plifier ircuits Methods of Obtaining plifier Two-Port Network i in v2 o v 2. TST : i TST Method 2. Write : 2 equations in standard for = i + IN 2 = i + 2 2 O 3. Thevenin-Norton Transforations 4. d Hoc pproaches
Two-port odel for oon ollector onfiguration i oon ollector be g π g be g O 2 pplying KL at the input and output node, obtain i 2 g i g g g g g 2 o 2 These can be rewritten as i r π 2 g g 2 2 g g go g g go Standard Two-Port plifier epresentation i ix v2 i v ix 2 i 2 2 ox ox 2 : 2 equations in standard for It thus follows that ix =r π Or= X g g g o g g g g g o
Two-port odel for oon ollector onfiguration i be g π g be g O 2 oon ollector i Two-port oon ollector Model ox ix v 2 vr2 ix =r π Or= X g g go g g g g go g
oon ollector onfiguration onsider the following application DD Deterine in,, and (this is not asking for a two-port odel for the application in and defined for no additional load on output, o defined for short-circuit input) in out IN oon ollector OUT SS in i ox ix vr2 v 2 out if g gox g g g g go g g g = = gox g g g go g g go g g g go g g g g = i g +g X in ix vr v in X = = g +g +g +g g +g +g π g g g o r g g go g = r r +β g g go g g g go g g g in π π g
oon ollector onfiguration onsider the following application (this is not asking for a two-port odel for the application, in and defined for no additional load on output, o defined for short-circuit input -) in DD out IN oon ollector OUT lternately, this circuit can also be analyzed directly SS i in g π g g O OUT in g g g g g out in in out g g g g g g out in g g g g g g g g g I Q I + Q t i i in g in in out g g g g gin g g g g g g g g out in g g g g r + g g o o in= rπ π β go g
oon ollector onfiguration onsider the following application (this is not asking for a two-port odel for the application, in and defined for no additional load on output, o defined for short-circuit input -) in DD out IN oon ollector OUT SS i in g π g g O OUT g π g g O i out in OUT To obtain, set in g g g g i out out out out = g g o g g g g g o
oon ollector onfiguration onsider the following application (this is not asking for a two-port odel for the application, in and defined for no additional load on output, o defined for short-circuit input -) in DD out IN oon ollector OUT SS out = g g g IQ g g g g g g I + g g g g r + g g o g g g g g o Q t g g o o in= rπ π β go g Question: Why are these not the two-port paraeters of this circuit? in defined for open-circuit on output instead of shortcircuit (see previous slide : -2 slides) r i ox ix v 2 vr2
oon ollector onfiguration DD For this application OUT (this is not a two-port odel for this application) IN in out oon ollector Sall signal paraeter doain g g g g g g if g g IQ I + Q t SS Operating point and odel paraeter doain I Q t g g o r +β in π in I Q t β +g g g Q t Output ipedance is low is positive and near Input ipedance is very large Widely used as a buffer Not copletely unilateral but output-input transconductance (or r ) is sall and effects are generally negligible though agnitude sae as I I t Q
oon ollector/oon Drain onfigurations For these /D applications (not two-port odels for these applications) DD OUT in out g g g g g g g g o r +β in π +g IQ I + Q t g I in Q t I g IN Q t β if g g Output ipedance is low is positive and near Input ipedance is very large oon ollector I Q t I t Q OUT in G D S SS S in out IN g g g g S +g In ters of operating point and odel paraeters: S S g S oon Drain if g g g 2IDQ S if 2I DQ Q 2IDQ S+Q S 2I DQ S Q +2I 2I in Widely used as a buffer Not copletely unilateral but output-input transconductance is sall Q S Q Q DQ S DQ S D
nd of Lecture 3