JOURNAL OF APPLIED PHYSICS VOLUME 86, NUMBER 12 15 DECEMBER 1999 Asymmetrical heating behavior of doped Si channels in bulk silicon and in silicon-on-insulator under high current stress C. N. Liao, a) C. Chen, J. S. Huang, b) and K. N. Tu c) Department of Materials Science and Engineering, UCLA, Los Angeles, California 90095 Received 8 July 1999; accepted for publication 13 September 1999 With continuing scaling down in microelectronic devices, the current density and the power consumption in the devices must increase. Hence, device reliability under high current density is an issue for ultralarge-scale integration technology. This study investigates the heating behavior of the heavily doped Si channels under high current stress. Thermal and electrical characterization of the channels in bulk Si and in silicon-on-insulator were conducted. An abnormal asymmetrical heating along the channels in bulk Si has been observed. We propose a junction leakage mechanism to explain the phenomenon observed. Other asymmetrical thermal effects, such as electron hole recombination and Peltier effect, have also been discussed. 1999 American Institute of Physics. S0021-8979 99 04324-8 I. INTRODUCTION Current density in microelectronic devices is increasing with decreasing integrated circuit feature size. The stability and reliability of electrical contacts under high current stress become important issues. There are many research contributions about the electrical, thermal, and mechanical phenomena associated with electrical contacts stressing. Öberg et al. reported an asymmetrical contact resistance increase of the aluminum contacts to nickel-plated copper, which were subjected to a dc current of 1000 A for 10 5 h. 1 The contact resistance at the cathode is found to be higher than that at the anode. The authors interpreted this phenomenon in terms of electromigration and Ni/Al intermetallic compound formation. Huang et al. reported a polarity effect on Ni and Ni 2 Si contact failures under high current density stress. 2 The different contact failure modes were attributed to wearout, electromigration enhanced silicide formation, and electron hole recombination mechanisms. Besides these proposed contact failure mechanisms, the heating and thermoelectric effects of the doped Si channels under high current stress have not been addressed in detail. The Si channel which connects the contacts will be heated up due to the Joule effect. It is known that a 10 20 C increase in chip temperature can sometimes double the failure rate of the components. 3 In this study, we observed an asymmetrical thermal behavior of the doped Si channels under high current density stress. Thermal and electrical characterization of the doped Si channels was conducted. We suggest that a junction leakage mechanism is responsible for the asymmetrical heating behavior. For comparison, the doped Si channels in bulk Si and in silicon-oninsulator SOI wafers were studied. The latter has no junction leakage. a Now at Intel, Portland, OR. b Now at Lucent Technologies, Orlando, FL. c Electronic mail: KNTU@UCLA.EDU II. EXPERIMENT A. Sample preparation The testing structures for thermal and electrical characterization of the implanted Si channels on bulk Si and SOI wafers were prepared. The plain view and the cross-sectional view of the testing structures are shown in Fig. 1. The implanted Si channels are 175 m long and 10 m wide with a contact area of 10 m 10 m. To prepare the bulk Si samples, Si wafers of 100 orientation were first grown a thin oxide layer 3000 Å thick by wet oxidation. The channels were defined on the oxide layer by photolithography and buffered HF etching. Prior to ion implantation, a screen oxide layer 200 Å thick was grown on the wafers for capping and filtering the implanted ions. The samples were implanted with BF 2 and As, respectively, to form p /n and n /p junctions. The implanted ions had a dose of 5 10 15 ions/cm 2 and an accelerating voltage of 40 kev. Postimplantation annealing was conducted at 900 C for 30 min under N 2 ambient for dopant activation. After stripping the screen oxide, a low temperature oxide LTO 3000 Å thick was deposited on the wafers. The second mask was used to open contact holes on the LTO oxide layer using photolithography and wet etching. A nickel film 2600 Å thick was deposited on the samples to make contacts with the diffused Si channels using e-beam evaporation. The final metal bond pads were patterned by the third photomask through typical photolithography and etching processes. For comparison, the Si channels in SOI structures were prepared using conventional complementary metal oxide semiconductor process technology. The SOI wafers used are separation by implantation of oxygen wafers, which have a buried oxide layer 4000 Å thick underneath the top Si thin film. The top Si film is around 2000 Å thick. The SOI wafers were grown a screen oxide 200 Å thick prior to ion implantation. Two different ionic species; BF 2 and As, were implanted on the SOI wafers. The implant species has a dose of 5 10 15 ions/cm 2 at an acceleration voltage of 40 kev. Postimplantation annealing was conducted at 900 C for 30 0021-8979/99/86(12)/6895/7/$15.00 6895 1999 American Institute of Physics
6896 J. Appl. Phys., Vol. 86, No. 12, 15 December 1999 Liao et al. FIG. 1. The testing structures for thermal and electrical characterization of the implanted Si channels on bulk Si and SOI wafers are prepared. min under nitrogen ambient. The silicon channel was patterned using photolithography and fluorine reactive ion etching processes. The Si channels were then capped by a plasma enhanced chemical vapor deposition SiO 2 layer of 2000 Å thickness. Contact holes were drilled through the oxide layer using buffer oxide etchant. A Ni 1500 Å metallic film was deposited on the samples by e-beam evaporation. Finally the metal bond pads were defined with wet etching processes. B. Experimental procedures An electrical probe station equipped with an optical microscope was used for electrical measurement. Samples were put on a hot stage that can be heated from room temperature to 300 C. The temperature of the hot stage was monitored using a Keithly 740 thermometer. Current sources Keithley 220 and multimeters Keithley 195 were used to supply electrical current and to measure the voltage drop across the Si channels. All the devices were controlled through a general purpose interface bus interface and a PC computer. The temperature of the test samples were calibrated using Omegaprobe test kits which has 20 crayons measuring temperatures ranging from 52 to 316 C. Each crayon melts at a specific temperature with a temperature resolution of 1.0 C. By applying the crayon on the sample surface and heating up the hot stage, the crayon will turn into a liquid smear when the specific temperature is reached. We found that the temperature at the Si sample surface was nearly the same as that measured at the hot stage within 1 C. To observe the thermal response of the doped Si channel under high current stress, an electrical current was applied through the Si channel that was pasted with Omegaprobe crayon. The electrical voltage current (V I) characteristic can also be measured. FIG. 2. Crayon 260 C melting test for the p -Si channels in bulk Si at a stress current of: a 35 ma, b 40 ma, c 50 ma, d 60 ma, e 70 ma, and f 80 ma. III. RESULTS AND DISCUSSION Figure 2 shows the crayon (T m 260 C) melting test results for the BF 2 -doped Si channels in bulk Si when an electric current ranging from 35 to 80 ma was applied. The crayon pasted on the channel surface melts symmetrically around the channel if the current is less than 40 ma as shown in Figs. 2 a and 2 b. Under this stress condition, the whole channel is uniformly heated up due to Joule effect. Once the current applied is over 40 ma, the crayon at the cathode side melts in a larger area than that at the anode side as shown in Figs. 2 c and 2 d. It indicates that the cathode end of the channel is hotter than the anode end. The crayon melts symmetrically again as the current reaches 70 ma and above as shown in Figs. 2 e and 2 f. However, in the last two cases a thin Ni silicide line is found inside the Si channel. The silicide line formation assisted by high current stress was first observed by Huang et al. 4 Figure 3 shows the testing setup and the V I characteristic curves of the BF 2 -doped Si channel in bulk Si. When the electric current applied is less than 38 ma, the total voltage of the whole channel increases with current and the voltages of two half channels are the same. When the current applied is above 38 ma, the total voltage V T decreases with current, but the voltage of the half channel at the cathode side V C is higher than that at the anode side V A. The V I characteristic curves show an irreversible behavior before and after the voltage reaches the peak value for the first stress cycle, but they become reversible for the second stress cycle. Assuming the two half channels have the same electrical resistance, the V A and the V C should be the same as the case when the current is less than 38 ma. However, the V A drops faster than the V C with increasing current when the
J. Appl. Phys., Vol. 86, No. 12, 15 December 1999 Liao et al. 6897 FIG. 4. The crayon (T m 135 C) melting result and the electrical characteristic of the As -doped Si channel in bulk Si. FIG. 3. a A schematic of the experimental setup and the V I characteristic curves of the BF 2 -doped Si channel in bulk Si for b the first stress cycle and c the second stress cycle. current applied is over 38 ma. This electrical behavior is consistent with the crayon melting test results which showed a transition from symmetrical heating to asymmetrical heating occurring between 40 and 50 ma as shown in Fig. 2. Figure 4 shows that the crayon (T m 135 C) melting result and the electrical characteristic of the As -doped Si channel in bulk Si. The crayon at the anode side appears to melt in a larger area than that at the cathode side under a stress current of 33 ma as shown in Fig. 4 a. An abrupt transition occurs at 40 V for the As -doped Si channels. Besides the sharp voltage drop shown in Fig. 4 b, V A and V C are about the same. As compared to the BF 2 -doped Si channels which are hotter at the cathode side, the As -doped Si channels are hotter at the anode side and have a lower transition voltage of 40 V. A. Junction leakage mechanism The voltage measured is equal to the product of the current applied and the Si channel resistance according to Ohm s law. The resistance of the two half channels are presumably the same by ignoring the thermally induced resistance change. One possible explanation for the unequal voltages of the two half channels is due to an uneven current distribution in the two half channels. This means that the current is not completely confined in the doped p -Si channel. In other words, there is a leakage. To prove this point, a test for substrate current measurement was conducted as shown in Fig. 5. The result reveals a very good correlation between the substrate current leakage and the voltage reduction when the current applied is over 38 ma. However, the substrate leakage current, which is in the range of A, seems too small to be responsible for the big voltage reduction of the p -Si channel. By examining the test structure, the junction of p -Si/n substrate at the anode is under a forward bias and the current can cross the junction very easily. But, the junction of p -Si/n substrate at the cathode is under a reverse bias. It requires a certain level of junction breakdown voltage in order to overcome the barrier. This explains the sharp voltage peak existing in the V I curve for the first stress cycle shown in Fig. 3 b. Once the current conduction path has been established, the breakdown voltage is reduced as shown in Fig. 3 c. The substrate leakage current measured in Fig. 5 is small because the contact is under a reverse bias and the electric current experiences an extra I R sub voltage drop in order to reach the contact of the Amp meter. To reduce the junction resistance at the cathode, an ohmic contact to the backside of the substrate is prepared by sanding the substrate surface and gluing the substrate onto a copper film coated substrate using silver paste. Figure 6
6898 J. Appl. Phys., Vol. 86, No. 12, 15 December 1999 Liao et al. FIG. 5. a A schematic of the experimental setup and b the leakage current measurement results for the p -Si channel in bulk Si. FIG. 6. a A schematic of the experimental setup and b the substrate current measurement results for the p -Si channel in bulk Si with an ohmic contact at the backside of the substrate. shows the experimental setup and the substrate leakage current with respect to the total current applied. Most of the substrate leakage current passes through the substrate backside instead of coming back to the p -Si channel due to low substrate resistance and junction barrier. When the total current applied is 20 ma, the substrate leakage current measured is around one half of the total current. The current passing through the substrate can be estimated using a simple parallel resistance model as shown in Fig. 7. The total resistance consists of the substrate resistance R S and the channel resistance R ch in a parallel configuration. Before the junction breakdown, R S is much larger than R ch and the total resistance measured is equal to R ch. The channel resistance increases nonlinearly with applied voltage due to high field effect. 5 The relationship between the channel resistance and the applied voltage was determined by polynomial curve fitting. We can calculate the channel resistance R ch in the region of junction leakage by knowing the applied voltage V meas. The channel current I ch obtained is V meas /R ch and the average leakage current entering the substrate I sub is then given by I sub I V meas /R ch. 1 When the total current is 60 ma, there would be a current of 25 ma leaking into the substrate. How is the leakage current related to the asymmetrical heating behavior of the Si channel? Since the n-sub is electrically floating, the current leaking into the substrate must go back to the cathode. When the voltage across the junction is less than the breakdown voltage, the total current is confined in the p -Si channel. Once the voltage across the junction is high enough to overcome the reverse bias, the substrate current will flow back to the p -Si channel. This causes the cathode half channel to have a higher current density than the anode half channel. The Joule heat generated at the cathode half channel is, therefore, larger than that at the anode half channel. This is the reason why an asymmetrical thermal behavior of the p -Si channel occurs when the current applied is more than 38 ma. To prevent the junction leakage, the doped Si channels in SOI structures were examined. The buried oxide layer in SOI wafers provides a very good electrical insulation. Figure 8 shows the V I characteristic curves of the BF 2 -doped Si and the As -doped Si channel in SOI wafers. Both the voltages of the p -Si channel and the n -Si channel increase with the applied current up to 100 V without the drops like those in bulk Si. Figure 9 shows the crayon (T m 260 C) melting test for the SOI testing structures. The crayon melts symmetrically along the channel when applying a current of 22 ma through the channels. These results provide further evidence of the junction leakage mechanism, which is responsible for the asymmetrical heating along the powered Si channels in bulk Si. The other interesting behavior of the p -Si channel under high current stress is silicide line formation. Figure 10 shows a narrow NiSi 2 silicide line formed at a stress current
J. Appl. Phys., Vol. 86, No. 12, 15 December 1999 Liao et al. 6899 FIG. 7. Calculation of substrate leakage current for the BF 2 -doped Si channel. of 90 ma. We believe that the silicide line formation is related to an avalanche-like breakdown behavior. A detailed mechanism is still under investigation. But, the metallic silicide line formation may redistribute the Joule heating and reduce the asymmetry of the heating along the p -Si channel. This may possibly explain the symmetrical crayon melting along the channel when the stress current is above 60 ma where the silicide line is formed. The different junction breakdown behaviors between the p -Si channel and the n -Si channel may be associated with the dopant concentration profiles. Figure 11 shows the dopant concentration profiles of the doped Si channels obtained from secondary ion mass spectrometry SIMS measurements. 6 The gradual breakdown behavior of the BF 2 -doped Si channel may be mainly due to a long tail of the concentration profile. On the other hand, a shallow and abrupt junction of the As -doped Si channel is responsible for the low breakdown voltage and sharp transition. There is no silicide line formation in the n -Si channel because most of the current enters the p substrate and it reduces the voltage built up along the channel. The junction cannot reach the avalanche breakdown voltage using a current source and no silicide line is formed. To confirm this effect, more experiments are needed. B. Electron hole recombination effect and Peltier effect Besides the junction leakage mechanism, the abnormal heating behavior observed along p -Si channels may also be contributed to other asymmetrical effects, such as electron FIG. 8. a A schematic of the experimental setup and the V I characteristic curves of b the BF 2 -doped Si channel and c the As -doped Si channel in the SOI wafer. hole recombination in p -Si channels 6 and the Peltier effect. The heating rate generated by the electron hole recombination can be roughly estimated as follows: P e h Eg n / t Eg I/e 1.12 ev 60 ma/e 67 mw, where Eg, n, I and e stand for the Si band gap, the number of electron hole recombination pairs, the applied current, and the electron charge, respectively. When applying a current of 60 ma, the heating power generated by the electron hole recombination is about 67 mw. The Peltier effect induced heating power difference between the two junctions is given by 7 PPeltier 2 SIT 2 200 V/K 60mA 300 K 7.2 mw, where S and T are the Seebeck coefficient of the Si and absolute temperature in Kelvin, respectively. The factor 2 is because heat is generated at one junction and absorbed at the other. Assuming the Seebeck coefficient of the Si is 200 2 3
6900 J. Appl. Phys., Vol. 86, No. 12, 15 December 1999 Liao et al. FIG. 11. SIMS profiles of the BF 2 -doped and the As -doped Si with an implant dose of 5 10 15 ions/cm 2 at 40 kev, followed by 900 C annealing for 30 min. V/K, the heating power difference due to the Peltier effect is calculated to be 7.2 mw when applying a current of 60 ma at room temperature. We can also estimate the difference of the heating power between the two half channels. The total channel voltage V T is equal to 66.5 V at a stress current of 60 ma. The corresponding channel resistance is calculated to be 1.9 k according to Fig. 7. Therefore, the resistance of the two half channels is 950 k. From Fig. 7 the currents passing through the two half channels are given by FIG. 9. The crayon (T m 260 C) melting test for the SOI testing structures: a the p -Si channel and b the n -Si channel at a stress current of 22 ma. I A V A /R half 26 V/950 27.4 ma and I C V C /R half 40.5 V/950 42.6 ma. The difference of the heating power between the two half channels is then equal to P leakage I C V C I A V A 42.6 ma 40.5 V 27.4 ma 26 V 1013 mw. 4 From the above discussions we know that the junction leakage effect may play a more important role in the asymmetrical heating behavior of p -Si channels than the other two effects. IV. CONCLUSIONS FIG. 10. NiSi 2 silicide line formation in the BF 2 -doped Si channel at a stress current of 90 ma. This study was initiated by investigating an asymmetrical heating behavior of the doped Si channels under high current stress. It appears that the cathode is hotter for the p -Si channel and cooler for the n -Si channel in bulk Si when the current passing through the channel is above a critical point. The asymmetrical thermal behavior is found to be associated with p /n and n /p junction leakage. The current enters the substrate when the voltage built up at the junction is higher than the junction breakdown voltage. The junction leakage causes an unequal current distribution along the Si channel and results in an asymmetrical Joule heating at both ends of the channel. The junction leakage behavior
J. Appl. Phys., Vol. 86, No. 12, 15 December 1999 Liao et al. 6901 depends on the dopant profile in the Si channel, which is influenced by ion implantation and annealing conditions. A gradual dopant profile causes a soft breakdown behavior like the BF 2 -doped Si channel, and an abrupt junction results in a sharp junction leakage like the As -doped Si channel. When the voltage applied on the doped Si channel is above a certain level, an avalanche-like breakdown behavior occurs and a silicide line is formed inside the Si channel. 1 Å.Öberg, O. Saksvik, and K. E. Olsson, Proceedings of the 18th International Conference On Electrical Contacts, Chicago, IL, 1996, p. 189. 2 J. S. Huang, K. N. Tu, S. W. Bedell, W. A. Lanford, S. L. Cheng, J. B. Lai, and L. J. Chen, J. Appl. Phys. 82, 1 1997. 3 G. N. Morrison, J. M. Kallis, L. A. Strattan, I. R. Jones, and A. L. Lena, RADC Thermal Guide for Reliability Engineers, Report No. RADC- TR-82-172, Rome Air Development Center, Air ForceSystems Command, Griffth Air Force Base, NY 1982. 4 J. S. Huang, C. N. Liao, K. N. Tu, S. L. Cheng, and L. J. Chen, J. Appl. Phys. 84, 4788 1998. 5 S. M. Sze, Physics of Semiconductor Devices, 2nd ed. Wiley, New York, 1981. 6 J. S. Huang, Ph.D. dissertation, UCLA, 1997. 7 A. F. Ioffe, Semiconductor Thermoelements, and Thermoelectric Cooling Infosearch, London, 1957.