Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines

Similar documents
Generalized FSM model: Moore and Mealy

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1

Example: A vending machine

Models for representing sequential circuits

Synchronous Sequential Circuit Design. Digital Computer Design

EGR224 F 18 Assignment #4

Synchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1

Example: vending machine

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

EECS150 - Digital Design Lecture 23 - FSMs & Counters

CSE140: Digital Logic Design Registers and Counters

FYSE420 DIGITAL ELECTRONICS

State & Finite State Machines

Timing Constraints in Sequential Designs. 63 Sources: TSR, Katz, Boriello & Vahid

CSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid

Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process

Sequential Circuit Design

CPE100: Digital Logic Design I

State and Finite State Machines

Adders allow computers to add numbers 2-bit ripple-carry adder

ENGG 1203 Tutorial. Solution (b) Solution (a) Simplification using K-map. Combinational Logic (II) and Sequential Logic (I) 8 Feb Learning Objectives

Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..

State & Finite State Machines

ECE380 Digital Logic. Synchronous sequential circuits

Finite State Machine (FSM)

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

EEE2135 Digital Logic Design

ALU, Latches and Flip-Flops

Lecture 10: Synchronous Sequential Circuits Design

Chapter 6. Synchronous Sequential Circuits

CSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Instructor: Mohsen Imani. Slides from Tajana Simunic Rosing

14:332:231 DIGITAL LOGIC DESIGN

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec 09 Counters Outline.

Lecture 13: Sequential Circuits, FSM

FSM Optimization. Counter Logic Diagram Q1 Q2 Q3. Counter Implementation using RS FF 10/13/2015

Present Next state Output state w = 0 w = 1 z A A B 0 B A C 0 C A C 1

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

CprE 281: Digital Logic

Module 10: Sequential Circuit Design

CPE100: Digital Logic Design I

or 0101 Machine

COE 202: Digital Logic Design Sequential Circuits Part 3. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

Digital Circuits ECS 371

CPE100: Digital Logic Design I

Appendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring

Synchronous Sequential Circuit Design

ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

Symbolic State Minimization

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

Review: Designing with FSM. EECS Components and Design Techniques for Digital Systems. Lec09 Counters Outline.

COE 202: Digital Logic Design Sequential Circuits Part 3. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs

ECE 341. Lecture # 3

The Design Procedure. Output Equation Determination - Derive output equations from the state table

ASYNCHRONOUS SEQUENTIAL CIRCUITS

Finite State Machines CS 64: Computer Organization and Design Logic Lecture #15 Fall 2018

IE1204 Digital Design. L10: State Machines (Part 2) Masoumeh (Azin) Ebrahimi Elena Dubrova

EECS150 - Digital Design Lecture 16 Counters. Announcements

Different encodings generate different circuits

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

Midterm review session tomorrow 4:15 EEB125 Midterm 2 in class (45min long, starts at 10:35am) Today Abi bigger example: Hungry Robot Ant in Maze

ELCT201: DIGITAL LOGIC DESIGN

Lecture 14: State Tables, Diagrams, Latches, and Flip Flop

EECS150 - Digital Design Lecture 18 - Counters

EECS150 - Digital Design Lecture 18 - Counters

CpE358/CS381. Switching Theory and Logical Design. Class 16

Announcements Monday, November 13

EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters)

Sequential logic and design

ECE/Comp Sci 352 Digital Systems Fundamentals. Charles R. Kime Section 2 Fall Logic and Computer Design Fundamentals

14.1. Unit 14. State Machine Design

Clocked Sequential Circuits UNIT 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS. Analysis of Clocked Sequential Circuits. Signal Tracing and Timing Charts

Appendix A: Digital Logic. CPSC 352- Computer Organization

Numbers and Arithmetic

Numbers and Arithmetic

Announcements Monday, September 18

Lecture 8: Sequential Networks and Finite State Machines

ENEL Digital Circuit Design. Final Examination

5 State Minimisation. university of applied sciences hamburg. Digital Systems. Prof. Dr. J. Reichardt Prof. Dr. B. Schwarz

Combinational vs. Sequential. Summary of Combinational Logic. Combinational device/circuit: any circuit built using the basic gates Expressed as

Appendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc.

Mealy & Moore Machines

CMSC 313 Lecture 16 Announcement: no office hours today. Good-bye Assembly Language Programming Overview of second half on Digital Logic DigSim Demo

Sequential Synchronous Circuit Analysis

Lecture 13: Sequential Circuits, FSM

Announcements Monday, November 13

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output of

Finite State Machine. By : Ali Mustafa

Chapter 7. Synchronous Sequential Networks. Excitation for

EECS150 - Digital Design Lecture 15 SIFT2 + FSM. Recap and Outline

CprE 281: Digital Logic

Digital Design. Sequential Logic

Chapter 3. Chapter 3 :: Topics. Introduction. Sequential Circuits

Lecture 17: Designing Sequential Systems Using Flip Flops

Transcription:

Lecture 2 Logistics HW6 due Wednesday Lab 7 this week (Tuesday exception) Midterm 2 Friday (covers material up to simple FSM (today)) Review on Thursday Yoky office hour on Friday moved to Thursday 2-:2pm online Last lecture Counter design Finite state machine started vending machine example Today Continue on the vending machine example Moore/Mealy machines The WHY slide Finite State Machine (FSM) This is what we have been waiting for in this class. Using combinational and sequential logics, now you can design a lot of clever digital logic circuits for functional products. We will learn different steps you take to go from word problems to logic circuits. Moore/Mealy machines There are two different ways to express the FSMs with respect to the output. oth have different advantages so it is good to know them. 2

FSM design Counter-design procedure. State diagram 2. State-transition table 3. ext-state logic minimization 4. Implement the design FSM-design procedure. State diagram 2. state-transition table 3. State minimization 4. State encoding 5. ext-state logic minimization 6. Implement the design 3 Example: A vending machine 5 cents for a cup of coffee oesn t take pennies or quarters Reset oesn t provide any change Coin Sensor FSM-design procedure. State diagram 2. state-transition table 3. State minimization 4. State encoding 5. ext-state logic minimization 6. Implement the design Vending Machine FSM Clock Open Release Mechanism 4

A vending machine: (conceptual) state diagram Reset (from all states) S raw self-loops for for S to S3 S S2 Also draw self-loops for for S4 to S8 S3 S4 S5 S6 S7 S8 5 A vending machine: State transition table present inputs next output state state open S S S S2 X X S S S3 S4 X X S2 S2 S5 S6 X X S3 S3 S7 S8 X X S4 X X S4 S5 X X S5 S6 X X S6 S7 X X S7 S8 X X S8 6

A vending machine: State minimization Reset present inputs next output state state open 5 5 5 5 5 5 5 + 5 5 5 Reset symbolic state table 7 A vending machine: State encoding present state inputs next state output open 8

A vending machine: Logic minimization X X X X X X X X Open X X X = + + = + + + OPE = 9 A vending machine: Implementation

Generalized FSM model: Moore and Mealy Combinational logic computes next state and ext state is a function of current state and inputs Outputs are functions of Current state (Moore machine) Current state and inputs (Mealy machine) Inputs output logic ext-state logic ext State Outputs Current State Moore versus Mealy machines inputs combinational next state state feedback reg Moore machine Outputs are a function of current state t Outputs change synchronously with state changes inputs combinational next state state feedback reg Mealy machine Outputs depend on state and on inputs Input changes can cause immediate output changes (asynchronous) 2

Example -> : Moore or Mealy? Circuits recognize A= followed by A= What kinds of machines are they? out A clock Moore A clock Mealy out 3 Example / detector: a Moore machine Output is a function of state only Specify output in the state bubble / / reset A/ C/ E/ current next current reset input state state output A A A C C E C C E C E E 4

Example / detector: a Mealy machine Output is a function of state and inputs Specify on transition arcs reset/ / / A / / / C / current next current reset input state state output A A A C C C C C 5 Comparing Moore and Mealy machines Moore machines + Safer to use because change at clock edge May take additional logic to decode state into Mealy machines + Typically have fewer states + React faster to inputs don't wait for clock Asynchronous can be dangerous We often design synchronous Mealy machines esign a Mealy machine Then register the 6

Synchronous (registered) Mealy machine Registered state and registered o glitches on o race conditions between communicating machines inputs reg combinational next state reg state feedback 7 Example -> : Moore or Mealy? Recognize A, =, Mealy or Moore? A clock out Registered Mealy (actually Moore) A out clock Moore 8