SGM800 Low-Power, SOT µp Reset Circuit with Capacitor-Adjustable Reset Timeout Delay

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GENERAL DESCRIPTION The low-power micro-processor supervisor circuit monitors system voltages from 1.6V to 5V. This device performs a single function: it asserts a reset signal whenever the V CC supply voltage falls below its reset threshold. The reset output remains asserted for the reset timeout period after V CC rises above the reset threshold. The reset timeout is externally set by a capacitor to provide more flexibility. The has an active-low, open-drain reset output. It is available in Green SOT-23-5 package and is specified over an ambient temperature range of -40 to +85. FEATURES Monitor System Voltages from 1.6V to 5V Capacitor-Adjustable Reset Timeout Period Low Quiescent Current (3µA TYP) Open-Drain Output Option Guaranteed Valid to V CC = 1V Immune to Short V CC Transients Available in Green SOT-23-5 Package APPLICATIONS Portable Equipment Battery-Powered Computers/Controllers Automotive Medical Equipment Intelligent Instruments Embedded Controllers Critical µp Monitoring Set-Top Boxes Computers TYPICAL APPLICATION V CC V CC C SRT SRT GND MICROPROCESSOR SYSTEM GND REV. A. 1

PACKAGE/ORDERING INFORMATION MODEL PIN-PACKAGE SOT-23-5 THRESHOLD (TYP) ORDERING NUMBER PACKAGE MARKING PACKAGE OPTION 1.63V -1.63YN5G/TR S69XX Tape and Reel, 3000 2.32V -2.32YN5G/TR S6AXX Tape and Reel, 3000 2.63V -2.63YN5G/TR S6BXX Tape and Reel, 3000 2.93V -2.93YN5G/TR S6CXX Tape and Reel, 3000 NOTE: Order number and package marking are defined as the follow: ORDER NUMBER MARKING INFORMATION - X X X G / TR SYY X X Tape and Reel Green product Date code - Month ("A" = Jan. "B" = Feb. "L" = Dec.) Date code - Year ("A" = 2010, "B" = 2011 ) Chip I.D. Package Type N5 SOT-23-5 Operating Temperature Range Y -40 to +85 Reset Threshold 1.63 1.63V 2.32 2.32V 2.63 2.63V 2.93 2.93V For example: S69BA (2011, January) ABSOLUTE MAXIMUM RATINGS All Voltages Referenced to GND V CC...-0.3V to 6V (open-drain)...-0.3v to 6V Input Current (all pins)...20ma Output Current ( )...20mA Operating Temperature Range...-40 to +85 Storage Temperature Range...-65 to +150 Junction Temperature...150 Lead Temperature (Soldering, 10s)...260 ESD Susceptibility HBM... 3000V MM...300V CAUTION This integrated circuit can be damaged by ESD if you don t pay attention to ESD protection. SGMICRO recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SGMICRO reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. Please contact SGMICRO sales office to get the latest datasheet. NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2

PIN CONFIGURATION (TOP VIEW) SRT 1 5 GND 2 N.C. 3 4 V CC SOT-23-5 PIN DESCRIPTION PIN NAME FUNCTION 1 SRT Set Reset Timeout Input. Connect a capacitor between SRT and ground to set the timeout period. Determine the period as follows: t RP = 2.6 10 6 C SRT + 340 10-6 with t RP in seconds and C SRT in farads. 2 GND Ground. 3 N.C. Not Internally Connected. Can be connected to GND. 4 V CC Supply Voltage and Reset Threshold Monitor Input. 5 changes from high to low whenever V CC drops below the selected reset threshold voltage. remains low for the reset timeout period after V CC exceeds the reset threshold. 3

ELECTRICAL CHARACTERISTICS (V CC = 1V to 5.5V, T A = -40 to +85, typical values are at V CC = 5V and T A = +25, unless otherwise specified.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage Range V CC 1.0 5.5 V Supply Current V CC Reset Threshold Accuracy I CC V TH V CC 5.0V 3.9 7.0 V CC 3.3V 3.4 5.5 V CC 2.0V 3.0 4.8 T A = +25 V TH - 2.5% V TH + 2.5% T A = -40 to +85 V TH - 3.5% V TH + 3.5% Hysteresis V HYST 4 V TH mv V CC to Reset Delay t RD V CC falling at 1mV/µs 80 µs Reset Timeout Period t RP C SRT = 1500pF 3.00 4.25 5.75 C SRT = 0 0.34 V SRT Ramp Current I RAMP V SRT = 0 to 0.65V, V CC = 1.6V to 5V 210 na V SRT Ramp Threshold V TH-RAMP V CC = 1.6V to 5V (V RAMP rising) 0.6 V Output Voltage Low Output Leakage Current, Open-Drain V OL V CC 1.0V, I SINK = 50µA 0.3 V CC 2.7V, I SINK = 1.2mA 0.3 V CC 4.5V, I SINK = 3.2mA 0.4 I LKG V CC > V TH, reset not asserted 1 µa μa V ms V 4

TYPICAL PERFORMANCE CHARACTERISTICS V CC = 5V, C SRT = 1500pF, T A = +25, unless otherwise noted. Supply Current (μa) Supply Current vs. Supply Voltage 5 +85 4 3 +25 2-40 1 V TH = 1.63V 0 0 1 2 3 4 5 6 Supply Voltage (V) Reset Timeout Period (ms) Reset Timeout Period vs. C SRT 10000 1000 100 10 1 0.1 0.01 0.1 1 10 100 1000 C SRT (nf) Reset Timeout Period (μs) 500 460 420 380 340 Reset Timeout Period vs. Temperature C SRT = 0 Reset Timeout Period (ms) 5.0 4.8 4.6 4.4 4.2 Reset Timeout Period vs. Temperature C SRT = 1500pF 300-50 -25 0 25 50 75 100 4.0-50 -25 0 25 50 75 100 Temperature ( ) Temperature ( ) Normalized Reset Threshold 1.006 1.004 1.002 1.000 0.998 0.996 Normalized Reset Threshold vs. Temperature Transient Duration (µs) 60 50 40 30 20 10 Maximum Transient Duration vs. Reset Threshold Overdrive V TH = 2.93V 0.994-50 -25 0 25 50 75 100 Temperature ( ) 0 0 200 400 600 800 1000 Reset Threshold Overdrive (mv) 5

TYPICAL PERFORMANCE CHARACTERISTICS V CC = 5V, C SRT = 1500pF, T A = +25, unless otherwise noted. 6

DETAILED DESCRIPTION Reset Output The reset output is typically connected to the reset input of a µp. A µp s reset input starts or restarts the µp in a known state. The µp supervisory circuit provides the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions. changes from high to low whenever V CC drops below the threshold voltage. Once V CC exceeds the threshold voltage, remains low for the capacitoradjustable reset timeout period. This device output is guaranteed valid for V CC > 1V. The is open-drain output. Connect an external pull up resistor to any supply from 0 to 5.5V. Select a resistor value large enough to register a logic low when is asserted and small enough to register a logic high while supplying all input current and leakage paths connected to the line. A 10kΩ to 100kΩ pull up is sufficient in most applications. Selecting a Reset Capacitor The reset timeout period is adjustable to accommodate a variety of µp applications. Adjust the reset timeout period (t RP ) by connecting a capacitor (C SRT ) between SRT and ground. Calculate the reset timeout capacitor as follows: C SRT = (t RP - 340 10-6 ) / (2.6 10 6 ) where t RP is in seconds and C SRT is in farads. The reset delay time is set by a current/capacitorcontrolled ramp compared to an internal 0.6V reference. An internal 210nA ramp current source charges the external capacitor. The charge to the capacitor is cleared when a reset condition is detected. Once the reset condition is removed, the voltage on the capacitor ramps according to the formula: dv/dt = I/C. The C SRT capacitor must ramp to 0.6V to deassert the reset. C SRT must be a low-leakage (<10nA) type capacitor; ceramic is recommended. Operating as a Voltage Detector The can be operated in a voltage detector mode by floating the SRT pin. The reset delay times for V CC rising above or falling below the threshold are not significantly different. The reset output is deasserted smoothly without false pulses. 7

APPLICATION INFORMATION Interfacing to Other Voltages for Logic Compatibility The open-drain output of the can be used to interface to µps with other logic levels. As shown in Figure 1, the open-drain output can be connected to voltages from 0 to 5.5V. This allows for easy logic compatibility to various µps. Wired-OR Reset To allow auxiliary circuitry to hold the system in reset, an external open-drain logic signal can be connected to the open-drain of the, as shown in Figure 2. This configuration can reset the µp, but does not provide the reset timeout when the external logic signal is released. 3.3V V CC VCC 5.0V - + VREF 10kΩ V CC 10kΩ μp SRT TIMEOUT 5V SYSTEM N CSRT GND GND OPEN-DRAIN LOGIC Figure 1. Open-Drain Output Allows Use with Multiple Supplies Negative-Going V CC Transients In addition to issuing a reset to the µp during power-up, power-down, and brownout conditions, this supervisor is relatively immune to short-duration negative-going transients (glitches). The graph Maximum Transient Duration vs. Reset Threshold Overdrive in the Typical Performance Characteristics shows this relationship. The area below the curve of the graph is the region in which these devices typically do not generate a reset pulse. This graph was generated using a negative-going pulse applied to V CC, starting above the actual reset threshold (V TH ) and ending below it by the magnitude indicated (reset-threshold overdrive). As the magnitude of the transient decreases (further below the reset threshold), the maximum allowable pulse widthdecreases. Typically, a V CC transient that goes 100mV below the reset threshold and lasts 50µs or less does not cause a reset pulse to be issued. N Figure 2. Wired-OR Reset Circuit Layout Consideration SRT is a precise current source. When developing the layout for the application, be careful to minimize board capacitance and leakage currents around this pin. Traces connected to SRT should be kept as short as possible. Traces carrying high-speed digital signals and traces with large voltage potentials should be routed as far from SRT as possible. Leakage current and stray capacitance (e.g., a scope probe) at this pin could cause errors in the reset timeout period. When evaluating these parts, use clean prototype boards to ensure accurate reset periods. 8

PACKAGE OUTLINE DIMENSIONS SOT-23-5 D 1.90 e1 E1 E 2.59 0.99 b e 0.69 0.95 RECOMMENDED LAND PATTERN (Unit: mm) L A A1 A2 θ 0.2 c Dimensions In Millimeters Dimensions In Inches Symbol MIN MAX MIN MAX A 1.050 1.250 0.041 0.049 A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.650 2.950 0.104 0.116 e 0.950 BSC 0.037 BSC e1 1.900 BSC 0.075 BSC L 0.300 0.600 0.012 0.024 θ 0 8 0 8 9

TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS P2 P0 W Q1 Q2 Q1 Q2 Q1 Q2 B0 Q3 Q4 Q3 Q4 Q3 Q4 Reel Diameter P1 A0 K0 Reel Width (W1) DIRECTION OF FEED NOTE: The picture is only for reference. Please make the object as the standard. KEY PARAMETER LIST OF TAPE AND REEL Package Type Reel Diameter Reel Width W1 A0 B0 K0 P0 P1 P2 W Pin1 Quadrant SOT-23-5 7 9.5 3.2 3.2 1.4 4.0 4.0 2.0 8.0 Q3 10

CARTON BOX DIMENSIONS NOTE: The picture is only for reference. Please make the object as the standard. KEY PARAMETER LIST OF CARTON BOX Reel Type Length Width Height Pizza/Carton 7 (Option) 368 227 224 8 7 442 410 224 18 11