Arithmetic ircuits-2 Multipliers Array multipliers hifters Barrel shifter Logarithmic shifter EE 261 Krish hakrabarty 1 Binary Multiplication X = Σ X i 2 i i=0 Multiplicand M-1 N-1 Y = Σ Y i 2 i i=0 Multiplier Product Z = X * Y N-1 M-1 = Σ (Σ X i Y j 2 i+j ) i=0 j=0 Partial products Product = um of partial products EE 261 Krish hakrabarty 2
Multiplication Example: : 12 10 0101 : 5 10 EE 261 Krish hakrabarty 3 Multiplication Example: : 12 10 0101 : 5 10 EE 261 Krish hakrabarty 4
Multiplication Example: : 12 10 0101 : 5 10 0000 EE 261 Krish hakrabarty 5 Multiplication Example: : 12 10 0101 : 5 10 0000 EE 261 Krish hakrabarty 6
Multiplication Example: : 12 10 0101 : 5 10 0000 0000 EE 261 Krish hakrabarty 7 Multiplication Example: : 12 10 0101 : 5 10 0000 0000 0011 : 60 10 EE 261 Krish hakrabarty 8
Multiplication Example: : 12 10 0101 : 5 10 0000 0000 0011 : 60 10 multiplicand multiplier partial products product M x N-bit multiplication Produce N M-bit partial products um these to produce M+N-bit product EE 261 Krish hakrabarty 9 The Binary Multiplication 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 Multiplicand Multiplier AND operation 1 0 1 0 1 0 Partial Products 0 0 0 0 0 0 + 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 EE 261 Krish hakrabarty 10
General Form Multiplicand: Y = (y M-1,y M-2,, y 1, y 0 ) Multiplier: X = (x N-1, x N-2,, x 1, x 0 ) Product: P = y x = x y M 1 N 1 N 1M 1 j i i+ j j2 i2 i j2 j= 0 i= 0 i= 0 j= 0 y 5 y 4 y 3 y 2 y 1 y 0 x 5 x 4 x 3 x 2 x 1 x 0 multiplicand multiplier x 0 y 5 x 0 y 4 x 0 y 3 x 0 y 2 x 0 y 1 x 0 y 0 p 11 p0 x 1 y 5 x 1 y 4 x 1 y 3 x 1 y 2 x 1 y 1 x 1 y 0 x 2 y 5 x 2 y 4 x 2 y 3 x 2 y 2 x 2 y 1 x 2 y 0 x 3 y 5 x 3 y 4 x 3 y 3 x 3 y 2 x 3 y 1 x 3 y 0 x 4 y 5 x 4 y 4 x 4 y 3 x 4 y 2 x 4 y 1 x 4 y 0 p 10 p 9 p 8 p 7 p 6 p 5 p 4 p 3 p 2 p 1 x 5 y 5 x 5 y 4 x 5 y 3 x 5 y 2 x 5 y 1 x 5 y 0 partial products product EE 261 Krish hakrabarty 11 Dot Diagram Each dot represents a bit x 0 partial products multiplier x x 15 EE 261 Krish hakrabarty 12
The Array Multiplier x 3 x 2 x 1 x 0 y 0 x 3 x 2 x 1 x 0 Z 0 y 1 HA FA FA HA x 3 x 2 x 1 x 0 y 2 Z 1 Z 7 x 3 FA FA FA HA FA FA FA HA Z 6 x 2 Z 5 x 1 Z 4 x 0 Z 3 y 3 Z 2 FA: Full adder HA: Half adder (two inputs) Propagation delay =? EE 261 Krish hakrabarty 13 The MxN Array Multiplier ritical Path HA FA FA HA FA FA FA HA ritical Path 1 ritical Path 2 ritical Path 1 & 2 FA FA FA HA EE 261 Krish hakrabarty 14
arry-ave Multiplier HA HA HA HA HA FA FA FA HA FA FA FA arries saved for next adder stage HA FA FA HA Unique critical path Trade offs? EE 261 Krish hakrabarty 15 Adder ells in Array Multiplier P V DD A i V DD A A P P i V DD B A P B A P V DD i i P o A i Identical Delays for arry and um P EE 261 Krish hakrabarty 16
Multiplier Floorplan X 3 X 2 X 1 X 0 Y 0 Y 1 Z 0 HA Multiplier ell FA Multiplier ell Y 2 Z 1 Vector Merging ell Y 3 Z 2 XandYsignalsarebroadcasted through the complete array. Z 7 Z 6 Z 5 Z 4 Z 3 EE 261 Krish hakrabarty 17 Multipliers ummary Optimization Goals Different Vs Binary Adder Once Again: Ide ntify ritical Path Other poss ible techniques - Logarithmic versus Linear - Data encoding (Booth) - Pipe lining (Wallace tree multiplier) EE 261 Krish hakrabarty 18
omparators 0 s detector: A = 00 000 1 s detector: A = 11 111 Equality comparator: A = B Magnitude comparator: A < B EE 261 Krish hakrabarty 19 1 s & 0 s Detectors 1 s detector: N-input AND gate 0 s detector: NOTs + 1 s detector (N-input NOR) A 7 A 6 A 5 A 4 A 3 A 2 allones A 3 A 2 A 1 A 0 allzeros A 1 A 0 A 7 A 6 A 5 A 4 A 3 A 2 allones A 1 A 0 EE 261 Krish hakrabarty 20
Equality omparator heck if each bit is equal (XNOR, aka equality gate) 1 s detect on bitwise equality B[3] A[3] B[2] A[2] B[1] A[1] B[0] A[0] A = B EE 261 Krish hakrabarty 21 Magnitude omparator ompute B-A and look at sign B-A = B + ~A + 1 For unsigned numbers, carry out is sign bit B 3 A B N A B A 3 B 2 A 2 B 1 Z A = B A 1 B 0 A 0 EE 261 Krish hakrabarty 22
hifters Logical hift: hifts number left or right and fills with 0 s 1011 LR 1 = 0101 1011 LL1 = 0110 Arithmetic hift: hifts number left or right. Rt shift sign extends 1011 AR1 = 1101 1011 AL1 = 0110 Rotate: hifts number left or right and fills with lost bits 1011 ROR1 = 1101 1011 ROL1 = 0111 EE 261 Krish hakrabarty 23 The Binary hifter Right nop Left One-bit shifts A i B i A i-1 B i-1 Bit-lice i EE 261 Krish hakrabarty 24
Multi-bit hifters ascade one-bit shifters? omplex, unwieldy, slow for larger number of shifts Two other types of shifters Barrel shifter Logarithmic shifter EE 261 Krish hakrabarty 25 The Barrel hifter A 3 h1 B 3 hift by 0 to 3 bits A 2 B 2 h2 :DataWire A 1 B 1 : ontrol Wire h3 A 0 B 0 h0 h1 h2 h3 EE 261 Krish hakrabarty 26
The Barrel hifter Area dominated by wiring Propagation delay is theoretically constant (at most one transmission gate), independent of shifter size, no. of shifts Reality: apacitance on buffer input α maximum shift width EE 261 Krish hakrabarty 27 4x4 barrel shifter A 3 A 2 A 1 A 0 h0 h1 h2 h3 Width barrel ~ 2 p m M Buffer pm = metal/poly pitch M = no. of shifts EE 261 Krish hakrabarty 28
Logarithmic hifter taged approach, e.g. 7 = 1 + 2 + 4, 5 = 1 + 0 + 4 hifter with maximum shift width M consists of log 2 M stages h1 h1 h2 h2 h4 h4 A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 EE 261 Krish hakrabarty 29 0-7 bit Logarithmic hifter A 3 Out3 A 2 Out2 A 1 Out1 A 0 Out0 EE 261 Krish hakrabarty 30
Funnel hifter A funnel shifter can do all six types of shifts elects N-bit field Y from 2N-bit input hift by k bits (0 k < N) 2N-1 N-1 0 B offset + N-1 offset Y EE 261 Krish hakrabarty 31 Funnel hifter Operation omputing N-k requires an adder EE 261 Krish hakrabarty 32
Funnel hifter Design 1 N N-input multiplexers Use 1-of-N hot select signals for shift amount nmo pass transistor design (V t drops!) k[1:0] left Inverters & Decoder s 3 s 2 s 1 s 0 Y 3 Y 2 Z 6 Y 1 Z 5 Y 0 Z 4 Z 3 Z 2 Z 1 Z 0 EE 261 Krish hakrabarty 33 Funnel hifter Design 2 k 1 k 0 Log N stages of 2-input muxes left No select decoding needed Z 0 Y 0 Z 1 Y 1 Z 2 Y 2 Z 3 Y 3 Z 4 Z 5 Z 6 EE 261 Krish hakrabarty 34