Computers also need devices capable of Storing data and information Performing mathematical operations on such data

Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable of Storing data and information Performing mathematical operations on such data Refer to such devices as memory devices argon Flip Flops Concept of State State escribe system by set of variables Called state variables escribe system state as set of values for such variables Each set of values represents unique state When value of variable changes State of system changes In traditional logic Simple memory device has two states Binary 0 Binary 1 evice will remain in state until changed State Changes Set of state changes with time Called behavior of system For simple systems can exhaustively name each state For more complex systems Perhaps describe by some form of algorithm or formula

State iagram State diagram one means for describing behavior of system Each state represented by circle Assign name to circle to indicate name of the state Name usually simple and descriptive For a memory device Have two states 0 1 2 Coins Initial Final Need two circles 1 We show the transition between two states Labeled directed line or arrow Head Final state Tail Initial state Label Identifies what caused the change Output of system If appropriate Such diagram called State iagram Example 0 1 Can use to describe behavior of student Says If in state awake Input boring lecture Change to state asleep Input fall off chair Change to state awake awake boring lecture fall off chair asleep State diagram becomes powerful tool for escribing behavior of many different kinds of systems Memory evices Set Reset Let s now look at variety of different memory devices Can build simple device from two inverting combinational logic devices Can be NAN or NOR Reset Consider following circuit Observe what happens if line labeled Set put at logical 0 Reset put at logical 1 goes to 0 Set not

~ goes to 1 Now Set put at logical 0 Reset put at logical 0 Observe nothing happens Next Set put at logical 1 Reset put at logical 0 goes to 1 ~ goes to 0 We have caused the device to change state Now Set put at logical 0 Reset put at logical 0 Observe once again nothing happens Next Set put at logical 0 Reset put at logical 1 goes to 0 ~ goes to 1 We have caused the device to change state Finally Set put at logical 0 Reset put at logical 0 Observe one more time nothing happens Examining the results By making either set or reset go to 1 Can place the device in a different state. When both inputs are at logical 0 evice remembers What state it s in and does not change Value of input Checking boundary conditions If both inputs are logical 1 Both and ~ are logical 0 State of device depends upon which one removed first We don t allow this condition

Can draw state diagram Have two states: {0, 1} Have two inputs {set, reset} 00 10 0 1 01 00 Tabular Format Can also describe such behavior in tabular form In actuality We don t allow input combination of 11 S R n+1 ~n+1 0 0 n ~n 0 1 0 1 1 0 1 0 1 1 1 1 S R n+1 ~n+1 0 0 n ~n 0 1 0 1 1 0 1 0 1 1 - - The second table reflects the proper behaviour ated R-S Latch As it currently stands evice called asynchronous Can change any time inputs change More useful to be able to control when state changes occur o this by adding specialized control signal Called gate Also referred to as a strobe We add this as follows Reset ate Set not Observe ate low Nothing can happen ate high State of set and reset line Propagated to output

Truth table now becomes S R ate n+1 ~n+1 0 0 0 n ~n 0 1 0 n ~n 1 0 0 n ~n 1 1 0 n ~n 0 0 1 n ~n 0 1 1 0 1 1 0 1 1 0 1 1 1 - - We use any one of 2 different logic symbols These reflect different ways device is gated For the circuit we ve been discussing Output follows the input When gate is a logical 1 Alternative Output follows input When gate is logical 0 We see those in following logic symbols S S R R In the diagram on the right Bubble indicates device enabled when gate low ated - Flip Flop Let s now modify circuit further We add third input to each input gate Re-label the input signals as and ate not Observe By connecting outputs back to input

Inputs to NOR gates must have opposite values o not have same situation as with R-S device ate low Nothing can happen as before ate high State of and line Propagated to output as shown in the truth table Truth table now becomes ate n+1 ~n+1 0 0 0 n ~n 0 1 0 n ~n 1 0 0 n ~n 1 1 0 n ~n 0 0 1 n ~n 0 1 1 0 1 1 0 1 1 0 1 1 1 ~n n Observe When both inputs 1 evice toggles to opposite state ate Can also observe another problem What is it Our logic symbols for the latch are given as In reality Rarely find latch Latch Let s now modify input circuit further

We remove one input Invert the remaining and Re-label the single input signal as not ate Observe Inputs to NOR gates must have Still have opposite values ate low Nothing can happen as before ate high State of line Propagated to output as shown in the truth table Truth table now becomes ate n+1 ~n+1 0 0 n ~n 1 0 n ~n 0 1 0 1 1 1 1 0 Observe evice tracks input SET CLR SET CLR ate

The logic diagrams for the latch become Master Slave evices Let s now look a bit more closely at the gates RS device Observe: If input changes while gate is high Change propagates to output Not something that is generally desirable To remedy situation Add extra level of buffering Circuit now becomes At the high level Set S S Reset R R and at a more detailed level Set Reset ~ We now refer to our device as a flip flop

Now note: First We now call the gate a clock Second Each constituent device still a latch Thus One enabled when clock is high Other enabled when clock is low High When clock is high Input signals sampled and stored In first stage Changes in input no longer reflected on output passed through inverter Low on input to second set of AN gates Blocks propagation Low When clock is low Input signals blocked First stage can no longer change Changes in input no longer reflected on output State of first stage propagated to output stage Observe that the output appears to change On the negative going clock edge In reality we change on the changing level of the gate That is the value stored in the master Transferred to slave when gate changes from high to low With the addition of inverter Can cause output change on rising edge Input stage called master Output stage called slave Tracks changes in input signal

The logic symbol for the device S S R R Our diagram shows a small triangle Such a symbol indicates output changes on an edge Preset and Clear We now add one final piece to the device Again let s work with the RS device It s often desirable to ensure that the device is in a known state At power on When not being used We accomplish this by using master Reset (clear) Places the output into the 0 state Set Places the output into the 1 state These are added to the circuit as follows Clear Set Reset Preset not We can extend the design To each of the other types of devices In a similar manner

Completing our logic symbols We now have Today Most of our work will be with type devices None the less devices are used when they can help us to simplify the overall logic esigning with Flip Flops and Latches Let s now look to see how we can use these devices To do some real work The simplest design is to implement what is called a register Registers Basic Registers and Latches Registers are used to hold things Form one small component of memory system in computer Often used for temporary storage High level view Collection of flip flops or latches Usually a binary number 4, 8, 16 bit register evices all have Common clock or gate May have common reset (and preset) Work as a unit Let s look at a 4 bit latch

The logic diagrams given as 4 Bit Latch 4 Bit Register Any values placed on the inputs ed or strobed to outputs With a simple inversion Can convert sense of strobe or clock Important point All values treated as a group Shift Registers Shift Right Shift Register Let s now look at a different kind of register Let s connect 4 flip flops in the following configuration A B C ata A B C Let s assume that the initial state of all devices Is logical 0

Now begin At time t 0 Let s put a 1 on the data input and issue one clock pulse The state of our flip flops looks like the following Time ata A B C t 0 1 0 0 0 0 t 1 0 1 0 0 0 After the clock pulse ata has been stored into the first flip flop At time t 1 Let s put a 0 on the data input and issue another clock pulse The state of our flip flops looks like the following Time ata A B C t 0 1 0 0 0 0 t 1 0 1 0 0 0 t 2 0 0 1 0 0 After the clock pulse A logic 0 has been stored into the first flip flop The logic 1 from the first flip flop has moved to the second At time t 2 Let s leave the 0 on the data input and issue another clock pulse The state of our flip flops looks like the following Time ata A B C t 0 1 0 0 0 0 t 1 0 1 0 0 0 t 2 0 0 1 0 0 t 3 0 0 0 1 0 After the clock pulse A logic 0 has propagated to the second flip flop The logic 1 from the second flip flop has moved to the third At time t 3

Let s leave the 0 on the data input and issue another clock pulse The state of our flip flops looks like the following Time ata A B C t 0 1 0 0 0 0 t 1 0 1 0 0 0 t 2 0 0 1 0 0 t 3 0 0 0 1 0 t 4 0 0 0 0 1 After the clock pulse A logic 0 has propagated to the third flip flop The logic 1 from the third flip flop has moved to the fourth Observe that with each clock pulse ata is shifted one position to the right Based upon this observation We can write two equations for describing the behaviour of the system For the 0 th flip flop 0 = data For the i th flip flop i = i-1 Shift Left Shift Registers How would we modify the design to implement a shift left shift register Shift Right by Two Shift Registers How would we modify the design to implement A shift right by two shift register Selectable Shift Right Shift Left Shift Registers How would we modify the design to implement A selectable shift right - shift left shift register Counting / ividing Counting and dividing are important tasks one quite frequently Counting

We use counters to accumulate events Count bits Identify when specified number of events have occurred etermine elapsed time ividers We use dividers produce lower frequency signal For higher one Let s look at simple designs ivide by Two Simplest divider is divide by two Observe If we take a flip flop Connect and to logical 1 device Vcc Since device will alternate states if inputs are both the same value Output will be as follows & Note Frequency is ½ that of input Can do the same thing with a

Observe we tie the! output back to the input Now let s connect the circuit as follows: ivide by 4 / 2 Bit Binary Count By connecting the! output of A to input of B VCC A B SET CLR SET CLR B will change state when!a transitions from low to high Timing diagram will now look like A B Circuit referred to as divide by 4 circuit Note also sequence of states Binary sequence Also known as 2 bit binary counter

State iagram given as 0 3 1 2 State Table given as Present State Next State 0 00 1 01 1 01 2 10 2 10 3 11 3 11 0 00 Configured as it is Flip flop B cannot change until after A changes As long as all we re doing is dividing No problem In many such stages cascaded Can lead to substantial delay Called asynchronous design ing of each stage not synchronized to master clock Better design Called synchronous Each stage clocked at same time Synchronized to clock Each output changes at approximately the same time State diagram and state tables unchanged VCC A B SET CLR SET CLR

ivide by 8 / 3 Bit Binary Count Let s look at a 3 bit binary sequence With 3 variables Will need 3 flip flops - one for each bit Let s look at the pattern Flip flop C changes state every other time B changes state whenever C is a 1 A changes state whenever B and C are 1 ABC 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 If we make the and inputs to C a logical 1 evice will continually alternate states This is the desired behaviour Thus C = 1 C = 1 If we connect the and inputs of B to C evice will toggle (change state) whenever C is a logical 1 Thus B = C or simply C B = C or simply C If we connect the and inputs of B to the and of B and C evice will toggle (change state) whenever both are logical 1 Thus A = BC A = BC Our circuit now looks like VCC A B SET SET SET CLR CLR CLR These counters are reasonably straight forward With a little practice and state table Can design almost by inspection What about more complex designs

Let s now begin to look at a more formal approach Formal esign efining Terms As first step in more formal approach to design Sequential circuits Need some definitions and background work first Will work with 3 bit binary counter from last example Repeating truth table Observe In making transition from state 0 to state 1 Flip flop C changes from 0 to 1 In making transition from state 1 to state 2 Flip flop C changes from 1 to 0 Let s call 0 to 1 transition an α change 1 to 0 transition an β change First Step Let s also draw a 3 variable arnaugh map Label variables as in counter above A B 0 1 C Eventually will need 3 maps One for each variable Start with map for variable C Begin with state 0 In state 0 C makes α change going to state 1 Next state 1 In state 1 C makes β change going to state 2 We identify changes for each of remaining states Map becomes Let s now do variable B Begin with state 0 In state 0 B is 0 and does not change going to state 1 Enter a 0 into state 0 Next state 1 In state 1 B makes α change going to state 1 Next state 2 In state 2 B is 1 and does not change going to state 3 Enter a 1 into state 2 0 0 α β 0 1 α β 1 1 α β 1 0 α β C

Next state 3 In state 3 B makes β change going to state 4 A B 0 1 C We identify changes for each of remaining states Map becomes 0 0 0 α 0 1 1 β 1 1 1 β 1 0 0 α B Finally let s now do variable A In states 0-2 A is 0 and does not change Enter a 0 into states 0-2 Next state 3 In state 3 A makes α change going to state 4 In states 4-6 A is 1 and does not change Enter a 1 into states 4-6 Next state 7 In state 7 A makes β change going to state 0 A B 0 1 C We identify changes for each of remaining states Map becomes eveloping Input Equations Next step is to use patterns in maps To develop input equations We associate these as follows 0 0 0 0 0 1 0 α 1 1 1 β 1 0 1 1 A Flip Flop Type Must Cover on t Care Terms Self Term R S α and β α Set input 1 for α and Must use β Reset input 0 for β α and β α input 1 for α and on t use β input 0 for β α and 1 α and 1 input None Must use We can now write the input equations for any flip flop directly from the maps Flip Flop Type C B A R S S C =!C R C = C S B =!BC R B = BC S A =!ABC R A = ABC C = 1 C = 1 B = C B = C A = BC A = BC C =!C B =!BC + B!C A =!ABC + A!C + A!B Observe: Equations for device same as we figured out earlier Let s look at another example We wish to design following counter

A B C 0 0 0 0 2 0 1 0 4 1 0 0 6 1 1 0 5 1 0 1 3 0 1 1 1 0 0 1 Observe Minterm 7 is missing We enter this as a don t care in the Map Forming the arnaugh maps we have A B 0 1 C 0 0 0 0 0 1 α 0 1 1 1 x 1 0 1 β A A B 0 1 C 0 0 α 0 0 1 β β 1 1 β x 1 0 α α B A B 0 1 C 0 0 0 β 0 1 0 1 1 1 α x 1 0 0 1 C Flip Flop Type C B A C = AB B = AC +!B!C A = B!C C =!A!B B = 1 A = 1 Additional Applications Three Bit Binary Up Counter Three Bit Binary own Counter Three Bit Selectable Binary Up own Counter ivide By Three Up Counter ohnson Counters Frequency Counter Interval Measurement