igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002
Naming Conventions In our text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edgetriggered elements flip-flops This leads to confusion however
Latch versus Register Latch stores data when clock is low Register stores data when clock rises Clk Clk Clk Clk
Latches
Latch-Based esign N latch is transparent when = 0 P latch is transparent when = 1 N Latch Logic P Latch Logic
Timing efinitions t su t hold t Register ATA STABLE t t c 2 q ATA STABLE t
Characterizing Timing t 2 Clk Clk t C 2 Register t C 2 Latch
Maximum Clock Frequency FF s LOGIC t p,comb t clk- + t p,comb + t setup = T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay
Positive Feedback: Bi-Stability V o1 V o1 V i2 V i 2 5Vo1 V i1 V o2 V i2 = V o1 V i 2 5 V o1 A C B V i1 = V o2
Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Converting into a MUX Forcing the state (can implement as NMOS-only)
Mux-Based Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) 1 0 0 1 Clk Clk In Clk Clk In
Mux-Based Latch
Mux-Based Latch M M NMOS only Non-overlapping clocks
Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair
Master-Slave Register Multiplexer-based latch pair I 2 T 2 I 3 I 5 T 4 I 6 I 1 T 1 M I 4 T 3
Volts Clk- elay 2.5 1.5 0.5 t c 2 q(lh) t c 2 q(hl) 2 0.5 0 0.5 1 1.5 2 2.5 time, nsec
Setup Time
Reduced Clock Load Master-Slave Register T 1 I 1 T 2 I 3 I 2 I 4
Avoiding Clock Overlap X A B (a) Schematic diagram (b) Overlapping clock pairs
Overpowering the Feedback Loop Cross-Coupled Pairs NOR-based set-reset S S S R 0 0 R R 1 0 1 0 0 1 0 1 1 1 0 0 Forbidden State
Cross-Coupled NAN Cross-coupled NANs Added clock V S M 2 M 4 R M 6 M 1 M 3 M 8 S M 5 M 7 R This is not used in datapaths any more, but is a basic building memory cell
(Volts) Volts Sizing Issues 2.0 3 S 1.5 2 W = 0.5 m m 1.0 W = 0.6 m m W = 0.7 m m 0.5 0.0 2.0 2.5 3.0 W/L 5 and 6 3.5 4.0 1 W = 0.8 m m W = 0.9 mm W = 1 mm 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time (ns) (a) (b) Output voltage dependence on transistor width Transient response
Storage Mechanisms Static ynamic (charge-based)
Making a ynamic Latch Pseudo-Static
More Precise Setup Time
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk-elay Inv1 CP T Clk- ata T Setup-1 Clock Time T Setup-1 t=0 Time
CN TG1 1 S M Inv2 M Clk-elay Inv1 CP T Clk- T Setup-1 Time Time
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk-elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk-elay Inv1 T Clk- CP ata Clock T Setup-1 Time T Setup-1 t=0 Time
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk-elay T Clk- Inv1 CP ata T Setup-1 Clock T Setup-1 Time t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk-elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk-elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk-elay Inv1 CP 0 T Clk- T Hold-1 Time Clock ata T Hold-1 t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk-elay Inv1 T Clk- CP 0 Clock T Hold-1 ata T Hold-1 Time t=0 Time
Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M T Clk- Clk-elay Inv1 CP 0 Clock T Hold-1 ata T Hold-1 Time t=0 Time
Other Latches/Registers: C 2 MOS V V M 2 M 6 M 4 X M 8 M 3 C L1 M 7 C L2 M 1 M 5 Master Stage Slave Stage Keepers can be added to make circuit pseudo-static
Insensitive to Clock-Overlap V V V V M 2 M 6 M 2 M 6 M 4 0 0 X M 8 X 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (0-0) overlap (b) (1-1) overlap
REG REG REG REG REG REG REG REG Pipelining a a log Out log Out b b Reference Pipelined
Other Latches/Registers: TSPC V V V V Out In In Out Positive latch (transparent when = 1) Negative latch (transparent when = 0)
Including Logic in TSPC V V V V PUN In 1 In 2 In PN In 1 In 2 Example: logic inside the latch AN latch
TSPC Register V V V M 3 M 6 M 9 Y M 2 X M 5 M 8 M 1 M 4 M 7
Pulse-Triggered Latches An Alternative Approach Ways to design an edge-triggered sequential cell: Master-Slave Latches ata Pulse-Triggered Latch L1 L2 L ata Clk Clk Clk Clk Clk
Pulsed Latches V V M 3 M 6 V G M 2 G M 5 M P X G M 1 M 4 M N (a) register (b) glitch generation G (c) glitch clock
Pulsed Latches Hybrid Latch Flip-flop (HLFF), AM K-6 and K-7 : P 1 x P 3 M 3 M 6 M 2 P 2 M 5 M 1 M 4
Hybrid Latch-FF Timing
Latch-Based Pipeline
Non-Bistable Sequential Circuits Schmitt Trigger In Out
Noise Suppression using Schmitt Trigger
CMOS Schmitt Trigger V M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter
Schmitt Trigger Simulated VTC 2.5 2.5 2.0 2.0 1.5 V M1 1.5 V X(V) 1.0 0.5 V M2 (V) V x 1.0 0.5 k = 1 k = 2 k = 3 k = 4 0.0 0.0 0.5 1.0 1.5 2.0 2.5 V in (V) Voltage-transfer characteristics with hysteresis. 0.0 0.0 0.5 1.0 1.5 2.0 2.5 V in (V) The effect of varying the ratio of the PMOS devicem 4. The width is k * 0.5 m. m
CMOS Schmitt Trigger (2) V M 4 M 3 M 6 In Out M 2 X M 5 V M 1
Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator
Transition-Triggered Monostable In ELAY t d Out t d
Monostable Trigger (RC-based) V In A R B Out C (a) Trigger circuit. In B V M (b) Waveforms. Out t t 1 t 2
Astable Multivibrators (Oscillators) 0 1 2 N-1 Ring Oscillator simulated response of 5-stage oscillator
Relaxation Oscillator I1 Out 1 I2 Out 2 R C Int T = 2 (log3) RC
Voltage Controller Oscillator (VCO) V M6 V M4 Schmitt Trigger restores signal slopes In M2 I ref M1 I ref V contr M5 M3 Current starved inverter 6 t ph L (nsec) 4 2 0.0 0.5 1.5 2.5 V co ntr (V) propagation delay as a function of control voltage
ifferential elay Element and VCO V o 2 V o 1 v 3 in 1 in 2 v 1 v 2 v 4 V ctrl delay cell 3.0 two stage VCO 2.5 V 1 V 2 V 3 V 4 2.0 1.5 1.0 0.5 0.0 2 0.5 0.5 1.5 time (ns) 2.5 3.5 simulated waveforms of 2-stage VCO