Reducing EMI Noise by Suppressing Power-Distribution Resonances Istvan Novak Distinguished Engineer, Signal and Power Integrity Sun Microsystems 1
Outline Introduction: revisiting the definition of EMI Possible resonances in PDN Suppressing resonances Conclusions 2
Introduction SI, PI, EMI In traditional view, the three disciplines are applied independently SI: 1D wave propagation effects Reflections, termination, crosstalk PI: 2D and 2.5D wave propagation effects Plane resonances, SSN due to via inductance EMI: 3D wave propagation effects EM interaction through distance (out-of system source) 3
Introduction SI, PI, EMI revisited More and more the interactions cant be ignored SI>EMI: Resonances on no-care signals may create EMI problems PI>EMI: Resonances on power distribution increase radiation PI>SI: Resonances on power distribution increase jitter and BER EMI>SI: conducted and radiated noise from in-system modules reduce BER In-system EMI is becoming an increasing problem 4
Trends in Power Distribution Design 60 50 40 30 20 10 0 0 I OL drive (ma) ABT BCT, 74F LVT, ALVT ALB, ALVC ALVT AC/ACT LVC Supply voltage: ALVC LV AC AUC AVC AH/AHCT AUP AVC ALVC AHC LVC 5V 3V 2.5V 1.8V 1.5V 1.2V 0.8V HC/HCT t pd (nsec) t pd 5 10 15 20 Source: Texas Instruments Logic Selection Guide, 2006; SDYU001Y http://www.ti.com Clock frequencies rise >> BW goes up Supply voltages drop >>more domains >>tighter tolerances >>higher currents >>lower PDN impedance 5
Trends in PDN Requirements Target impedance predicted in early 1998 Ztarget 1000 100 Frequency Current 10 1 0.1 Power Vdd Larry Smith, Power Distribution for High Performance Systems, Conference Class 4, EPEP98, West Point, NY, October 26-28, 1998 1992 1994 1996 1998 2000 6
PDN Trends Increasing number of independent supply rails (less room for planes and PDN components) Increasing system density (noise sources and sensitive circuits are closer). Note: scaling. Higher efficiency (lower losses create more high-frequency noise) Size and cost constraints (resonances may not be sufficiently suppressed) 7
PDN Design Process Worst-case PDN noise calculation Worst-case positive response [V] V p =V 0 -V 1 +V 2 Δt 2 Step response [V] Δt 1 V 2 Δt 2 V 0 Time [sec] Δt 1 V 1 V DC t=0 Worst-case peakto-peak transient: Vpp = 2*Vp - VDC Stimulus edge Log time [sec] Drabkin, et al, Aperiodic Resonant Excitation of Microprocessor power Distribution Systems and the Reverse Pulse Technique, Proc. of EPEP 2002, p. 175 8
PDN Design (1) Ideal response 1.0E-1 Impedance magnitude [ohm] Worst-case peakto-peak transient: 10mVpp/A 1.0E-2 1.25E-02 Step response [V] 1.00E-02 7.50E-03 5.00E-03 2.50E-03 0.00E+00-2.50E-03 Time [sec] 1.E-9 1.E-8 1.E-7 1.E-6 1.E-5 1.E-4 1.0E-3 Frequency [Hz] 1.E+2 1.E+4 1.E+6 1.E+8 C [uf] ESR [ohm] L [nh] R - 0.01-9
PDN Design (2) The practical best: R-L 1.E-1 Impedance magnitude [ohm] 1.25E-02 Worst-case peakto-peak transient: 10mVpp/A Step response [V] R-L 1.E-2 Frequency [Hz] 1.E-3 1.E+2 1.E+4 1.E+6 1.E+8 1.00E-02 7.50E-03 5.00E-03 R-L C [uf] - ESR [ohm] 0.01 L [nh] 0.15 2.50E-03 0.00E+00-2.50E-03 Time [sec] 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 10
Impedance magnitude [ohm] 1.E-01 1.E-02 PDN Design (3) PDN comparison with voltage positioning Frequency [Hz] 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 1.E-03 Step response [V] 1.2E-02 1.0E-02 8.0E-03 Worst-case peak-to-peak transient: R-L: 10 mvpp/a, blue trace Multipole: 15.7 mvpp/a, red trace Big-V : 21.4 mvpp/a, green trace 6.0E-03 4.0E-03 2.0E-03 Time [sec] 0.0E+00 1.E-9 1.E-8 1.E-7 1.E-6 1.E-5 1.E-4 11
Impedance magnitude [ohm] 1.E-01 1.E-02 PDN Design (4) PDN comparison without voltage positioning Frequency [Hz] 1.E+3 1.E+4 1.E+5 1.E+6 1.E+7 1.E+8 1.E-03 Step response [V] 1.2E-02 1.0E-02 8.0E-03 Worst-case peak-to-peak transient: R-L: 19 mvpp/a, blue trace Multipole: 25 mvpp/a, red trace Big-V : 27.5 mvpp/a, green trace 6.0E-03 4.0E-03 2.0E-03 Time [sec] 0.0E+00 1.E-9 1.E-8 1.E-7 1.E-6 1.E-5 1.E-4 12
PDN in the Frequency Domain DC sources: low frequency Bypass capacitors: mid frequency PDN planes, board and chassis features: high frequency 1.E+00 Impedance magnitude [ohm] 1.E-01 1.E-02 DC source Capacitors PCB 1.E-03 Frequency [Hz] 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 13
Potential PDN Resonances DC sources Peaking due to improper loop design High-frequency ringing due to switch parasitics Peaking between DC source and bulk capacitors Peaking between capacitor banks Peaking between capacitors and planes Structural resonances of PDN planes Structural resonances of boxes, enclosures 14
DC-source Resonance due to Loop Typical switching frequency is in the 0.1-1MHz range Typical loop peaking is in the tens of khz range No EMI concern, primarily a PI issue 1.E-01 Impedance magnitude [ohm] 1.E-02 1.E-03 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Frequency [Hz] 15
Converter Ringing Typical ringing frequency is in the 50 500 MHz range High-current converters may switch 100+ A Sensitive clock signals run on a few ma 80+ db ratio EMI and SI risk 16
Peaking Between DC Source and Bulk Impedance magnitude [ohm] Low-frequency peaking PI concern, no EMI risk 1.E+00 1.E-01 1.E-02 Unpowered Powered 1.E-03 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Frequency [Hz] 17
Peaking Between Capacitor Banks 1.E+00 Impedance magnitude [ohm] Low-frequency peaking PI concern, no EMI risk 1.E-01 1.E-02 1.E-03 1.E+07 Frequency [Hz] 1.E+08 18
Peaking Between Capacitors and Plane 1.E+01 Impedance magnitude [ohm] High-frequency peaking PI and EMI risk 1.E+00 1.E-01 1.E-02 1.E-03 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 Frequency [Hz] 19
Peaking Between Capacitors and Plane: How to Solve Matched termination Area capacitors Hardest peaking to suppress 20
Structural Plane Resonances 1.E-01 Impedance magnitude [ohm] High-frequency peaking PI and EMI risk 1.E-02 1.E-03 1.E+07 1.E+08 1.E+09 1.E+10 Frequency [Hz] 21
Structural Plane Resonances: How to Solve Options: Thin laminates Resistive termination Area capacitors 22
Structural Plane Resonances: Thin Laminates (Self-Z) Thin laminates: Dampen structural resonances Make it harder to suppress plane-capacitor resonances Magnitude of self impedance at center [ohm] 1.0E+02 1.0E+01 1.0E+00 1.0E-01 1.0E-02 1.0E-03 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 10 x10 planes Bare board Simulated, t = 10-mil 5-mil 2-mil 1-mil 0.5-mil 0.2-mil 0.1-mil 0.05-mil 0.02-mil 0.01-mil 23
Structural Plane Resonances: Thin Laminates (Transfer-Z) Magnitude of transfer impedance corner-to-center [ohm] 1.0E+02 1.0E+01 1.0E+00 1.0E-01 1.0E-02 1.0E-03 1.0E-04 1.0E-05 1.0E-06 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 10 x10 planes Bare board Simulated, t= 10-mil 5-mil 2-mil 1-mil 0.5-mil 0.2-mil 0.1-mil 0.05-mil (1.2um) 0.02-mil 0.01-mil 24
Structural Plane Resonances: Resistive Termination Implementation options: Discrete R-C Embedded R Controlled-ESR capacitors 1.4E-01 1.2E-01 1.0E-01 8.0E-02 6.0E-02 Impedance with and without DET [ohm] 2.2x 1.9x 1.E+00 Impedance magnitude [ohm] 4.0E-02 2.0E-02 0.0E+00 1.E-01 1.E+08 Frequency [Hz] 1.E+09 1.E-02 Frequency [Hz] T2000 CPU module High-current rail 1.E-03 1.E+02 1.E+04 1.E+06 1.E+08 25
Structural Plane Resonances: High-ESR and/or Area Capacitors 1.E+01 PDN impedance [ohm] Thin laminates require more capacitors Number of parts is proportional to plane area 1.E+00 1.E-01 1.E-02 High-ESR capacitors, large number 1.E-03 Low-ESR capacitors, medium number 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Frequency [Hz] 26
EMI from AC-DC Source With PSU #1 With PSU #2 Only the AC/DC power supply was changed 27
Conclusions High-frequency PDN resonances adversely affect EMI High-frequency PDN resonances may occur Inside AC-DC and DC-DC converters Between capacitors and planes In PCB structures In board and chassis features Best defence Not to excite resonances (F source < F resonances ) Minimise loop sizes and coupling areas Suppress resonances by impedance matching Suppress resonances with area capacitors 28
THANK YOU Istvan Novak Sun Microsystems istvan.novak@sun.c om 29