EE45/55: Digital Control Final Exam Review Fall 03
Exam Overview The Final Exam will consist of four/five questions for EE45/55 students based on Chapters 7 and a bonus based on Chapters 8 9 (students are free to work as many of the problems as they can). The example problems that follow are representative of what you will see on the exam
P.: Relating Time and Frequency Domain Specifications. Time constant, a 0.8.5. Rise time, Tr, note: this is a linear approx. 0.7 3. Time delay, Td, note: this is a linear approx. 4. Percent overshoot, PO e 00% 5. Peak time, T p d 4 3 6. Settling time, T or T n n n s% s5% n 7. Steady-state error, e e( ) See Chapter 3 ss n
Design Example Relating Specifications Design a osed loop system response that approx. a second order system with peak time, Tp 0.89s, d 4 and settling time Ts %.4 s. From the specs., n we have the constraints: 4 0.89 and.4 n n Solving these eqns. simultaneously yields 5 and 0.707 desired osed-loop poles are located at: n n n d 3.54 3.54 s j j j the CP is given by () s s s n n s s 7.08 5.06
Controller Design Example # Given the plant: G ( s) p s s design a lead cascade controller of the form: c G ( s) that places the desired osed-loop system poles at: s K s s p z lead lead ( s) s 7.08s 5.06 3.54 j3.54 (see prior design example for related time-domain specs.)
Controller Design Example # It is ear from a basic RL plot of the plant that the desired osed poles cannot be achieved by gain alone and that the resulting loci must be biased to move further into the left-half plane (see prior example for RL plot of this plant) Given these observations and the RL plot rules, it is reasonable to propose a lead compensator of the form: This results in t G ( s) c K s s 7.08 he following Type loop gain: Ls ( ) s s K 7.08
Controller Design Example # The location of the controller pole should be obvious from the RL rules, but can be calculated from the AC as: Ls () lead The control s 3.54 j3.54 s sp p s 3.54 j3.54 lead s 3.54 j3.54 7.08 KLs () s 3.54 j3.54 3.54 j3.54 ler gain can be calculated from the MC as: K 5.06 Ls () s
Design Verification Using Coefficient Matching It has been shown that the desired osed-loop characteristic polynominal (CP) is given by: Based on the proposed lead compensator form, we can calculate If we select ( ) 7.08 5.06 s s s the resulting loop gain as: Ks z lead K Ls () s p s s s s p lead zlead as noted previously, this results in a osedloop CP of the form (see prior controller topology analysis slide): lead ( s) s s p K s p sk lead lead Comparing coefficients of the two CPs yields: p lead 7.08 and K 5.06
Calculation of the Steady State Error The steady-state error to a unit step input is given by: lim e( t) k ss step t step where k is the position error constant given by: k p p e 5.06 lim L( s) lim s0 s0 s s 7.08 ess 0 step k Note: this result is due to the pole at zero in the loop gain! It can also be shown that e is finite, yet non-zero using the results of Chapter 3 p ss ramp p
P.: Sample Period Selection Based on the loop gain Ls ( ) and the cascade control topology (see prior analysis), we have: Y() s K 5.06 H ( s) Rs ( ) s s p K s 7.08s5.06 lead which agrees with the prior design specifications developed We can use the ( s) associated with H ( s) to selecte an appropriate sample rate for the related discrete time controller by noting from Chapter 3 that 50d s 00d T Since the osed-loop d n 3.54, an appropriate sample period for the desired osed-loop system dynamics is given by the interval 0.0 T 0.04
If we select transform to calculate Converting G c (s) to G c (z) T 0.0, we can use the inverse of the bilinear ( z) as shown: 5.06s 3.64z 3.7 s7.08 z0.8678 G ( z) G ( s) c c z G c s T z z s00 z Note: This transformation is commonly performed using a CAD package, like the cd() command in Matlab, as shown in the scripts posted on the ass web site that solve each of the Chapter 5 controller examples in the lecture notes using Matlab
Discrete Controller Implementation The cascade controller is physically implemented in hardware in the discrete time using the invere-z TF as shown: G c U( z) 3.64z3.7 3.64 3.7z ( z) Ez ( ) z0.8678 0.8678z z U z 0.8678 ( ) 3.64 3.7 z E( z) uk ( ) 3.64 ek ( ) 3.7 ek ( ) 0.8678 uk ( ) where uk ( ) is the control signal and ek ( ) is the error defined: ek ( ) rk ( ) yk ( )
P.3: Design Example Relating Specifications Design a osed loop system response that approx. a second order system with peak time, Tp 0.89s, d 4 and settling time Ts %.4 s. From the specs., n we have the constraints: 4 0.89 and.4 n n Solving these eqns. simultaneously yields 5 and 0.707 desired osed-loop poles are located at: n n n d 3.54 3.54 s j j j the CP is given by () s s s n n s s 7.08 5.06
If the system is sampled with a period of T 0.0, n 3.540.0 then r e T e 0.936 and T 3.54 0.0 0.0708 rad 4 d This implies that the discrete CP is given by: To check these results, solve for and : z z r z r z z ( ).8586 0.8680 ln r ln 0.936 0.707 ln r ln 0.936 0.0708 n Design Example Relating Specifications r T 0.0 ln ln 0.936 0.0708 5 n
Direct Digital Controller Design Example #3 Given the plant: Gp( s) sampled at T 0.0, G ZAS ( z) ss3 z 4.9475 0 0.9737 ( z0.980)( z0.948) design a lead-lag cascade controller of the form: G c ( z) lead lag p K z z z z z p z that places the desired osed-loop system poles at: r 0.936 and 0.0708 lead ( z) zr zr z 0.993 j0.0659.8585z0.8679 while producing zero steady-state error to a step input. z lag
Controller Design Example #3 It is ear from a basic RL plot of the plant that the desired osed poles cannot be achieved by gain alone and that the resulting loci must be biased to move left into the unit cire (see prior example for RL plot of the plant G ( Z)) Given these observations and the RL plot rules, it is reasonable to propose a lead-lag compensator of the form: K( z0.980) ( z0.948) Gc ( z) z z p T Applying AC and MC to Lz ( ): plead 0.8634 and K4.990 lead his results in a Type loop gain of the form: 4.94750 Kz0.9737 Lz ( ) z z p lead ZAS
P.4: Example of State Equation Soln. T Given the system with unit step input and x(0) [,0] : 0 x 0 x u 0 x x y 0 0u x The state transition matrix ( t) L si A c n c can be computed as shown: t s s s s e () t L c L t 0 s 0 e 0 s
Transfer Function Matrix Given the prior example, we can compue the system TF and IR as: H() s 0 Do these results agree with prior sta s ss 0 0 ss 0 s Y() s U() s h 0 t e () t 0 0 () t e t 0 e >> Ac=[0,;0, ];Bc=[0;];Cc=[,0];Dc=[0]; >> H_s=tf(ss(Ac,Bc,Cc,Dc)) Transfer function: s^ + s t te soln., see Matlab verification? >> zpk(h_s) zero/pole/gain: s (s+)
Example Discrete State Eqn. Given the sampled data system with T 0. and G ( s), find the discrete state space representation p s s t e As shown previously, c ( t) ; therefore, t 0 e T c ( ) d 0 0 T t e T T e t 0 e 0 e 0.095 Thus, Ad c( T ) and T 0. 0 0.905 T 0. 0.004840 0.00484 Bd c( ) d Bc 0 0.095 0.095 0 T 0. T T
Discrete Transfer Function Matrix Note: ( z) zi A d n d 0.095 z zz0.905 0 z 0.095 0 z 0.905 k kk 0.05k.00k.073 0.905 ( k) d k 0.050 0.905 z 0.905
Discrete Transfer Function Matrix Given the prior example, we can compute the system TF and IR as: 0.095 z z z 0.905 0.00484 0.095 0 z 0.905 Y( z) H( z) 0 0 U( z) 0.00484 z z z 0.905 0.095 hk ( ) 0 0.095 0.00484 z 0. 9675 z z 0.905 k kk 0.05k.00 k.073 0.905 0.00484 k 0.0500.905 0.095 0 ( k ) k 0.00 ( k) 0.054 0.9050 0.005 ( k)
P.5: Direct Controller Design By Synthesis It is often possible to design the controller z-tf directly from the given plant z-tf and the desired osed-loop z-tf as shown: H ( z) G ( z) G ( z) c ZAS G ( z) G ( z) c ZAS G This can le c ( z) H ( z) G ( z) H ( z) ZAS This requires the proper selection of H ( z) ad to some unique controller designs, only found in the discrete domain such as Deadbeat Controllers that deliver finite settling time; the trick is to design controllers that are implementable, e.g, are causal and stable!
Rules for Selecting H (s) Use the following rules for selecting resulting ( z) is implementable: ( z) to ensure the. H ( z) must have the same pole-zero deficit as G ( z) to ensure causality c. H ( z) must contain as zeros all of the zeros of G are outside the unit cire to ensure stability H ZAS ( z) that 3. Zeros of H ( z) must inude all of the poles of G ( z) outside the unit cire to ensure stability 4. H () to ensure e 0 ss step G ZAS ZAS Obviously, performance of the resulting controller on an accurate model of the plant G ( z) ZAS G c ( z) relies
If all of the poles and zeros of Rules for Selecting H (s) we can consider a desired analog prototype H which is mapped to where ( s) H s G ZAS n nsn 0 ( z) are inside the unit cire; H ( s) of the form: n nt nt nt e sin T, e cos T, e d d 0 d H ( z) st ( z) using z e as: and the gain K is selected to ensure that H () K 0 z Kz z
H ( z) Rules for Selecting H (s) z K z 0 z0 H ( z) K z ( ) H z z K z 0 G 0 z z0 z p z p with all poles/zeros inside the unit cire, by synthesis design: Assuming the plant has the form GZAS ( z) z G c ( z) G ZA H ( z) S( z) H( z) K zz p z p G zz z K z 0 0 0 Lz ( ) H K z ( z), as desired! Lz ( ) z z0
Example Based on Ch5 Example # Given the plant: Gp ( s) sampled at T 0.0, The fo s s3 4.9475 0 0.9737 z GZAS ( z) ( z0.980)( z0.948) and a desired analog prototype H ( s) of the form: 5 H ( s) s 7.07s5 llowing controller results from the synthesis design technique outlined above (see Ch6_ Ex6.m): 47.849 zz ( 0.980)( z0.948) Gc ( z) ( z0.9737)( z)( z0.868)
Bonus: