EE260: Digital Desig, Sprig 2018 EE 260: Itroductio to Digital Desig Arithmetic Biary Additio Complemet forms Subtractio Multiplicatio Overview Yao Zheg Departmet of Electrical Egieerig Uiversity of Hawaiʻi at Māoa 1-bit Adder Performs the additio of two biary bits. Four possible operatios: 0+0=0 0+1=1 1+0=1 1+1=10 Circuit implemetatio requires 2 outputs; oe to idicate the sum ad aother to idicate the carry. Performs 1-bit additio. Iputs: A 0, B 0 Half Adder Outputs: S 0, C 1 Idex idicates sigificace, 0 is for LSB ad 1 is for the ext higher sigificat bit. Boolea equatios: S 0 = A 0 B 0 +A 0 B 0 = A 0 Å B 0 C 1 = A 0 B 0 Truth Table A 0 B 0 S 0 C 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 Half Adder (cot.) S 0 = A 0 B 0 +A 0 B 0 = A 0 Å B 0 C 1 = A 0 B 0 -bit Additio Desig a -bit biary adder which performs the additio of two -bit biary umbers ad geerates a -bit sum ad a carry out. Block Diagram Logic Diagram Example: Let =4 C 1 A 0 B 0 1 bit half adder A 0 B 0 S 0 C out C 3 C 2 C 1 C 0 1 1 0 1 0 A 3 A 2 A 1 A 0 1 1 0 1 +B 3 B 2 B 1 B 0 +1 1 0 1 -------------- ---------- S 3 S 2 S 1 S 0 1 0 1 0 S 0 C 1 This requires 3-bit additio! Chapter 8: Arithmetic 1
EE260: Digital Desig, Sprig 2018 Full Adder Full Adder (cot.) Full adder (for higher-order bit additio) Combiatioal circuit that performs the additios of 3 bits (two bits ad a carry-i bit) C i+1 A i B i 1 bit full adder S i C i The K-maps for C i+1 : S i : A i A i B i C i 0 0 1 0 0 1 1 1 B i C i 0 1 0 1 1 0 1 0 A i B i C i S i C i+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Full Adder (cot.) Boolea equatios: Full Adder (cot.) C i+1 = A i B i + A i C i + B i C i S i = A i B i C i + A i B i C i + A i B i C i + A i B i C i = A i Å B i Å C i You ca desig full adder circuit directly from the above equatios (requires 3 ANDs ad 1 OR for C i+1 ad 2 XORs for S i ) Ca we do better? Full Adder usig 2 Half Adders A full adder ca also be realized with two half adders ad a OR gate, sice C i+1 ca also be expressed as: C i+1 = A i B i + A i B i C i + A i B i C i = A i B i + (A i B i + A i B i )C i = A i B i + (Ai Å B i )C i ad S i = A i Å B i Å C i A i B i S i -bit Combiatioal Adders Perform parallel multi-bit additio Ripple Carry Adder Simple desig Time cosumig. Why? (you ll see i a bit!) Carry Lookahead Adder More complex tha ripple-carry adder Reduces circuit delay C i C i+1 Arithmetic PJF - 11 Chapter 8: Arithmetic 2
EE260: Digital Desig, Sprig 2018 -bit Ripple Carry Adder Costructed usig 1-bit full adder blocks i parallel. Cascade the full adders so that the carry out from oe becomes the carry i to the ext higher bit positio. Example: 4-bit Ripple Carry Adder C 4 C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B0 -------------- S3 S2 S1 S0 Ripple Carry Adder Delay Circuit delay i a -bit ripple carry adder is determied by the delay o the carry path from the LSB (C 0 ) to the MSB (C ). Let the delay i a 1-bit FA be D. The, the delay of a -bit ripple carry adder is D. Carry Lookahead Adder Alterative desig for a combiatioal - bit adder. Practical desig with reduced delay at the expese of more complex hardware. Derived from a trasformatio of the ripple carry adder desig. Carry Lookahead Adder Desig From a FA, separate betwee carry geeratio (a ew carry sigal is geerated, i.e. C out =1) ad carry propagatio (a existig C i is propagated to C out ) Geerate: G i = A i B i : if 1, C i+1 =1 Propagate: P i = A i Å B i : if true, C i+1 = C i Full Adder (FA) Partial Full Adder (PFA) Carry Lookahead Adder Desig (cot.) A sigle bit of G/P logic does t help, but Cascaded G/P logic ca geerate the carry out of a block Bi Ai Ai Bi Si Ci+1 Ci Si Gi Pi Ci Chapter 8: Arithmetic 3
EE260: Digital Desig, Sprig 2018 Carry Lookahead Adder Desig (cot.) Carry Lookahead Adder (cot.) C i+1 = G i + P i C i PFA desig breaks S fuctioality apart from G/P fuctioality Does this (desig i previous slide) solve the log delay problem? No, carry out still ripples! Idea: use two levels of logic to geerate carry out of ay block C i i terms of carry i C 0 ad added bits A i ad B i Implemet: Block CLA Geerate/Propagate logic of a 4-bit CLA -- C 0 C -1 have a 2-gates delay C 1 = G 0 +P 0 C 0 C 2 = G 1 +P 1 C 1 = G 1 +P 1 (G 0 +P 0 C 0 ) = G 1 +P 1 G 0 +P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 C 0 C 4 = G 3 +P 3 G 2 +P 3 P 2 G 1 +P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 = G 0-3 + P 0-3 C 0 Group carry geerate Group carry propagate Decimal Arithmetic Desig circuits that perform decimal additio, subtractio, Iput is i biary coded form, ex. BCD BCD Decimal Adder: Requires 8 iputs (4 bits per decimal umber) 5 outputs idicate the decimal sum ad the carry Remember BCD additio rules: Add 0110 to the sum if it is greater tha 1010 to correct the carry bit Biary Coded Decimal (BCD) Adder C = K + z3z2 + z3z1 C 0 K Added Added 4-bit biary adder z3 z2 z1 z0 4-bit biary adder S3 S2 S1 S0 BCD sum Chapter 8: Arithmetic 4
EE260: Digital Desig, Sprig 2018 Complemets There are 2 types of complemets for each base-r system: Radix (r s) complemet, ex. 2 s complemet ad 10 s complemet. Dimiished radix (r-1 s) complemet, ex. 1 s complemet ad 9 s complemet. We examie oly 2 s ad 1 s complemets for base 2. Same cocepts hold for other bases (ex. decimal). 2 s Complemet For a positive digit umber N 2 i biary, the 2's complemet, 2C(N 2 ), is give by: { 2C(N 2 ) = 2 -N 2, if > 0 0, if = 0 Example: N 2 =1010 2C(N 2 ) = 2 4 -N 2 = 10000 2 1010 2 = 0110 2 Example: N 2 =11111 2C(N 2 ) = 2 5 -N 2 = 100000 2 11111 2 = 00001 2 2 s Complemet (cot.) Here s a easier way to compute the 2 s complemet: 1. Leave all least sigificat 0 s ad first 1 uchaged. 2. Replace 0 with 1 ad 1 with 0 i all remaiig higher sigificat bits. Examples: N = 1010 N = 01011000 01 10 10101000 1 s Complemet For a positive digit umber N 2 i biary, the 1's complemet, 1C(N 2 ), is give by: 1C(N 2 ) = (2-1) - N 2 Example: N 2 =011 1C(N 2 ) = (2 3-1)-N 2 = 111 2 011 2 = 100 2 Example: N 2 =1010 1C(N 2 ) = (2 4-1) - N 2 = 1111 2 1010 2 = 0101 2 Observatio: 1 s complemet ca be derived by just complemetig all the bits i the umber. Observatio Subtractio with Complemets Compare 1 s complemet with 2 s complemet: 2 -N = [(2-1) - N] + 1 Thus, the 2 s complemet ca be obtaied by derivig the 1 s complemet ad addig 1 to it. Example: N = 1001 2C(N) = 2 4 N = 10000 1001 = 0111 1C(N) = 2 4 1 - N = 1111 1001 = 0110 à 2C(N) = 1C(N) + 1 = 0110 + 0001 = 0111 To perform M-N = M+(-N), we may use a complemet form to represet the egative umber -N, ad perform a plai old additio. Need to be able to covert the result. Chapter 8: Arithmetic 5
EE260: Digital Desig, Sprig 2018 Subtractio with 2 s complemet If we use 2's complemets to represet egative umbers: 1. Form R I = M + 2C(N 2 ) = M + (2 -N) = M N + 2. 2. If there is a ozero carry out of the additio, M N, so discard that carry ad the remaiig digits are the result R = M-N. 3. Otherwise, M < N, so take the 2 s complemet of R I (=2 - R I = 2 - (M N + 2 ) = N M), ad attach a mius sig i frot, i.e., the result R is -2C([R I ] 2 ) = -(N-M). Example A = 1010100 (84 10 ), B = 1000011 (67 10 ) Fid R = A-B: 2C(B) = 0111101 (61 10 ) A+B = 1010100+0111101 = 10010001 Discard carry, R = 0010001 (17 10 ) Fid R = B-A: 2C(A) = 0101100 (44 10 ) B+A = 1000011+0101100 = 1101111 R = -2C(B+A) = -0010001 (-17) Subtractio with 1 s complemet If we use 1's complemets to represet egative umbers: 1. Form R I = M + 1C(N 2 ) = M + (2-1-N) = M N + 2-1. 2. If there is a ozero carry out of the additio, M N, so discard that carry ad add 1 to the remaiig digits. The result R = M-N. 3. Otherwise, M < N, so take the 1 s complemet of R I (=2-1 - R I = 2-1 - (M N + 2-1) = N M ), ad attach a mius sig i frot, i.e., the result R is -1C([R I ] 2 ) = -(N-M). Example A = 1010100 (84 10 ), B = 1000011 (67 10 ) Fid R = A-B: 1C(B) = 0111100 (60 10 ) A+B = 1010100+0111100 = 10010000 Discard carry ad add 1, R = 0010000 + 1 = 0010001 (17 10 ) Fid R = B-A: 1C(A) = 0101011 B+A = 1000011+0101011 = 1101110 R = -1C(B+A) = -0010001 (-17) Biary Adder/Subtractors If we perform subtractio usig complemets, we elimiate the subtractio operatio, ad thus, ca use a adder with appropriate complemeter for subtractio. Actually, we ca use a adder for both additio ad subtractio: Complemet subtrahed for subtractio Do ot complemet subtrahed for additio Thus, to form a adder-subtractor circuit, we oly eed a selective complemeter ad a adder. Biary Adder/Subtractors (cot.) The subtractio A-B ca be performed by takig the 2's complemet of B ad addig to A. The 2's complemet of B ca be obtaied by complemetig B ad addig oe to the result. A-B = A + 2C(B) = A + 1C(B) + 1 = A + B + 1 Chapter 8: Arithmetic 6
EE260: Digital Desig, Sprig 2018 4-bit Biary Adder/Subtractor 4-bit Biary Adder/Subtractor (cot.) Whe S=0, the circuit performs A + B. The carry i is 0, ad the XOR gates simply pass B utouched. Whe S=1, the carry ito the least sigificat bit (LSB) is 1, ad B is complemeted (1 s complemet) prior to the additio; hece, the circuit adds to A the 1 s complemet of B plus 1 (from the carry ito the LSB). XOR gates act as programmable iverters 4-bit Biary Adder/Subtractor (cot.) 4-bit Biary Adder/Subtractor (cot.) S=0 S=1 B 3 B 2 B 1 B 0 0 B 3 B 2 B 1 B 0 1 S=0 selects additio S=1 selects subtractio 4-bit Biary Adder/Subtractor (cot.) Whe C 4 = 0 ad S=1 it meas that A < B ad we must correct the result R 3 R 0 (see slide 15). Thus, we must compute 2 s complemet of R 3 R 0 : Use a specialized 2 s complemet circuit or Use the 4-bit Adder/Subtractor agai, with A 3 A 0 =0000, B 3 B 0 =R 3 R 0, ad S=1. Siged Biary Numbers Siged-magitude system: Siged umbers are represeted usig the MSB of the biary umber to idicate the umber s sig: If MSB is 0 à umber is positive If MSB is 1 à umber is egative Do ot cofuse with usiged umbers! Chapter 8: Arithmetic 7
EE260: Digital Desig, Sprig 2018 Siged Biary Numbers (cot.) For example: -10 10 is -1010 2 i usiged (- sig is implicit) 11010 2 i siged (- sig is idicated i MSB=1) Aother example: 1011 2 is 11 10 i usiged -3 10 i siged Siged Biary Numbers (cot.) To implemet siged-magitude additio ad subtractio we eed to separate the sig bit from the magitude bits, ad treat the magitude bits as a usiged umber (do correctio wheever ecessary). To avoid correctio, use the sigedcomplemet system. Siged-Complemet System The magitude of the egative umber is represeted i a complemet form (2 s or 1 s complemet). Ex.: Use 8-bits to represet -9 10 ad 9 10-9 10 is: 1001001 2 i siged-magitude 11110110 2 i siged-1 s complemet 11110111 2 i siged-2 s complemet 9 10 is 00001001 2 i ay of the above systems Siged-Magitude Additio-Subtractio To perform additio or subtractio of two umbers M ad N i siged-magitude, follow ordiary arithmetic rules: Same sigs: Add ad keep same sig. Differet sigs: Subtract N from M; if ed Borrow is 1, correct result by takig its 2 s complemet. Sig is egative. Example: M:00011001, N:10100101 N is egative, so fid M-N =0011001-0100101 =1110100, with ed borrow 1. This implies that M-N is a egative umber, so to correct fid its 2 s complemet 0001100. Result is 10001100. Siged-Complemet Additio Additio of two siged umbers, with egative oes represeted i siged-2 s complemet, is obtaied by addig the two umbers (icludig the sig bits). Carry out is discarded. Siged-Complemet Additio (cot.) Do ot get cofused readig egative umbers i siged-2 s complemet! Remember, if MSB is 1 the umber is egative ad you eed to fid the 2 s complemet of the magitude. Examples: (Assume 5-bit represetatios) 01010 (+10) 01010 (+10) 10110 (-10) 10110 (-10) +00101 (+5) +11011 (-5) +00101 (+5) +11011 (-5) 01111 (+15) 00101 (+5) 11011 (-5) 10001 (-15) Example: What s the decimal equivalet of 1001001 2? Negative umber, sice MSB=1 Magitude = 001001 2 s complemet of magitude = 110111 The umber is -55 10 Chapter 8: Arithmetic 8
EE260: Digital Desig, Sprig 2018 Siged-Complemet Subtractio Subtractio of two siged umbers, with egative oes represeted i siged-2 s complemet, is obtaied by takig the 2 s complemet of the subtrahed (icludig sig bit) ad add it to the miued. Discard carry out. Examples: (Assume 5-bit represetatios) 01010 (+10) 01010 (+10) 10110 (-10) 10110 (-10) -00101 -(+5) -11011 -(-5) -00101 -(+5) -11011 -(-5) 01010 (+10) 01010 (+10) 10110 (-10) 10110 (-10) +11011 +(-5) +00101 +(+5) +11011 +(-5) +00101 +(+5) 00101 (+5) 01111 (+15) 10001 (-15) 11011 (-5) The Overflow problem If the sum of two -bit umbers results i a +1 umber, the a overflow coditios is said to occur. Detectio of overflow ca be implemeted usig either hardware or software. Detectio depeds o umber system used: siged or usiged. Additio: The Overflow problem i Usiged System Whe Carry out is 1. Subtractio: Ca ever occur. Magitude of the result is always equal or smaller tha the larger of the two umbers. à Not REALLY a problem! The Overflow problem i Siged-2 s Complemet Remember that the MSB is the sig. But, the sig is also added! Thus, a carry out equal to 1 does ot ecessarily idicate overflow. Overflow ca occur ONLY whe both umbers have the same sig. This coditio ca be detected whe the carry out (C ) is differet tha the carry at the previous positio (C -1 ). The Overflow problem i Siged-2 s Complemet (cot.) Example 1: Let M=65 10 ad N=65 10 i a 8-bit siged-2 s complemet system. M = N = 01000001 2 M+N = 10000010 with C =0. This is clearly wrog! Brig C as the MSB to get 010000010 2 (130 10 ) which is correct, but requires 9-bits à overflow occurs. Example 2: Let M=-65 10 ad N=-65 10 i a 8-bit siged-2 s complemet system. M = N = 10111111 2 M+N = 01111110 with C =1. This is wrog agai! Brig C as the MSB to get 101111110 2 (-130 10 ) which is correct, but also requires 9-bits à overflow occurs. Overflow Detectio i Siged-2 s Complemet Overflow coditios is detected by comparig the carry values ito ad out of the sig bit (C ad C -1 ). -bit Adder/Subtractor with Overflow Detectio Logic V C C +1 C -bit Adder/Subtractor C =1 idicates overflow coditio whe addig/subtr. usiged umbers. V=1 idicates overflow coditio whe addig/subtr. siged-2 s complemet umbers Chapter 8: Arithmetic 9
EE260: Digital Desig, Sprig 2018 Biary Multiplier Biary multiplicatio resembles decimal multiplicatio: -bit multiplicad is multiplied by each bit of the m- bit multiplier, startig from LSB, to form partial products. Each successive set of partial products is shifted 1 bit to the left. Derive result by additio the m rows of partial products. Example: Biary Multiplier (cot.) Multiplier A=A 1 A 0 ad multiplicad B=B 1 B 0 Fid C = AxB: B 1 B 0 x A 1 A 0 A 0 B 1 A 0 B 0 + A 1 B 1 A 1 B ------------- 0 C 3 C 2 C 2 C 0 ------------------------- Biary Multiplier Circuit 2-bit by 2-bit multiplier Biary Multiplier Circuit 4-bit by 3-bit multiplier 4 bit by 3 bit yields a 7 bit result Half Adders are Sufficiet sice there is o Carry-i i additio to the two iputs to sum Arithmetic Chapter 8: Arithmetic 10