Combinational Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2010 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/
Combinational Circuits Analysis Procedure Design Procedure Binary Adder-Subtractor Decimal Adder Binary Multiplier Decoders Encoders Multiplexers Outlines DCD-04-2
Introduction Logic circuits for digital systems may be either combinational or sequential. A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. DCD-04-3
Combinational Circuits A combinational circuits 2 n possible combinations of input values n input variables Combinational Logic Circuit m output variables Specific functions Adders, subtractors, comparators, decoders, encoders, and multiplexers MSI circuits or standard cells DCD-04-4
Analysis Procedure Step 1: Label all gate outputs that are a function of input variables with arbitrary symbols but with meaningful names. Determine the Boolean functions for each gate output. Step 2: Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates. Step 3: Repeat the process outlined in step 2 until the outputs of the circuit are obtained. Step 4: By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables. DCD-04-5
Analysis Procedure Example A straight-forward procedure DCD-04-6
Analysis Procedure Example Step 1: F 2 = AB+AC+BC T 1 = A+B+C T 2 = ABC Step 2: T3 = F 2 'T 1 Step 3: F1 = T 3 +T 2 Step 4: F 1 = T 3 +T 2 = F 2 'T 1 +ABC = (AB+AC+BC)'(A+B+C)+ABC = (A'+B')(A'+C')(B'+C')(A+B+C)+ABC = (A'+B'C')(AB'+AC'+BC'+B'C)+ABC = A'BC'+A'B'C+AB'C'+ABC DCD-04-7
Truth Table DCD-04-8
Design Procedure The design procedure of combinational circuits Step 1: State the problem (system spec.) Step 2: From the specifications of the circuits, determine the required number of inputs and outputs and assign a symbol to each. Step 3: Derive the truth table that defined the required relationship between inputs and outputs Step 4: Obtain the simplified Boolean functions for each output as a function of the input variables. Step 5: Draw the logic diagram and verify the correctness of the design (manually or by simulation). DCD-04-9
Design Method and Constraint Functional description Boolean function HDL (Hardware description language) Verilog HDL VHDL Schematic entry Logic constraint number of gates number of inputs to a gate propagation delay number of interconnections limitations of the driving capabilities DCD-04-10
BCD to Excess-3 Code Conversion Digital Circuit Design DCD-04-11
BCD to Excess-3 Code Conversion Digital Circuit Design DCD-04-12
BCD to Excess-3 Code Conversion Digital Circuit Design Simplified functions z = D' y = CD +C'D' x = B'C + B'D+BC'D' w = A+BC+BD Efficient implementation z = D' y = CD +C'D'= CD + (C+D) x = B'C + B'D+BC'D = B'(C+D) +B(C+D)' w = A+BC+BD= A+ B(C+D) DCD-04-13
Logic Diagram for BCD to Excess-3 Code Converter Digital Circuit Design DCD-04-14
1-Bit Half Adder Half adder 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = (10) 2 two input variables: x, y two output variables: C (carry), S (sum) truth table S = x'y+xy'=x y= (x+y)(x'+y') C = xy= (x'+y')' S' = xy+x'y' S = (C+x'y')' DCD-04-15
Logic Diagram of 1-Bit Half Adder Digital Circuit Design DCD-04-16
Full-Adder The arithmetic sum of three input bits three input bits x, y: two significant bits z: the carry bit from the previous lower significant bit Two output bits: C, S 1-Bit Full Adder Sum Carry DCD-04-17
Logic Diagram of 1-Bit Full Adder Digital Circuit Design DCD-04-18
Logic Diagram of 1-Bit Full Adder Digital Circuit Design S = x'y'z+x'yz'+ xy'z'+xyz = x (y z) +x(y z) = x y z C = xy + xz + yz = xy + xyz + xy z + xyz + x yz = xy + z (x y + xy) = xy + z (x y) DCD-04-19
4-Bit Full Adder Binary adder DCD-04-20
Carry Lookahead Adder (1/7) Given Stage i from a Full Adder, we know that there will be a carry generated when A i = B i = "1", whether or not there is a carry-in. Alternately, there will be a carry propagated if the half-sum is "1" and a carry-in, C i occurs. These two signal conditions are called generate, denoted as G i, and propagate, denoted as P i respectively and are identified in the circuit. G i C i+1 A i B i P i C i S i Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-21
Carry Lookahead Adder (2/7) In the ripple carry adder: G i, P i, and S i are local function to each cell of the adder C i is also local function for each cell In the carry lookahead adder, in order to reduce the length of the carry chain, C i is changed to a more global function spanning multiple cells Defining the equations for the Full Adder in term of the P i and G i : P i = A B G = Ai Bi S = G + P i i i i = Pi Ci Ci+ 1 i i C i Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-22
Carry Lookahead Adder (3/7) C i+1 can be removed from the cells and used to derive a set of carry equations spanning multiple cells. Beginning at the cell 0 with carry in C 0 : C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 (G 1 + P 1 G 0 + P 1 P 0 C 0 ) = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-23
Carry Lookahead Adder (4/7) DCD-04-24
Carry Lookahead Adder (5/7) DCD-04-25
Carry Lookahead Adder (6/7) CLA GEN Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-26
Carry Lookahead Adder (7/7) This lookahead scheme could be extended to more than four bits; in practice, due to limited gate fan-in, such extension is not feasible. Instead, the concept is extended another level by considering group generate (G 0-3 ) and group propagate (P 0-3 ) functions: G Using these two equations: P 0-3 0-3 = = G P 3 3 P + 2 P P 1 3 P G 0 2 + C4 = G0-3 + P0-3 C0 P 3 P Thus, it is possible to have four 4-bit adders use one of the same carry lookahead circuit to speed up 16-bit addition. 2 G 1 + P 3 P 2 P 1 G C 4 = G 3 + P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 0 Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD-04-27
4-Bit Adder/Subtractor A-B = A+(2 s complement of B) 4-bit Adder-subtractor M=0, A+B; M=1, A+B +1 DCD-04-28
Overflow Discussion Overflow The storage is limited. Add two positive numbers and obtain a negative number Add two negative numbers and obtain a positive number V = 0, no overflow; V = 1, overflow Example: DCD-04-29
BCD Adder Add two decimal digits in BCD together with an input carry from a previous stage 9 inputs: two BCD's and one carry-in 5 outputs: one BCD and one carry-out Design approaches Since each input digit does not exceed 9, the output sum cannot be grater than 9+9+1 =19, where 1 denotes an input carry. A truth table with 19 entries Use two 4-bit binary full adders Modifications are needed if the binary sum > 9 C = 1 K = 1 Z 8 Z 4 = 1 Z 8 Z 2 = 1 modification: +6 C = K +Z 8 Z 4 + Z 8 Z 2 DCD-04-30
Truth Table of BCD Adder DCD-04-31
Logic Diagram of BCD Adder BCD BCD BCD DCD-04-32
Binary Multiplier DCD-04-33
4-Bit by 3-Bit Binary Multiplier DCD-04-34
Magnitude Comparator The comparison of two numbers outputs: A>B, A=B, A<B Design Approaches the truth table 2 2n entries - too cumbersome for large n use inherent regularity of the problem reduce design efforts reduce human errors Algorithm -> logic A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 A=B if A 3 =B 3, A 2 =B 2, A 1 =B 1 and A 0 =B 0 equality: x i = A i B i +A i 'B i ' (A=B) = x 3 x 2 x 1 x 0 (A>B) = A 3 B 3 '+x 3 A 2 B 2 '+x 3 x 2 A 1 B 1 '+x 3 x 2 x 1 A 0 B 0 ' (A<B) = A 3 'B 3 +x 3 A 2 'B 2 +x 3 x 2 A 1 'B 1 +x 3 x 2 x 1 A 0 'B 0 Implementation x i = (A i B i '+A i 'B i )' DCD-04-35
Four-Bit Magnitude Comparator DCD-04-36
An n-to-m decoder Decoder a binary code of n bits = 2 n distinct information n input variables; up to 2 n output lines only one output can be active (high) at any time DCD-04-37
Three-to-Eight Line Decoder x y z DCD-04-38
Demultiplexers Decoder with Enable /Demultiplexer a decoder with an enable input receive information on a single line and transmits it on one of 2 n possible output lines Digital Circuit Design 0 Two-to-four-line decoder with enable input DCD-04-39
Decoder with Enable /Demultiplexer Digital Circuit Design DCD-04-40
Expansion 4x16 Decoder two 3-to-8 decoder: a 4-to-16 decoder 4 16 decoder constructed with two 3 8 decoders DCD-04-41
Combinational Logic Implementation Digital Circuit Design Each output = a minterm Use a decoder and an external OR gate to implement any Boolean function of n input variables A full-adder S(x,y,x)=S(1,2,4,7) C(x,y,z)= S(3,5,6,7) DCD-04-42
Encoder z = D + D + D + D 1 3 5 7 y = D + D + D + D 2 3 6 7 x = D + D + D + D 4 5 6 Lan-Da 7 Van The encoder can be implemented with three OR gates. DCD-04-43
Encoder An implementation x=d 4 +D 5 +D 6 +D 7 y=d 2 +D 3 +D 6 +D 7 z=d 1 +D 3 +D 5 +D 7 limitations illegal input: e.g. D 3 =D 6 =1 the output = 111 (¹3 and ¹6) DCD-04-44
Priority Encoder Resolve the ambiguity of illegal inputs Only one of the input is encoded D 3 has the highest priority D 0 has the lowest priority X: don't-care conditions V: valid output indicator DCD-04-45
Priority Encoder 1 DCD-04-46
Priority Encoder x = D + D 2 3 y = D + D D 3 1 2 V = D + D + D + D 0 1 2 3 DCD-04-47
Multiplexer Select binary information from one of many input lines and direct it to a single output line 2 n input lines, n selection lines and one output line E.g.: 2-to-1-line multiplexer Two-to-one-line multiplexer DCD-04-48
4-to-1-Line Multiplexer DCD-04-49
Quadruple 2-to-1-Line Multiplexer Digital Circuit Design DCD-04-50
Boolean Function Implementation Using MUX MUX: a decoder + an OR gate Digital Circuit Design 2 n -to-1 MUX can implement any Boolean function of n input variable. Procedure: assign an ordering sequence of the input variable the rightmost variable (D) will be used for the input lines assign the remaining n-1 variables to the selection lines w.r.t. their corresponding sequence construct the truth table consider a pair of consecutive minterms starting from m 0 determine the input lines DCD-04-51
Boolean Function Implementation Using MUX Example: Given F(x,y,z) = S(1,2,6,7) Digital Circuit Design DCD-04-52
Boolean Function Implementation Using MUX Digital Circuit Design Example: Given F(A, B, C, D) = S(1, 3, 4, 11, 12, 13, 14, 15) DCD-04-53
Three-State Gate A multiplexer can be constructed with three-state gates. Output state: 0, 1, and high-impedance (open ckts) DCD-04-54
Four-to-One-Line Multiplexer DCD-04-55
Conclusion From this lecture, you have learned the follows: Adder/Subtractor Multiplier Decoder Encoder Multiplexer DCD-04-56