ECE38 Digital Logic Synchronous Sequential Circuits: State Diagrams, State Tables Dr. D. J. Jackson Lecture 27- Synchronous sequential circuits Circuits here a clock signal is used to control operation are called synchronous sequential circuits The term active clock edge refers to the clock edge that causes a change in state (positive or negative) Realied using combinational logic and one or more flip-flops To models for synchronous sequential circuits Moore model: circuit outputs depend only on the present state of the circuit Mealy model: circuit outputs depend on the present state of the circuit and the primary inputs Sequential circuits are also called finite state machines (FSM) Dr. D. J. Jackson Lecture 27-2
Moore versus Mealy machines Combinational circuit Flip-flops Combinational circuit f clock Moore state machine Combinational circuit Flip-flops Combinational circuit f clock Mealy state machine Dr. D. J. Jackson Lecture 27-3 Basic design steps We ill introduce techniques for sequential circuit design via a simple example Design a circuit that meets the folloing specifications: The circuit has one input,, and one output, All changes in the circuit occur on the positive edge of the clock signal Output = if the input as during the to immediately preceding clock cycles From this specification it is obvious that cannot depend solely of the value of Dr. D. J. Jackson Lecture 27-4 2
Sequences of signals The example input and output sequence belo aides in the description of the circuit Clock cycle t t t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t Dr. D. J. Jackson Lecture 27-5 State diagram The first step in designing an FSM is determining ho many states are needed and hich transitions are possible from one state to another No preset procedure for this The designer must think about hat the circuit is to accomplish A good beginning is to define a reset state that the circuit should enter hen poer is applied or hen a reset signal is received Dr. D. J. Jackson Lecture 27-6 3
State diagram For our example, assume the starting state is called A As long as =, the circuit should do nothing and = reset = A/= Dr. D. J. Jackson Lecture 27-7 State diagram When =, the circuit should remember this by transitioning to a ne state (B) This transition should occur at the next positive edge of the clock signal reset = A/= = B/= Dr. D. J. Jackson Lecture 27-8 4
State diagram When in state B and =, the circuit should remember this by transitioning to a ne state (C) reset = A/= = B/= C/= = Dr. D. J. Jackson Lecture 27-9 Complete state diagram reset = = A/= = = B/= = C/= Moore model state diagram = Dr. D. J. Jackson Lecture 27-5
State table A state diagram describes circuit functionality, but does not describe circuit implementation Translation to a tabular form is necessary The state table should contain All transitions from each present state to each next state for all valuations of the input signals The output,, is specified ith respect to the present state Present state Next state Output = = A A B B A C C A C Dr. D. J. Jackson Lecture 27- State assignment The states are defined in terms of variables (A, B, and C) Each state is represented by a particular valuation of state variables Each state variable is implemented ith a flip-flop Since three states have to be realied, it is sufficient to use to state variables Use y 2 y for the present state (present state variables) Use Y 2 Y for the next state (next state variables) Dr. D. J. Jackson Lecture 27-2 6
State-assigned table Present state y 2 y Next state = = Y 2 Y Y 2 Y Output A B C dd dd d Note the addition of the y 2 y = state. Although it is not used, it is needed for completeness. Dr. D. J. Jackson Lecture 27-3 Next-state and output maps K-maps are constructed from the state table for: Circuit outputs ( in this case) Inputs for the flip-flops (next-state K-maps) Constructing the next-state maps depends on the type of flip-flop (D, T, JK) used for the implementation D is the most straightforard: next-state maps are constructed directly from the state table since (t+)= + =D T and JK implementations ill be covered later Dr. D. J. Jackson Lecture 27-4 7
State table and next-state maps Present state y 2 y Next state = = Output Y 2 Y Y 2 Y A B C dd dd d y 2 y d d Y =y y 2 y 2 y d d Y 2 =(y +y 2 ) Dr. D. J. Jackson Lecture 27-5 State table and output map Present state y 2 y Next state = = Output Y 2 Y Y 2 Y A B C dd dd d y y 2 d =y 2 Dr. D. J. Jackson Lecture 27-6 8
Circuit diagram Y 2 D y 2 Y D y Clock Resetn Dr. D. J. Jackson Lecture 27-7 Timing diagram Clock t t t t t t t t t t t 2 3 4 5 6 7 8 9 y y 2 Dr. D. J. Jackson Lecture 27-8 9