USC-ISI The MOSIS Service BSIM3v3.1 Model Parameters Extraction and Optimization October 000 Henok Abebe ance C.Tyree
Table of Contents 1. Introduction and Motivation: -----------------------------------------------1. Model Equations: -------------------------------------------------------------3.1 Threshold and Subreshold Regions: --------------------------------3. The Effective Channel eng and Wid: ---------------------------6.3 Source/Drain Parasitic Resistance: ------------------------------------7 3. Junction Capacitance Model: -----------------------------------------------8 4. Parameter Extraction and Optimization Strategies: ---------------------9 5. References: -------------------------------------------------------------------16
-1-1. Introduction and Motivation: - BSIM3 was developed in an ort to solve e problems of semiempirical models and as a complement to BSIM 1-. It has extensive built-in dependencies of important dimensional and process parameters such as channel leng, wid, gate ide ickness, junction dep, doping concentration, and so on. The model has evolved rough ree different versions. The first version forms e original basis for e model but had some severe maematical problems. The second version was largely a correction of ese maematical difficulties, and several new parameters were introduced. The ird version at we are going to discuss here has become an industry standard for modeling deep-submicron MOS technologies. The model is suitable for bo digital and analog applications because of better modeling of e output conductance. It also offers binning parameters for improving e model fits for smaller devices.
-- The main motivation to prepare is report is to provide MOSIS customers wi information at help to understand e MOSIS parameter extraction and optimization procedure. MOSIS SPICE parameters are obtained from electrical measurements on a selected wafer and using a commercial extraction and optimization tool (Silvaco UTMOST III). We measure I- data on a large array of test transistors included in e MOSIS process Monitor. Model parameters are extracted using is I- data such at e simulated I- results compare closely wi e measured I- data. A parameter extraction phase pays close attention to physical significance of e primary model parameters while e optimization phases focus on e correction parameters at make e model fit e full range of device sizes in a particular process. The resulting parameter accuracy is tested by simulating benchmark test circuits (inverter and ring oscillator) contained on e MOSIS Process Monitor and comparing simulation results wi measurements.
-3- One must keep in mind at e BSIM33.1 model is only partly physical. Its physical foundation is more an overpowered by e very large number non-physical correction parameters at are used to get e model to work over a large range of channel dimensions in a deep sub-micrometer process. Each parameter value can vary not only from one fabrication process to anoer (even at e same feature size) but also from run to run by reflecting e actual measured transistor characteristics.. Model Equations: -.1. Threshold and Subreshold Regions:
-4- A) In e strong inversion region, e current along e channel of e transistor is given by: [1,] I µ C W µ 1 υ sat ( gs A bulk / ) - - - - - - - - - (.1.1) Where, A bulk (1 K φ 1 bs A 0 X j X dep [ 1 A ( ) ] gs gst X j X dep W B 0 B 1 }) 1 1 KETA* bs - - - - - - - - - (.1.) is e Threshold oltage : 0 D k 1 vt0w exp( D vt1 ( [exp( D l φ [exp( D t )]( sub bi l vt1w bs t0 φ) ) W l φ ) * tw ) exp( D k sub l bs t 0 k ( 1 exp( D vt1w )]( Etao 1 W NX l * tw Etab) 1) )]( φ bi ( k 3 φ) D k 3b vt0 bs T ) W [exp( D vt1 W l ) - - - - - - - (.1.3) t 0 φ For large device sizes eabove expression can be reduced in to: 0 0 is e ideal reshold voltage of a long channel device at zero volt substrate bias. Where bs bs bc k 1 ( φ is Substrate bias wi upper limit. [1,] 0.5[ bs bs bc φ ) k DETA bs ( bs bc k1 bs 0.9( φ - 4k DETA) ) bc 4 * DETA* bc, ] (.1.3b)
-5- If we examine equation (.1.1) for a very small drain/source voltage ( Abulk also ( ) is much less an one. W ( gs ) That will lead equation (.1.1) to become, I µ C (This is e classic equation of channel current for MOS device in elinear region.) Where µ µ Here µ value 0.05 ), we will see at ( µ 1 0 ( U is e parameter which represents elow field The coicents U, U by e vertical field. is emobility and given by a U c a * bs b )( gst and U c µ T 0 ) b U ( ) is gst T much less an ( υ ) mobility ( ideal ) and - - - - - - - - - (.1.4) mobility of a large device). are parameters at represent e reduction of e channel mobility sat gst t n * vt ln[1 φ 1 n * C qε N v is e ermal voltage, v From e above equation it is possible toshow at for large for gs less an, si gst ch t gs exp( )] n * vt gs exp( n * v KbT q will be proportional to [ exp( t off ) gs gs value, )] gst - - - - - - - - - (.1.5) gs - and following: B) The drain current equation in e subreshold region is given by e I gs Iso( 1 exp( ))exp( ) - - - - - - - (.1.6) v n* v t t
-6- Where I so µ o W qεsin ch v φ s t Cd n 1 N factor C C C it C C C D D ( c cd cb bs )[exp( vt1 ) exp( vt1 )] lt lt C εsit Xdep εsit X dep lt ( 1 Dvt bs ), ltw ( 1 Dvt wbs ) & lt 0 ε ε ε T X si dep ε - - - - - - - (.1.7) C) The drain current equation in e saturated region: I W * C ( A ) v gst bulk at sat at at (1 )(1 ) - - - - - -(.1.8) A ASCBE b b ac at 4 Where a 1 a Abulk RCWvsat ( 1 ) Abulk, b [ gst( 1 ) AbulkEsat 3 Abulk RCWvsatgst ] λ λ c E R C Wv, λ A A E sat A ASCBE sat gst sat gst 1 gst v, v is e carrier saturated velocity. sat sat µ f (PCM, PDIBC1, PDIBC, PDIBCB, P, DROUT) is called e early voltage. f (PSCBE1,PSCBE) is e early voltage due to e substrate current induced body ect. Detail expression for A & ASCBE vag can be found in [1,], here it is given as a function of e parameters... The Effective Channel eng and Wid: -
-7- The ective channel leng and wid model in BSIM3v3.1 is: W W X int W W drawn N WN N WN, N, W, W& WN are e leng parameter at represent e short channel ect.- - (..1) X is e difference between e drawn channel leng on e layout and e printed leng on e wafer. W WW WW W Wdrawn XW Wint DWG * DWB WN WWN WN WWN gst ( φs bs φs ) W W W, WN, WW, WWN, WW, DWG& DWB are e wid parameters at represent narrow channel ect. XW is e difference between e drawn channel wid on e layout and e printed wid on e wafer. Usually it is enough to extract X W W XW W int drawn drawn and W int int int for long channel device. are parameters at represent reduction of e channel leng and wid of e device due to Source / Drain diffuse. int & W int.3. Source/Drain Parasitic Resistance: - Model for e parasitic resistance is a simple expression using e channel current equation in e linear region:
-8- I R tot R ch R R ch is e channel resistance calculated from equation (.1.1) R ch I 1 µ C W µ 1 υ sat ( gs A bulk / ) 1 R is e parasitic resistance and given by : R R w [1 P rwg gst (10 P rwb 6 W ( φ ) s Wr bs φ s )] - - - - - - - (.3.1) Where R w, P rwg, P rwb & W r are e parasitic resistance parameters. 3. Junction Capacitance Model: - The Source and Drain capacitance is divided into two components, namely e area junction capacitance per unit area and e perimeter junction capacitance per unit leng.
-9- The total junction capacitance C Jcap is found from: C C * A C * P Jcap JA JP - - - - - (3.1) Where A is e total junction area. P is e total junction perimeter. The area junction capacitance and C JA C C M bs JA J ( 1 J ) if bs > 0 P bs M J CJ ( 1 ) if bs < 0 - - - -(3.) P b b The perimeter junction capacitance C C M bs JP Jsw( 1 Jsw ) if bs > 0 P and C JP bs CJSW ( 1 ) P bsw M JSW bsw if < 0 - - - -(3.3) bs 4. Parameter Extraction and Optimization Strategies: - MOSIS is using e following data measurement procedures for parameter extraction and optimization on a large array of test transistors included in e MOSIS Process Monitor.
-10- I s data @ ow oltage wi different values. gs bs I s data @ High oltage wi different values. gs bs I s data @ ow oltage wi different values. bs gs I s data @ High oltage wi different values. bs gs C s data (Junction capacitance s oltage) Additional electrical measurements on e MOSIS Process Monitor also determine values of e following parameters: T CGDO CGSO R sh - - - (Gate ide ickness.) - - - (Gate to Drain overlap capacitance.) - - - (Gate to Source overlap capacitance.) - - - (Sheet Resistance.) Parameter extraction for each process technology start wi an initial set of parameters at comes from, 1) endor supplied models. ) Previous MOSIS models. 3) Extracted models from physical fundamentals. Using ese setup parameters wi e above four extracted parameters from e MOSIS Process Monitor e following nine optimization strategies are implemented.[3] (Note: Interaction between parameters at are optimized in a given strategy is controlled by e maximum and minimum limit of each parameter. The strategy presented here is a standard optimization strategy and it may vary from one technology to e oer.)
-11- Strategy 1: (Parameters in Threshold and Subreshold Regions) This local strategy is applied for e wide W and long device only and e parameters are ose in equation (.1.3), (.1.4) & (.1.7). Target parameters are, µ, U, U, U, K, K, N & 0 0 a b c 1 factor off It requires data @ ow oltage wi different values. I s gs bs Strategy : (Threshold Shift ect parameters) This local strategy is applied for e narrow W and long device only and e parameters are ose in equation (.1.3)& (..1) Target parameters are Wint, K, DWG, DWB, W, WN, WW, WWN, W & K 3 0 3b I s data @ gs ow voltage wi different values required. bs Strategy 3: (Threshold Shift and Channel Resistance ects parameters)
-1- This local strategy is applied for e wide W and short device only and e parameters are ose in equation (.1.3), (.1.7), (..1)& (.3.1) Target parameters are int,, N, W, WN, R, D 0, D 1, D, NX, P & P w vt vt vt rwg rwb I s data @ gs ow voltage wi different values required. bs Strategy 4: (Threshold Shift and Channel Resistance ects Binning parameters) A good model result can be obtained for carefully chosen target device sizes, but e simulation characteristics vary widely from e actual device characteristics when e channel leng and wid are varied from large to very small device size. This problem is handled in approach known as Model Binning. BSIM3v3.1 follow e following implementation for all ose parameters listed in [1] at can be binned. As an example for parameter P,
-13- P WP P P0 W P 0 PP * W is parameter for e large device size. - - - - - - - - - - - -(4.1) P is Binning parameter for e leng variation. WP is Binning parameter for e wid variation. PP is Binning parameter for e leng times wid variation. This local optimization strategy is applied for e small device size only (short channel and narrow wid.) Target Binning parameters are P, PR and PK 0 w I s data @ ow voltage wi different values required. gs bs Strategy 5: (ow Bias Drain Saturated Current parameters.) This local optimization strategy uses different geometry and e parameters are ose in equation (.1.), (.1.8), & (4.1). Target parameters are A, v, B, Pv, B, & A I s data @ ow oltage wi different values required. For parameters A & A use wide W & long device. For parameter v For parameters B & B use narrow W & long devices. For e Binning parameter Pv 0 sat 1 sat 0 gs bs gs 0 sat gs use wide W & short devices. 0 1 sat use small size devices.
-14- Strategy 6: (ow Bias Output Resistance Parameters) The output resistance local optimization is e most difficult one and e user should careful in including or excluding certain device sizes. This strategy is usually applied for e short channel devices togeer wi e long channel. If e wide W and long device become e dominant factor for e optimization, is device can be excluded. This strategy and strategy #5 should be executed one after anoer several times to get a good result. The parameters at are going to be optimized in is strategy are ose in equation (.1.3), (.1.3b) & (.1.8). Target parameters are PCM, PDIBC1, PDIBC, P, DROUT, DETA, PSCBE1, PSCBE, ETA0,& DSUB. AG RDS s data @ ow oltage wi different values required. bs gs Strategy 7: (High Bias Drain Saturated Current parameters) This local optimization strategy uses different geometry and e parameters are ose in equation (.1.) & (4.1).
-15- Target parameters are KETA, WKETA, KETA, and PKETA. I s data @ High oltage wi different values required. bs gs For parameter KETA use wide W & long device only. For binning parameter WKETA use narrow W & long devices only. For binning parameter KETA use wide W & short devices only. For Binning parameter PKETA use small devices only. Strategy 8: (High Bias Output Resistance Parameters) This local optimization strategy is usually applied for e short channel devices togeer wi e long channel and e parameters at are going to be optimized in is strategy are ose in equation (.1.3) & (.1.8). Target parameters are ETAB and PDIBCB. RDS s data @ High voltage wi different values required. bs gs Strategy 9: (Junction Capacitance Parameters)
-16- This global optimization strategy uses e junction capacitance data to optimize e parameters listed in equation (3.) & (3.3). Junction capacitance verses voltage measurements are taken on two junction capacitors: One wi an area dominated structure and e oer wi a perimeter-dominated structure. Target parameters are C, M, P, C, M, and P J J b JSW Jsw bsw 5. References: - [1] Department of Electrical Engineering and Computer Sciences University of California, Burkeley. " BSIM3v3 Users' Manual (Final ersion),"1996. [] Daniel Foty," Mosfet Modeling wi Spice," Prentice - Hall, Inc.1997. [3] Silvaco Simulation Standard," ocal Optimization Templates in UTMOST III." O 9, No1, January 1998. for Extracting BSIM3v3.1 Parameters