Tani et al.: Multilayer Wiring Technology with Grinding Planarization (1/6) [Technical Paper] Multilayer Wiring Technology with Grinding Planarization of Dielectric Layer and Via Posts Motoaki Tani, Kanae Nakagawa, and Masataka Mizukoshi Device & Materials Laboratories, Fujitsu Laboratories Ltd., 10-1, Morinosato-Wakamiya, Atsugi City, Kanagawa 243-0197, Japan (Received June 29, 2010; accepted September 2, 2010) Abstract We have developed a novel fine-pitch multilayer wiring technology for wafer level packages using mechanical grinding. In this process, a dielectric film containing a rubber filler was first laminated and then cured over electroplated Cu posts. Second, the dielectric layer was subjected to mechanical grinding in order to expose the Cu posts. Finally, a Cu layer was deposited on the dielectric layer using electroless plating. Here, in order to improve the adhesion between the dielectric layer and the Cu layer, the dielectric layer was exposed to oxygen plasma and then chemically treated with a coupling agent. From this study, we found that the rubber filler enhances the adhesion strength between the dielectric layer and Cu wirings. Also, we successfully fabricated fine-pitch wirings with line/space of 5 μm/5 μm with the new process using the new dielectric film. Keywords: Grinding, Via Posts, Multilayer Wiring, Dielectric Surface, Coupling Agent 1. Introduction Currently, high-density packaging technologies are being investigated as part of an effort to develop highperformance devices with new and enhanced functionalities for the ubiquitous communication society of the future by not only downsizing the size of features but also by reducing their costs. Among contemporary packages, chip-size packages (CSPs) are considered a promising class of packages because of their small size, which is comparable to present day LSIs. Recently, with the progress achieved in the development of low-cost, fine-pitch wiring technology, the configuration of CSPs is gradually changing from packages in which an individual chip is mounted on a resin interposer to wafer level CSPs (WL-CSPs). In WL-CSP production, individual packages are made using a dicing process following the packaging and inspection processes. Therefore, WL-CSPs are considered small-size, low-cost packages in the semiconductor industry. Currently, extensive R&D work is being conducted on WL- CSPs to achieve ultra-high-performance semiconductor devices.[1 4] Generally, Cu/polyimide multilayer wirings are used for the redistributed wirings of WL-CSPs. Here, in order to make via-holes, expensive photosensitive polymers are used for the dielectric layer, and also, a dry-vacuum sputtering process is used to deposit the seed layer of the wirings. Therefore, there is a great need to develop a highthroughput, low-cost process to facilitate the widespread use of WL-CSPs. In this regard, several low-cost methods have been reported integrating bare chips through the build-up process and using epoxy dielectric films together with a wet process for direct metal plating.[5, 6] However, these methods have some shortcomings, which include chip damage from laser ablation during via-hole formation and high surface roughness due to the desmear treatment, which is considered to be a major obstacle to fine-pitch wire formation. This paper describes a novel fine-pitch wiring technology for WL-CSP fabrication that uses an epoxy dielectric film instead of a photosensitive polyimide, and all-wet processes for electroless plating and electroplating. Moreover, we introduce a via post method without laser abrasion which allows chip damage to be avoided. Using this process, we developed a new multi-layer wiring technology using simultaneous grinding planarization of the dielectric layer and via posts. We also investigated how the coupling agent would enhance the adhesion between the smooth dielectric surface and the Cu wiring. 1
Transactions of The Japan Institute of Electronics Packaging Vol. 3, No. 1, 2010 Fig. 1 Multi-layer wiring process using grinding planarization. 2. Experiments 2.1 Multilayer wiring process Figure 1 shows an outline of the multilayer wiring process using grinding planarization. After the lower dielectric layer was formed on a silicon wafer, the lower electrodes and via posts were formed on the dielectric layer using Cu electroplating. Next, an epoxy dielectric film was laminated over the via posts. After curing at 180 C for 1 hour, the dielectric layer was subjected to mechanical grinding in order to expose the Cu posts. Finally, the surface of the dielectric layer was chemically modified by treatment with oxygen plasma and a coupling agent. The wiring process on the dielectric layer includes (1) seed layer electroless plating, (2) photo resist patterning, (3) Cu electroplating, (4) photo resist removal, and (5) seed layer etching. 2.2 Grinding technology Figure 2 shows the schematic of the grinding planarization process for the via posts embedded in the dielectric layer. Although this process is generally used for silicon wafer thinning, for the first time ever, we utilized this method for grinding planarization of the dielectric layer with via posts. The grinding procedure involves (1) the formation of via posts on the wafer, (2) the lamination of the epoxy dielectric film over the posts and curing, (3) the attachment of the wafer to the chuck table, and (4) the simultaneous grinding of the via posts and dielectric layer. We used a vertical surface grinding machine manufactured by Nachi Fujikoshi Corporation, and a vitrified bonded diamond grinding wheel manufactured by A.L.M.T. Corporation. Fig. 2 Schematic of grinding planarization. 2.3 Adhesion improvement We introduced a novel technology for improving the adhesion between the dielectric layer and the Cu wirings. Here, the epoxy dielectric surface was exposed to oxygen plasma to generate hydroxyl functional groups. Next, the dielectric surface was treated with a silane coupling agent that has two chemical functionalities: namely, to form chemical bonds with the surface OH groups of the dielectric layer, and to form coordination bonds with the Pd atoms of the electroless Cu plating as the seed layer. Then, electroless Cu plating was done. The condition for the oxygen plasma exposure was 300 W for 5 minutes. In our previous work, we have reported on a new dielectric material containing a rubber filler to obtain a high concentration of hydroxyl groups through oxygen plasma exposure.[7, 8] In the present study, we selected the mercapto group as the functional group of the coupling agent, γ-mercaptopropyltrimethoxysilane. After the oxygen plasma exposure, the dielectric surface was treated with 1 5 wt% 2
Tani et al.: Multilayer Wiring Technology with Grinding Planarization (3/6) of the coupling agent in a solution, and then heated to 120 C for 30 minutes to dehydrate. Figure 3 illustrates the concept of the adhesion improvement, and Figure 4 illustrates the wire formation process flow. 2.4 Observation of surface morphology and measurement of surface roughness The surface morphology of the dielectric layer was observed using a FE-SEM (JEOL JSM-6320F, Japan). The surface roughness was measured using DECTAK from Sloan Technology and AFM from Digital Instruments. 2.5 Measurement of peel strength After the electroless Cu plating, Cu electroplating was done to get a 30 μm thick Cu layer on the dielectric layer. Next, the Cu layer was heated to 180 C for 1 hour. Then, in the test specimen, a series of 1 cm wide cuts were made through the Cu layer. The peel strength was measured with a peel strength tester equipped with a digital force gauge. 3. Results and Discussion 3.1 Surface morphologies of the dielectric layer before and after grinding Figure 5 shows the FE-SEM images of the surface morphologies of the dielectric layer before and after grinding planarization. Before grinding, although the surface roughness is found to be at micrometer order depending on the rubber filler content, overall, it is considered smooth. On the contrary, after grinding, a few microscopic cavities are visible on the dielectric surface. However, because both the rubber filler and the epoxy dielectric film are ground at the same rate, a smooth dielectric surface can be obtained. 3.2 Surface morphologies of the dielectric layer with via posts after grinding Figure 6 shows a surface view of the dielectric surface with Cu via posts after planarization. 20 μm 20 μm square via posts with a post pitch of 40 μm are used in this study. From the observation of the surface after planarization, grinding marks are observed on the via posts. However, the surface morphology of the dielectric layer is the same as that in Figure 5. Moreover, no grinding residue is observed on the dielectric layer in the FE-SEM image of the surface view. 3.3 Surface morphologies of the dielectric layer after exposure to oxygen plasma Figure 7 compares the FE-SEM images of the surface morphologies of the dielectric layer containing the rubber filler after exposure to oxygen plasma and a conventional build-up dielectric layer after desmear treatment. The dielectric layer containing the rubber filler exhibits a smooth surface roughness (Rz) of about 0.5 μm. This roughness may be attributed to the different etching rates between the base epoxy resin and the rubber filler. On the other hand, the surface roughness of the conventional build-up dielectric layer with silica filler is found to be Fig. 3 Concept of adhesion improvement. Fig. 5 Surface morphologies of dielectric layer before and after grinding planarization. Fig. 4 Wire formation process flow. Fig. 6 Surface view of the dielectric surface with via posts after planarization. 3
Transactions of The Japan Institute of Electronics Packaging Vol. 3, No. 1, 2010 (a) After O2 plasma exposure of newly developed dielectric layer. (a) Before O 2 plasma exposure (b) After desmear treatment of conventional build-up dielectric layer. Fig. 7 Surface morphologies of dielectric layers. larger than 5 μm. 3.4 Generation of hydroxyl function after exposure to oxygen plasma The chemical binding energy of the oxygen at the dielectric surface containing the rubber filler was estimated using XPS. From the XPS narrow spectra of the dielectric surface as shown in Figure 8, it is confirmed that oxygen plasma exposure can generate hydroxyl groups on the surface. 3.5 Chemical bonding between the coupling agent and Pd catalyst In this study, the chemical bonding between the coupling agent and Pd catalyst of electroless Cu plating on the dielectric surface was investigated after the treatment with the coupling agent. Figure 9 shows XPS narrow spectra of S2p and Pd3d of the dielectric surface after Pd catalyst deposition. The S2p spectrum, which arises from the S- atoms of the coupling agent, exhibits peaks for S-C bonds and S-metal bonds. As no other metal is detected except for Pd, we believe that the S-metal peak is for Pd-S bonds. Also, Pd-S bonds are confirmed in the Pd3d spectrum. From this result, we can conclude that the Pd atoms bind to the S atoms of the coupling agent. 3.6 Relationship between the coupling agent concentration and the peel strength Figure 10 illustrates the effect of the coupling agent concentration on the peel strength when the oxygen plasma exposure time is 5 minutes. When the concentration is 2 wt%, the highest peel strength, which exceeds 8 N/cm, (b) After O 2 plasma exposure Fig. 8 XPS narrow spectra of O1s of dielectric surface. is obtained. We believe that if the coupling agent concentration is too low, the concentration of the surface modified mercapto groups would not be sufficient to establish strong adhesion. On the other hand, if the coupling agent concentration is too high, the coupling agent itself reacts, thereby interfering with the reaction between the mercapto groups and the Pd catalyst. Moreover, it can be concluded that we have achieved stronger peel strength in the new process because of the formation of chemical bonds between the Pd atoms and the S atoms of the silane coupling agent, as shown in Figure 9. 3.7 Fabrication of via-chain and fine-pitch wirings A test circuit pattern was successfully fabricated by grinding planarization of the dielectric layer containing the rubber filler and via posts formed by electroless plating and electroplating on a silicon substrate. 20 μm 20 μm square vias with a via pitch of 40 μm were fabricated in the test specimen. Figure 11 presents a cross-sectional view of a typical via-chain. We find that there is no damage to the silicon substrate and lower electrodes. Figure 12 and Figure 13 show the surface view and cross-sectional view 4
Tani et al.: Multilayer Wiring Technology with Grinding Planarization (5/6) (a) S2p Fig. 12 Surface view of fine-pitch wirings. Fig. 13 Cross-sectional view of fine-pitch wirings. (b) Pd3d XPS narrow spectra of S2p and Pd3d of dielectric sur- Fig. 9 face. of a 10 μm-pitch wire (line/space = 5 μm/5 μm) pattern, respectively. We confirm strong adhesion between the Cu wirings and the dielectric film with a smooth surface roughness of about 0.5 μm. Fig. 10 strength. Effect of coupling agent concentration on peel 4. Conclusion We developed a novel fine-pitch multilayer wiring technology by via formation using grinding planarization of the via posts embedded the dielectric layer as a promising process for future low-cost WL-CSP manufacturing. Although some grinding marks were visible after the grinding planarization step, no grinding residue was observed on the dielectric layer in the FE-SEM image of the surface view. The dielectric layer containing the rubber filler generated hydroxyl groups at its surface upon exposure to oxygen plasma, and through these hydroxyl groups, the coupling agent was fixed to the dielectric layer. As the mercapto groups of the coupling agent react with the Pd catalyst from the electroless Cu plating, a high peel strength, exceeding 8 N/cm, was achieved. Through this process, a high-density multilayer circuit with fine square vias of 20 μm 20 μm at a pitch of 40 μm and fine-pitch wirings with line/space of 5 μm/5 μm was fabricated. Fig. 11 Cross-sectional view of via-chain. Acknowledgements The authors are grateful to Hitachi Chemical Co., Ltd., for supplying the dielectric film containing the rubber fill- 5
Transactions of The Japan Institute of Electronics Packaging Vol. 3, No. 1, 2010 ers, and to A.L.M.T. Corporation for the grinding experiments. References [1] O. Yamagata, Embedded Wafer Level System in Package, Proceeding of 13th Microelectronics Symposium (MES2003), pp. 228 231, 2003. [2] T. Sakai and H. Eifuku, Application of Epoxy Encapsulated Solder Connection 4th (ESC4) Process to CSP (WL-CSP), 12th Symposium on Microjoining and Assembly Technology in Electronics, pp. 431 434, 2006. [3] T. Kobayashi, Y. Takita, H. Ito, Y. Takada, S. Takagi, and N. Hashimoto, The Development Embedding Inductors and Capacitors on Package using Wafer Level CSP Technology, Proceeding of 15th Microelectronics Symposium (MES2005), pp. 177 180, 2005. [4] M. Brunnbauer, E. Furgut, D. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kikuchi, and K. Kobayashi, An Embedded Device Technology Based on a Molded Reconfigured Wafer, 56th Electric Components and Technology Conference, pp. 547 551, 2006. [5] H. Braunisch, S. N. Towle, R. D. Emery, C. Hu, and G. J. Vandentop, Electrical Performance of Bumpless Build-up Layer Packaging, 52nd Electronic Components and Technology Conference, pp. 353 358, 2002. [6] C.-T. Ko, S. Chen, C.-W. Chiang, T.-Y. Kuo, Y.-C. Shih, and Y.-H. Chen, Embedded Active Device Packaging Technology for Next-generation Chip-in-substrate Package, CiSP, 56th Electronic Components and Technology Conference, pp. 322 329, 2006. [7] M. Tani, K. Nakagawa, and M. Mizukoshi, Fine-Pitch Wiring Technology Using Dielectric Surfaces Planarized by Grinding, 13th Symposium on Microjoining and Assembly Technology in Electronics, pp. 153 156, 2007. [8] M. Tani, K. Nakagawa, M. Mizukoshi, and M. Kato, Fine-Pitch Multilayer Wiring Technology for Packages using Via Posts and Grinding Planarization, THE IEICE TRANSACTIONS ON ELECTRONICS, Vol. J90-C, No. 11, pp. 734 740, 2007. 6