Multiplication of signed-operands

Similar documents
14:332:231 DIGITAL LOGIC DESIGN. 2 s-complement Representation

Complement Arithmetic

Lecture 8: Sequential Multipliers

14:332:231 DIGITAL LOGIC DESIGN. Why Binary Number System?

Binary Multipliers. Reading: Study Chapter 3. The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding

Numbering Systems. Contents: Binary & Decimal. Converting From: B D, D B. Arithmetic operation on Binary.

What s the Deal? MULTIPLICATION. Time to multiply

Lecture 8. Sequential Multipliers

Four Important Number Systems

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits

Chapter 5 Arithmetic Circuits

ECE260: Fundamentals of Computer Engineering

ENGIN 112 Intro to Electrical and Computer Engineering

ECE380 Digital Logic. Positional representation

UNSIGNED BINARY NUMBERS DIGITAL ELECTRONICS SYSTEM DESIGN WHAT ABOUT NEGATIVE NUMBERS? BINARY ADDITION 11/9/2018

EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters

Tree and Array Multipliers Ivor Page 1

Combinational Logic Design Arithmetic Functions and Circuits

Multiplication Ivor Page 1

Design of Sequential Circuits

Introduction to Digital Logic

Hakim Weatherspoon CS 3410 Computer Science Cornell University

Graduate Institute of Electronics Engineering, NTU Basic Division Scheme

Menu. Review of Number Systems EEL3701 EEL3701. Math. Review of number systems >Binary math >Signed number systems

Numbers and Arithmetic

Chapter 1: Solutions to Exercises

Numbers and Arithmetic

Conversions between Decimal and Binary

EE260: Digital Design, Spring n Digital Computers. n Number Systems. n Representations. n Conversions. n Arithmetic Operations.

CprE 281: Digital Logic

A field F is a set of numbers that includes the two numbers 0 and 1 and satisfies the properties:

CSCI 255. S i g n e d N u m s / S h i f t i n g / A r i t h m e t i c O p s.

Combinational Logic. By : Ali Mustafa

CHAPTER 2 NUMBER SYSTEMS

ELEN Electronique numérique

DIVIDER IMPLEMENTATION

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

COMPUTERS ORGANIZATION 2ND YEAR COMPUTE SCIENCE MANAGEMENT ENGINEERING UNIT 3 - ARITMETHIC-LOGIC UNIT JOSÉ GARCÍA RODRÍGUEZ JOSÉ ANTONIO SERRA PÉREZ

Binary Floating-Point Numbers

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

Divider Implementation

MATH Dr. Halimah Alshehri Dr. Halimah Alshehri

Design of Digital Circuits Reading: Binary Numbers. Required Reading for Week February 2017 Spring 2017

6.111 Lecture # 12. Binary arithmetic: most operations are familiar Each place in a binary number has value 2 n

Logic and Computer Design Fundamentals. Chapter 8 Sequencing and Control

0,..., r 1 = digits in radix r number system, that is 0 d i r 1 where m i n 1

Negative Bit Representation Outline

Carry Look Ahead Adders

Exam for Physics 4051, October 31, 2008

Binary addition example worked out

1. Revision Description Reflect and Review Teasers Answers Recall of Rational Numbers:

Introduction to Digital Logic Missouri S&T University CPE 2210 Subtractors

EXTENDING THE RESOLUTION OF PARALLEL DIGITAL-ANALOG CONVERTERS

Arithmetic in Integer Rings and Prime Fields

Chapter 2 Basic Arithmetic Circuits

CS 140 Lecture 14 Standard Combinational Modules

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H Lipasti. Fall 2010 University i of Wisconsin-Madison

Number Representation and Waveform Quantization

CSE 20 Discrete Math. Algebraic Rules for Propositional Formulas. Summer, July 11 (Day 2) Number Systems/Computer Arithmetic Predicate Logic

Systems I: Computer Organization and Architecture

9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017

CSE 241 Digital Systems Spring 2013

Design at the Register Transfer Level

Educjatipnal. L a d ie s * COBNWALILI.S H IG H SCHOOL. I F O R G IR L S A n B k i n d e r g a r t e n.

Hardware Design I Chap. 4 Representative combinational logic

Function Operations and Composition of Functions. Unit 1 Lesson 6

CS1800: Mathematical Induction. Professor Kevin Gold

What is Binary? Digital Systems and Information Representation. An Example. Physical Representation. Boolean Algebra

Cost/Performance Tradeoffs:

Commutative Rings and Fields

Spiral 2-4. Function synthesis with: Muxes (Shannon's Theorem) Memories

1. Introduction to commutative rings and fields

Chapter 1 CSCI

CprE 281: Digital Logic

Lecture 2 Review on Digital Logic (Part 1)

ELE2120 Digital Circuits and Systems. Tutorial Note 10

Numbering Systems. Computational Platforms. Scaling and Round-off Noise. Special Purpose. here that is dedicated architecture

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Unit 6 Study Guide: Equations. Section 6-1: One-Step Equations with Adding & Subtracting

On the Analysis of Reversible Booth s Multiplier

Representing signed numbers in Two s Complement notation

EXPERIMENT Bit Binary Sequential Multiplier

Discrete Mathematics. CS204: Spring, Jong C. Park Computer Science Department KAIST

Ex code

Example: x 10-2 = ( since 10 2 = 100 and [ 10 2 ] -1 = 1 which 100 means divided by 100)

Problem 1: Suppose A, B, C and D are finite sets such that A B = C D and C = D. Prove or disprove: A = B.

cse 311: foundations of computing Fall 2015 Lecture 11: Modular arithmetic and applications

Arithmetic Circuits-2

Efficient random number generation on FPGA-s

Power Optimization using Reversible Gates for Booth s Multiplier

Chapter 4 Number Representations

Residue Number Systems Ivor Page 1

Data byte 0 Data byte 1 Data byte 2 Data byte 3 Data byte 4. 0xA Register Address MSB data byte Data byte Data byte LSB data byte

Total Time = 90 Minutes, Total Marks = 100. Total /10 /25 /20 /10 /15 /20

ARITHMETIC COMBINATIONAL MODULES AND NETWORKS

Binary addition (1-bit) P Q Y = P + Q Comments Carry = Carry = Carry = Carry = 1 P Q

Lecture 11. Advanced Dividers

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

Module 2 LOSSLESS IMAGE COMPRESSION SYSTEMS. Version 2 ECE IIT, Kharagpur

Transcription:

Multiplication of signed-operands Recall we discussed multiplication of unsigned numbers: Combinatorial array multiplier. Sequential multiplier. Need an approach that works uniformly with unsigned and signed (positive and negative 2 s complement) n-bit operands. Booth s algorithm treats positive and negative 2 s complement operands uniformly. 1

2 Booth s algorithm Booth s algorithm applies uniformly to both unsigned and 2 s complement signed integers. Basis of other fast product algorithms. Fundamental observation: Division of an integer into the sum of block-1 s integers. Suppose we have a 16-bit binary number: 0110011011110110 This number can be represented as the sum of 4 block-1 integers: 0110000000000000 0000011000000000 0000000011110000 +0000000000000110 0110011011110110

3 Booth s algorithm (contd..) Suppose Q is a block-1 integer:q = 0000000001111000 = 120 Then: X.Q = X.120 Now: 120 = 128-8, so that X.Q = X.120 = X.(128-8) = X.128 - X.8 And: Q = 0000000001111000 128 = 0000000010000000 8 = 0000000000001000 If we label the LSB as 0, then the first 1 in the block of 1 s is at position 3 and the last one in the block of 1 s is at position 6. As a result: X.Q = X.120 = X.128 - X.8 = X.2 7 - X.2 3

4 Booth s algorithm (contd..) Representing Block-1 integers Q is an n-bit block-1 unsigned integer: -Bit position 0 is LSB. -First 1 is in bit position j -Last 1 is in bit position k Then: Q = 2 k+1-2 j Q.X = X.(2 k+1-2 j ) = X. 2 k+1 - X. 2 j

5 Booth s algorithm (contd..) Let Q be the block-1 integer: Q = 01111111111111110 To form the product X.Q using normal multiplication would involve 14 add/shifts (one for each 1-valued bit in multiplier Q). Since: Q = 2 15 2 1 X.Q = X.(2 15 2 1 ) Product X.Q can be computed as follows: 1. Set the Partial Product (PP) to 0. 2. Subtract X.2 1 from PP. 3. Add X.2 15 to PP. Note that X.2 j is equivalent to shifting X left j times.

6 Booth s algorithm (contd..) If Q is not a block-1 integer, Q can be decomposed so that it can be represented as a sum of block-1 integers. Suppose: Q = 0110011011110110 Q can be decomposed as: 0110000000000000 = 2 15-2 13 0000011000000000= 2 11-2 9 0000000011110000= 2 7-2 4 +0000000000000110 = 2 3-2 1 0110011011110110 Thus, Q.X = X.(2 15-2 13 + 2 11-2 9 +2 7-2 4 + 2 3-2 1 )

7 Booth s algorithm (contd..) Inputs: n-bit multiplier Q n-bit multiplicand x 2n-bit current Partial Product (PP) initially set to 0. (Upper half of PP is bits n-1 through n) Q has an added 0 bit attached to the LSB (Q has n+1 bits). Algorithm: For every bit in Q: 1. Examine the bit and its neighbor to the immediate right. If the bit pair is: 00 do nothing. 01 Add the multiplicand to the upper half of PP. 10 Sub the multiplicand from the upper half of PP. 11 Do nothing. 2. Shift the PP right by one bit, extending the sign bit.

8 Booth s algorithm (contd..) Example #1 01001100 Multiplicand X 01110111 Multiplier Q 00000000 00000000 Double-length PP register Step 0 bit pair 10 action: SUB 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 Shift Right 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 Step 1 bit pair 11 action: --- 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 Shift Right 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 Step 2 bit pair 11 action: --- 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 Shift Right 1 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 Step 3 bit pair 01 action: ADD 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 Shift Right 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 Step 4 bit pair 10 action: SUB 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 Shift Right 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 Step 5 bit pair 11 action: --- 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 Shift Right 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 Step 6 bit pair 11 action: --- 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 Shift Right 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 Step 7 bit pair 01 action: ADD 0 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 Shift Right 0 0 1 0 0 0 1 1 0 1 0 1 0 1 0 0 = Product: 9044

9 Booth s algorithm (contd..) Example #2 Multiplicand in Binary: 1 0 1 1 0 1 0 0 = -119 Multiplier in Binary: 0 1 1 1 0 1 1 1 = 76 Step 0 bit pair 10 action: SUB 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Shift Right 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 Step 1 bit pair 11 action: --- 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 Shift Right 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 Multiplier: Step 2 bit pair 11 Positive action: --- 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 Shift Right 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 Multiplicand: Step 3 bit pair 01 action: ADD 1 0 1 1 1 1 0 1 1 0 0 0 0 0 0 0 2 s comp. -ve Shift Right 1 1 0 1 1 1 1 0 1 1 0 0 0 0 0 0 Step 4 bit pair 10 action: SUB 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 Shift Right 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 Step 5 bit pair 11 action: --- 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 Shift Right 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 Step 6 bit pair 11 action: --- 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 Shift Right 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 Step 7 bit pair 01 action: ADD 1 0 1 1 1 0 0 1 0 1 0 1 1 0 0 0 Shift Right 1 1 0 1 1 1 0 0 1 0 1 0 1 1 0 0 = Product: -9044

10 Booth s algorithm (contd..) Example #3 Multiplicand in Binary: 1 0 1 1 0 1 0 0 = -119 Multiplier in Binary: 1 0 0 0 1 0 0 1= -76 Step 0 bit pair 10 action: SUB 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 Shift Right 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 Step 1 bit pair 01 action: ADD 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 Shift Right 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 Multiplier: Step 2 bit pair 00 action: --- 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 Shift Right 1 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 Step 3 bit pair 10 action: SUB 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 Shift Right 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 Step 4 bit pair 01 action: ADD 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 Shift Right 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 Step 5 bit pair 00 action: --- 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 Shift Right 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 Step 6 bit pair 00 action: --- 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 0 Shift Right 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 0 Step 7 bit pair 10 action: SUB 0 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 Shift Right 0 0 1 0 0 0 1 1 0 1 0 1 0 1 0 0 = Product: 9044 2 s comp. -ve Multiplicand: 2 s comp. -ve

11 Booth s algorithm and signed integers Booth s algorithm works correctly for any combination of 2 s complement numbers. If Q is a 2 s complement negative number, the Q is of the form: Q = 1 q n-2 q n-3 q n-4... q 1 q 0 And: V(Q) = -2 n-1 + q n-2 2 n-2 + q n-3 2 n-3 +... + q 2 2 2 + q 1 2 1 + q 0 2 0 If Q has no zeros, that is: Q = 111...11 = -1 Booth technique will: - See the first pair as 10 (subtract the multiplicand) - See all other pairs as 11 (do nothing) Thus, Booth technique will compute the result as required: 0 - X = -X = -1.X

Booth s algorithm and signed integers (contd..) Booth s technique is correct for an arbitrary ve 2 s complement number Q is a 2 s complement number: Q = 1 q n-2 q n-3 q n-4... q 1 q 0 V(Q) = -2 n-1 + q n-2 2 n-2 + q n-3 2 n-3 +... + q 2 2 2 + q 1 2 1 + q 0 2 0 If we read Q from MSB (left hand side), Q will have certain number of 1s followed by a 0. If the first 0 appears in the m th bit of Q. V(Q) = -2 n-1 + q n-2 2 n-2 + q n-3 2 n-3 +... + q 2 2 2 + q 1 2 1 + q 0 2 0 = ( -2 n-1 + 2 n-2 + 2 n-3 +... 2 m+1 ) + (q m-1 2 m-1 +... + q 2 2 2 + q 1 2 1 + q 0 2 0 ) = -2 m+1 + (q m-1 2 m-1 +... + q 2 2 2 + q 1 2 1 + q 0 2 0 ) Where ( -2 n-1 + 2 n-2 + 2 n-3 +... 2 m+1 ) = -2 m+1 Bit m is 0, so m-bit number starting from 0 is a positive number. Booth s algorithm will work correctly. Transitioning from bit m to m+1, algo sees the bit pair 10, causing it to subtract the multiplicand 2 m+1 from the PP. All other transition see pairs 11 which have no effect. 12