or 0101 Machine

Similar documents
The Design Procedure. Output Equation Determination - Derive output equations from the state table

3. Complete the following table of equivalent values. Use binary numbers with a sign bit and 7 bits for the value

Digital Circuit Engineering

Sequential Synchronous Circuit Analysis

Synchronous Sequential Circuit Design

FSM model for sequential circuits

Lecture 10: Synchronous Sequential Circuits Design

Digital Circuit Engineering

Week-5. Sequential Circuit Design. Acknowledgement: Most of the following slides are adapted from Prof. Kale's slides at UIUC, USA.

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering

CE1911 LECTURE FSM DESIGN PRACTICE DAY 1

11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output of

Synchronous Sequential Circuit Design. Digital Computer Design

Sequential Circuit Design

14.1. Unit 14. State Machine Design

Finite State Machine (FSM)

Finite State Machine. By : Ali Mustafa

Digital Logic and Design (Course Code: EE222) Lecture 19: Sequential Circuits Contd..

Clocked Synchronous State-machine Analysis

EGR224 F 18 Assignment #4

ECE380 Digital Logic. Synchronous sequential circuits

Topic 8: Sequential Circuits

Total time is: 1 setup, 2 AND, 3 XOR, 1 delay = (1*1) + (2*2) + (3*3) + (1*1) = 15ns

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017

Analysis and Design of Sequential Circuits: Examples

IE1204 Digital Design. L10: State Machines (Part 2) Masoumeh (Azin) Ebrahimi Elena Dubrova

Q: Examine the relationship between X and the Next state. How would you describe this circuit? A: An inverter which is synched with a clock signal.

Ch 7. Finite State Machines. VII - Finite State Machines Contemporary Logic Design 1

ELE2120 Digital Circuits and Systems. Tutorial Note 10

Lecture 14 Finite state machines

L10 State Machine Design Topics

CprE 281: Digital Logic

Clocked Sequential Circuits UNIT 13 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS. Analysis of Clocked Sequential Circuits. Signal Tracing and Timing Charts

EECS Components and Design Techniques for Digital Systems. FSMs 9/11/2007

FYSE420 DIGITAL ELECTRONICS

State & Finite State Machines

Menu. EEL3701 Classical Design

Chapter 4 Part 2 Sequential Circuits

10/12/2016. An FSM with No Inputs Moves from State to State. ECE 120: Introduction to Computing. Eventually, the States Form a Loop

Models for representing sequential circuits

CPE100: Digital Logic Design I

Chapter 6 Introduction to state machines

Synchronous Sequential Logic Part I. BME208 Logic Circuits Yalçın İŞLER

EE 209 Logic Cumulative Exam Name:

EET 310 Flip-Flops 11/17/2011 1

Sequential Circuit Analysis

Topic 8: Sequential Circuits. Bistable Devices. S-R Latches. Consider the following element. Readings : Patterson & Hennesy, Appendix B.4 - B.

Let s now begin to formalize our analysis of sequential machines Powerful methods for designing machines for System control Pattern recognition Etc.

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

Different encodings generate different circuits

State and Finite State Machines

Last lecture Counter design Finite state machine started vending machine example. Today Continue on the vending machine example Moore/Mealy machines

Lecture 17: Designing Sequential Systems Using Flip Flops

Lecture 14: State Tables, Diagrams, Latches, and Flip Flop

Logic Design II (17.342) Spring Lecture Outline

State & Finite State Machines

Synchronous Sequential Logic

Synchronous Sequential Circuit Design. Dr. Ehab A. H. AL-Hialy Page 1

ELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 7-10)

Chapter 15 SEQUENTIAL CIRCUITS ANALYSIS, STATE- MINIMIZATION, ASSIGNMENT AND CIRCUIT IMPLEMENTATION

ELE2120 Digital Circuits and Systems. Tutorial Note 9

EECS150 - Digital Design Lecture 23 - FSMs & Counters

King Fahd University of Petroleum and Minerals College of Computer Science and Engineering Computer Engineering Department

Appendix B. Review of Digital Logic. Baback Izadi Division of Engineering Programs

Synchronous Sequential Logic Part I

Parity Checker Example. EECS150 - Digital Design Lecture 9 - Finite State Machines 1. Formal Design Process. Formal Design Process

EECS150 - Digital Design Lecture 17 - Sequential Circuits 3 (Counters)

Lecture (08) Synchronous Sequential Logic

CARLETON UNIVERSITY Final rev EXAMINATION Fri, April 22, 2005, 14:00

Lab #10: Design of Finite State Machines

Lecture 13: Sequential Circuits, FSM

Computers also need devices capable of Storing data and information Performing mathematical operations on such data

SYNCHRONOUS SEQUENTIAL CIRCUITS

Mealy & Moore Machines

Lecture 8: Sequential Networks and Finite State Machines

CARLETON UNIVERSITY Final EXAMINATION April 13, 2009: 14:00

CSE370 HW6 Solutions (Winter 2010)

(Boolean Algebra, combinational circuits) (Binary Codes and -arithmetics)

Logic and Computer Design Fundamentals. Chapter 8 Sequencing and Control

Generalized FSM model: Moore and Mealy

Chapter 5 Synchronous Sequential Logic

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

ELCT201: DIGITAL LOGIC DESIGN

Logical design of digital systems

COE 202: Digital Logic Design Sequential Circuits Part 3. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

CHW 261: Logic Design

Homework #4. CSE 140 Summer Session Instructor: Mohsen Imani. Only a subset of questions will be graded

Asynchronous sequence circuits

6. Finite State Machines

Outcomes. Unit 14. Review of State Machines STATE MACHINES OVERVIEW. State Machine Design

Chapter 7 Sequential Logic

Adders allow computers to add numbers 2-bit ripple-carry adder

ELCT201: DIGITAL LOGIC DESIGN

State Graphs FSMs. Page 1

Appendix A: Digital Logic. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. Heuring

Digital Control of Electric Drives

Problem Set 9 Solutions

Sequential Logic (3.1 and is a long difficult section you really should read!)

Transcription:

Synchronous State Graph or Synchronous State Graph or Detector Design a state graph for a machine with: One input X, one output Z. Z= after receiving the complete sequence or Overlapped sequences are detected. Z= except for the single clock period after the sequence is received. Solution: Step : Block diagram and waveforms X CLK or Z Moore Output: Output rises in clock period after sequence is received RST x CLK z - Printed; 8/3/5 Slide 4 Modified; March 8, 25 John Knight Sequential Circuits p. 26 or Machine or Machine This machine recognizes two sequences. The sequences may overlap, so the end of one sequence may be the start of another. Step : By now, you should be able to write the input sequence as s and s, knowing that these are the final values of the input as they appear just before the next active clock edge. These sequences should illustrate various overlapping sequences. The output here is a Moore output, so it rises after the clock cycle in which the final appears. Step2: Draw the state graph. We will draw the graph for one sequence. Then do the other sequence. Then combine them. The Moore outputs are written in the bottom of the state circles. Remember that the next state is determined by x just before the active clock edge The state changes after a clock edge. Also Moore output only change just after the active clock edge. Printed; 8/3/5 Comment on Slide 4 Modified; March 8, 25 John Knight Sequential Circuits p. 27

Synchronous State Graph or Design of a Mealy or Sequence Detector, with Overlap. Step : Block diagram and waveforms x CLK X CLK or RST Z z - Step 2: State Graph Do sequence; temporarily forget Reset Wait for a x= x= x= R R Read Read Wait for Wait for Read Wait for x= R3 Read Wait for x= R4 Read Wait for Read Output x= R5 z= Printed; 8/3/5 Comment Slide 42 on Slide Modified; March 8, 25 John Knight Sequential Circuits p. 28 or machine The sequence There are two sequences to look for. We started by looking only for the sequence. Two pages later we will consider a machine to find the sequence. Then we will combine them as a product machine. a. Start by drawing the sequence of to capture the input. b. Then next page will add on what happens when the sequence is not this sequence. or machine Printed; 8/3/5 Comment on Slide 42 Modified; March 8, 25 John Knight Sequential Circuits p. 29

Synchronous State Graph or A Mealy or Sequence Detector with Overlap Step 2: State Graph Continued Complete the sequence x= Reset x= Read Read Output x= x= x= x= R3 x= R R R4 x= R5 z= Read Read Read Read x= x= x= x= x= x= Example: After we Read where next? Let x=. Tack the on the end Is the end part of the desired sequence? Yes, is the start of a new sequence and would have taken us to. Send the next state arrow to. Printed; 8/3/5 Slide 43 Modified; March 8, 25 John Knight Sequential Circuits p. 3 The sequence or machine There are two sequences to look for. We started by looking only for the sequence. On the next page we will add more states to find the sequence. Here we noted that with one input each state must have two exit arrows, one for a input and one for a input. Even if the input does not come as directly, one may be able to find the sequence later. Thus from each state, one has to check the previous input bits, and check for,,,, to see if one is part way through the desired sequence. There must be two arrows leaving each state. Fill in all these arrows. Printed; 8/3/5 Comment on Slide 43 Modified; March 8, 25 John Knight Sequential Circuits p. 3

Synchronous State Graph or A Mealy or Sequence Detector with Overlap Step 2: State Graph (Continued) Do the sequence alone; temporarily forget Draw in the arrows for the sequence we want Got Wait for Got Got Got Output x= x= x= G G z= x= Draw in the side arrows to give to arrows out of each state x= Got Got Wait for Got Got Output x= x= x= G G z= x= x= x= x= x= x= Printed; 8/3/5 Slide 44 Modified; March 8, 25 John Knight Sequential Circuits p. 32 or machine The Submachine We now have two machines, one two detect each sequence. The next step is to consider both machines operating at once. Printed; 8/3/5 Comment on Slide 44 Modified; March 8, 25 John Knight Sequential Circuits p. 33

Product State Graph Before Transitions Product State Graph Before Transitions are Added Possible States Not all are used R R z= G G G G R G R G R R G R G R R 2 G R 2 G R 2 R 3 G R 3 G R 3 R 4 G R 4 G R 4 R 5 z= G R 5 z= G R 5 z= z= G 2 G 3 z= G 2 R G 3 R z= G 2 R G 3 R z= z= z= z= z= z= Printed; 8/3/5 Slide 45 Modified; March 8, 25 John Knight Sequential Circuits p. 34 One Way to Combine the Graphs, the Product State Graph The combined graph will be done on the slides using a product graph. or machine Since there are two machines, one is always in one state say the G states) and the other is in another (say the R states). When both machines are considered together, this whole combine machine is in a combined state made from the two other states. Consider a machine four R states, which requires 2 flip flops to store the state. Also suppose the G machine has four states and it uses another two. The combined machine has 4 flip flops. Thus if the R machine is in state, and the G machine is in state, the combined machine would be in state (or if you wanted to order the flip flops differently). One can see the combined machine would have 4x4 = 8 states. Here the R machine has 7 states and the G machine has 5, so the product machine has 5x7 = 35 states. However they frequently are not all used. Printed; 8/3/5 Comment on Slide 45 Modified; March 8, 25 John Knight Sequential Circuits p. 35

Product State Graph; Main Transitions are Product State Graph; Main Transitions are Added Add the transitions for the desired sequences and R R z= G G z= G G G 2 G 3 z= R G R G R G 2 R G 3 R z= R G R G R G 2 R G 3 R z= R 2 G R 2 G R 2 z= R 3 G R 3 G R 3 z= R 4 G R 4 G R 4 z= R 5 z= G R 5 z= G R 5 z= z= z= Printed; 8/3/5 Slide 46 Modified; March 8, 25 John Knight Sequential Circuits p. 36 The Product State-Table or machine Having named the stages, and plotted them on an x-y grid, the next step is to add transitions. Start by adding the transitions that would happen if the machine received exactly the right sequence. First and then. Starting at A is received: Look at the green machine, and one sees a takes one to G. i.e. row 2. Look at the red machine, and one sees a takes one to R, i.e. column 2. Hence the next product state is GR in row 2 and column 2. Now let a be received. For the green machine, starting in state G, a takes one to state G For the red machine, starting in state R, a takes one to state R. Hence for the product machine, starting in state GR, a takes one to state GR. Continue adding the transitions (that s jargon for the arrows) for the sequence. Then repeat for the sequence starting from. The Product State-Table One could, instead of adding the transitions to the graph, make a state table directly. In this case it turns out to be more work. In some cases, particularly where the graph is large and messy, the state table is easier. Printed; 8/3/5 Comment on Slide 46 Modified; March 8, 25 John Knight Sequential Circuits p. 37

Product State Graph; Add the transitions Product State Graph; Add the transitions leaving states reached before. Each state has two exits R R z= G G G G R G R G R R G R G R R 2 G R 2 G R 2 R 3 G R 3 G R 3 R 4 G R 4 G R 4 R 5 z= G R 5 z= G R 5 z= z= G 2 G 3 z= G 2 R G 3 R z= G 2 R G 3 R z= z= z= z= z= z= Printed; 8/3/5 Slide 47 Modified; March 8, 25 John Knight Sequential Circuits p. 38 Transitions in the Product State Table Filling in Transitions not done before Transitions in the Product State Table Several of the states that were reached on the last slide, have only one, or perhaps zero, exit arrows. Each state needs two exit arrows, so fill those in now. Note that one state G now has an arrow going into it, whereas previously it did not. We will add the exit arrow from G on the next page. Printed; 8/3/5 Comment on Slide 47 Modified; March 8, 25 John Knight Sequential Circuits p. 39

Product State Graph; Add exits from all Product State Graph; Add exits from all states previously reached. Finish leads starting from G R 2 R R z= G G z= G G G 2 G 3 z= R G R G R G 2 R G 3 R z= R G R G R G 2 R G 3 R z= R 2 G R 2 G R 2 z= R 3 G R 3 G R 3 z= R 4 G R 4 G R 4 z= R 5 z= G R 5 z= G R 5 z= z= z= Printed; 8/3/5 Slide 48 Modified; March 8, 25 John Knight Sequential Circuits p. 4 The Product State Table Transitions in the Product State Table Starting at state G, add the exit arrows. Doing this reaches two new states R and R3. Add exit arrows for them. Doing that reaches the new state G. Add exit arrows for it too. Check that all the states that can be reached have two exit arrows. If so, check the arrows, and if there were no errors, the graph is complete. Printed; 8/3/5 Comment on Slide 48 Modified; March 8, 25 John Knight Sequential Circuits p. 4

A Moore or Sequence A Moore or Sequence Detector with Overlap The final state graph R R z= G G z= G R st G R st G 2 R st G 3 R st z= R G R G R G 2 R G 3 R z= R G R G R G 2 R G 3 R z= R 2 G R 2 G R 2 z= R 3 G R 3 G R 3 z= R 4 G R 4 G R 4 z= R 5 z= G R 5 z= G R 5 z= z= z= Printed; 8/3/5 Slide 49 Modified; March 8, 25 John Knight Sequential Circuits p. 42 The Final Product State Graph. Comments The Final Product State Graph. Here the final state graph has 2 states requiring 4 flip-flops If one had used two separate machines and ORed their outputs, this would have worked, but it would have required 3 flip flops for the five state machine, and 3 more for the seven state machine for a total of 6 flip-flops. Printed; 8/3/5 Comment on Slide 49 Modified; March 8, 25 John Knight Sequential Circuits p. 43