Number representation A number can be represented in binary in many ways. The most common number types to be represented are: Integers, positive integers one-complement, two-complement, sign-magnitude Decimal real numbers with a fixed range fixed-point Decimal real numbers floating-point
Integers Positive integers: 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 1 0 1 1 0 1 = 1 2 6 + 1 2 5 + 1 2 3 + 1 2 2 + 1 2 0 = 109 But how to represent negative numbers???
Sign-magnitude Integer: S 2 5 2 4 2 3 2 2 2 1 2 0 1 1 0 1 1 0 1 = - (1 2 5 + 1 2 3 + 1 2 2 + 1 2 0 ) = - 45 The magnitude of the number Sign-bit Drawback: 1 0 0 0 0 0 0 two representations 0 0 0 0 0 0 0 of zero (+/-) 0
1-complement The negative numbers are the complement of the positive numbers. Bit for bit in the positive number is inverted to get the corresponding negative. B=b N-1 b N-2...b 1 b 0 där b i {0,1} b N-1 b N-2... b 1 b 0 Sign Bit Drawbacks: Two zeroes (+/-) 0. At some additions adjusting is required.
2-complement Representation with 2-complement B=b N-1 b N-2...b 1 b 0 där b i {0,1} b N-1 b N-2... b 1 b 0 Sign Bit Decimalvalue: D(B)= - b N-1 2 N-1 +b N-2 2 N-2 +...+b 1 2 1 +b 0 2 0 This is the most common representation of signed integers.
2-complement Conversion example: B=b N-1 b N-2...b 1 b 0 där b i {0,1} 1 1 1 1 1 1 1 1 Sign Bit Decimalvalue: D(B)= - b N-1 2 N-1 +b N-2 2 N-2 +...+b 1 2 1 +b 0 2 0 = -128 + 127 = -1 It s alwais the biggest number that corresponds to -1.
Number conversion positive number to negative The Twocomplement methood 01111 +15 10000 invert 10001 add one 10001-15
Number conversion negative number to positive Twocomplement methood 10001-15 01110 invert 01111 add one 01111 +15 The same procedure in both directions!
2-complement 000 Computer registers are "rings". The figure shows a three-bit register. When you count with signed numbers the negative numbers, are the left half of the ring. 110 111-2 -1 0 001-3 3 101-4 011 100 1 2 010
2-complement fast conversion In order to easily produce 2's complement of a binary number, you can use the following procedure: Start fron the right side Copy all bits from the binary number that is 0 and the first bit that is 1. Invert Invert the rest of the bits. Copy Exemple: 2-complement from 110 is 010
Sign-extension In calculations the computers often need to increase the number of digits (bits) before any calculation - how do you do it with negative numbers? Integer: -2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 1 0 1 1 0 1 = -1 2 6 + 1 2 5 +1 2 3 + 1 2 2 + 1 2 0 = - 45 Sign bit has a negative weight -2 n-1 2 n-2 1 1 2 7 1 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 1 0 1 1 0 1 If you want to extend the number of digits you need to copy the sign bit to all extended bits!
Addition (BV: page 264) (+5) + (+2) (+7) 0101 + 0010 0111
Addition (BV: page 264) ignore (+5) + (-2) (+3) 1 1 0101 + 1110 1 0011 Carry-bit could be ignored!
Addition (BV: page 264) ignore (-5) + (-2) (-7) 1 11 1011 + 1110 1 1001 Carry-bit could be ignored!
Overflow Overflow the sign bit is not consistent with the input numbers (+5) + (+5) (-6) 1 1 0101 + 0101 1010
Overflow 2 ignore Overflow the sign bit is not consistent with the input numbers (-5) + (-5) (+6) 1 11 1011 + 1011 1 0110 Carry-bit could be ignored!
Subtraction (BV: page 265) Borrow one (+5) - (+2) (+3) 10 0101-0010???? How do you do the subtraction in an easy way?
Subtraction (BV: page 265) ignore (+5) - (+2) 0101-0010 1 1 0101 + 1110 (+3)???? 1 0011 Making an addition of 2's complement instead! Carry-bit could be ignored!
Subtraction (BV: page 265) ignore (-5) - (+2) 1011-0010 111 1011 + 1110 (-7)???? 1 1001 Carry-bit could be ignored!
Subtraction (BV: page 265) (+5) - (-2) (+7) 1011-1110???? 0101 + 0010 0111
Subtraction (BV: page 265) (-5) - (-2) (-3) 1011-1110???? 1 1011 + 0010 1101
2-complement summary Range: -2 N-1 up to 2 N-1-1 Negation: Invert every bit (the boolean complement), and add 1. Expansion of bit-length: Extend with bits at the left of the number with the same value as the sign bit. Overflow-rule: If two numbers with the same sign are added, it has become overflow if the result has the opposite sign. Subtraction rule: To subtract B from A, take the two complement of B and add to A.
Alternative way to detect overflow (BV: page 271) c 4 =0 c 3 =1 (+7) + (+2) (-7) 0 1 1 0111 + 0010 1001 Overflow because c 4 and c 3 are different!
Alternative way to detect overflow (BV: page 271) c 4 =0 c 3 =0 (-7) + (+2) (-5) 0 0 1001 + 0010 1011 Not Overflow because c 4 and c 3 are the same!
Alternative way to detect overflow (BV: page 271) ignore (+7) + (-2) (+5) c 4 =1 c 3 =1 1 1 1 0111 + 1110 1 0101 Not Overflow because c 4 and c 3 are the same! Carry-bit could be ignored!
Alternative way to detect overflow (BV: page 271) ignore (-7) + (-2) (+7) c 4 =1 c 3 =0 1 0 1001 + 1110 1 0111 Overflow because c 4 and c 3 are different! Carry-bit could be ignored!
Logic to detect overflow XOR For 4-bit-number Overflow if c 3 och c 4 are different Otherwise, it is not overflow Overflow = c 3 c 4 + c 3 c 4 = c 3 c 4 For n-bit-number Overflow = c n 1 c n
Quickie Question The number +5 is represented by 0101 if we use 4 bits. What number is equivalent to -5 if we use 8-bit two's complement representation? a: 1111 1011 b: 1111 1010 c: 1000 0101
Hardware for arithmetic
Half adder a b HA s c a b c s 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 a b 0 1 0 1 0 0 0 1 a b 0 1 0 1 0 1 1 0 c = a b s = a b a b s c
Full adder a b c in FA s c ut a b c in c ut s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 a b c in s c ut c in c in 0 1 ab 00 01 11 10 0 1 0 1 1 0 1 0 s = a b c in 00 01 11 10 0 0 0 1 0 1 0 1 1 1 c ut = a b + c in a + c in b
The sum function? c in 00 01 11 10 0 1 0 1 1 0 0 1 1 0 s = a b c in
c ab 0 1 0 1 1 0 Sum = Odd parity The Full Adder sum function is the "odd" parity function. This is the XOR function s natural extension to more variables than two. Odd parity is when the number of 1 s on the inputs is an odd number. Odd parity 00 01 11 10 0 1 1 0 b 0 1 a XOR 0 1 0 1 1 0 Odd parity a b a b c Odd parity
Carry function? 00 01 11 10 0 1 0 0 0 1 1 0 1 1 Majority function. Output assumes same value 1/0 as a majority of the inputs. M
Full-adder with two ½ -adders We may also construct a full-adder with two half-adders and an OR gate. a b c in FA s c ut a b c in HA HA s cut Decomposition means that you see the circuit as composed of building blocks. Such known building blocks could be used to build build entirely new systems, Composition.
a b c in c ut s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Full-adder ½+ ½ = 1 c in a b c in a b HA (a b) can be shared for both s and c ut! HA s cut s c ut c in c in ab a b 00 01 11 10 0 0 0 1 0 1 0 1 1 1 (a b) c in c ut = (a b) c in + a b ab 00 01 11 10 0 0 1 0 1 1 1 0 1 0 s = a b c in
Popular tattoo? Tattoos are forever! Unfortunately this is not the "best" adder, not if you want fast computers. Exciting continuation of adder circuits follow...
( Parityfunction Three-way light control) c in 0 1 00 01 11 10 0 1 0 1 1 0 1 0 Odd parity. s = a b c in
Three-way light control - revisited Brown/Vranesic: 2.8.1 Suppose that we need to be able to turn on / off the light from three different places. x 3 x 2 f Parityfunction x 1 x 2 x 3 Odd parity f x 1
XOR or NAND? x 1 x 2 x 3 Udda paritet f The former solution was based on NAND gates. XOR gates will be much more effective than NAND gates! x 1 x 2 x 3 f x x 2 x 3 1 00 01 11 10 f 0 1 0 1 1 0 0 1 1 0
Simpler with XOR gates With XOR-gates: x 1 x 2 x 3 f 7486 ( With NAND-gates: )
( Parity check ) With parity function we can check whether data has been disturbed or not. Disturbance! Data transmitted always have even parity! ALARM!? A bit modified!? Data has been disturbed! 0 1 P U P U? 1 0 1 0 0 1 0 1 0 0 1 1 1 0 1 1 1 0 Data - orginal Paritybit is added Parity Check Checks if an odd number of "1s is recived error!
More composition composition can be used to construct the n-bit adder One need n full-adders for constructing an n-bit adder?
Ripple-Carry Adder (RCA) a 1 b 1 a 0 b 0 c ut1 FA c in1 c ut0 FA c in0 s 1 s 0 + c ut1 c ut0 b 1 a 1 s 1 c in0 b 0 a 0 s 0
Ripple-Carry Adder (RCA) a n-1 b n-1 a 1 b 1 a 0 b 0 c utn-1 FA c inn-1 FA c in1 c ut0 FA c in0 s n-1 s 1 s 0 a n-1 b n-1... a 0 b 0 A FA area for a Fulladder t FA delay trough a Fulladder c utn-1 n-bit ADD s n-1... s 0 c in0 Timedelay from c in0 to c outn-1 is total of n t FA Total area is n A FA
Ripple-Carry Adder (RCA) a0 b0 c in0 s0 Critical path a1 b1 s1
Fulladder Carry-function & AND-OR A AND-OR = 20 MOS T AND-OR = 5T NAND & NAND-NAND & >1 & & & A NAND-NAND = 14 MOS T NAND-NAND = 3T NAND &
XOR with NAND & & & & a b b a b a ab ab b a b b a a b a b b a a = + = = + + + = = + ) ( ) ( ) ( ) ( Area: A XOR =16 MOS Delay: T XOR =3T NAND
Can we construct a faster adder? The delay of a ripple adder grows proportionally with the number of bits For 32 bits, the delay becomes very large
generate- och propagate- funktionerna p i = x i + y i p i = x Works also! The Carry-chain can be described by two functions: Generate g i ( carry-out c i+1 = 1 if g i = 1 ) Propagate p i ( carry-out c i+1 = 1 if c i = 1 and x i = 1 or y i = 1 ) i y i 0 0 g i = x i y i 1 c = g + i+1 i p i c i c i c i x i y i 0 c = 0 1 c i+ 1 x 00 01 11 10 0 1 i x i y i = y i x i 0 0 0 1 y i + c i 1 0 1 1 + c ( x i i x + 00 01 11 10 = x y 1 0 1 1 + c i + c y ( x i ) i y y i+ 1 i i i i i i )
Carry-look-ahead function Carry-bit c 0 g i = x i y i c 1 = g 0 + p 0 c 0 Carry-bit c 1 c 2 = g 1 + p 1 c 1 = g 1 + p 1 (g 0 + p 0 c 0 ) Propagate function from previous bits can be generated in parallel p i = x i + y i = g 1 + p 1 g 0 + p 1 p 0 c 0 Only two logic levels is needed
Carry-chain in ripple-adder #1 ½ + ½ c 0 OR or XOR can be used for the p function! p 0 g 0 p 1 g 1 #2 #3 #4 c1 c 2 #5 p 2 #6 g 2 6 gate levels c 3
Quicker implementation of the Carry-chain Distributive theorem: (a+b)c = ac+bc c 0 p 0 g 0 c 1 p 1 g 1 c 2 c 1 = g 0 +p 0 c 0 c 2 = g 1 +p 1 g 0 +p 1 p 0 c 0 Two- logic levels
(n=8) and two logic levels c 1 =g 0 +p 0 c 0 c 2 =g 1 +p 1 g 0 +p 1 p 0 c 0.... Fast, but cumbersome with so many inputs! c 8 =g 7 +p 7 g 6 +p 7 p 6 g 5 +p 7 p 6 p 5 g 4 +p 7 p 6 p 5 p 4 g 3 + + p 7 p 6 p 5 p 4 p 3 g 2 +p 7 p 6 p 5 p 4 p 3 p 2 g 1 + + p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 +p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0 Ooops!
Carry-lookahead adder (CLA) 8-bit adder c s s s s s s = a a a a a a + b 8 7 6 5 4 3 2s1s0 7 6 5 4 3 2a1a0 7 6 5 4 3 2b1b 0 b b b b b a 7 b 7 a 6 b 6 a 5 b 5 a 4 b 4 a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 1-bit Full Adder 1-bit Full Adder 1-bit Full Adder 1-bit Full Adder 1-bit Full Adder 1-bit Full Adder 1-bit Full Adder 1-bit Full Adder c 0 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 c 8 p 7 g 7 c 7 p 6 g 6 c 6 p 5 g 5 c 5 p 4 g 4 c 4 p 3 g 3 Carry look ahead unit c 3 p 2 g 2 c 2 p 1 g 1 c 1 p 0 g 0 P 0 G 0 c 8 =g 7 +p 7 g 6 +p 7 p 6 g 5 +p 7 p 6 p 5 g 4 +p 7 p 6 p 5 p 4 g 3 +p 7 p 6 p 5 p 4 p 3 g 2 +p 7 p 6 p 5 p 4 p 3 p 2 g 1 + + p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 + p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0
Hierarchical expansion (BV page 277) a 31-24 b 31-24 a 23-16 b 23-16 32-bit adder a 15-8 b 15-8 a 7-0 b 7-0 32-bit adder. Each block consists of a 8-bit CLA. Block 3 CLA Block 2 CLA Block 1 CLA Block 0 CLA G 3 P 3 S 31-24 G 2 P 2 S 23-16 G 1 P 1 S 15-8 G 0 P 0 S 7-0 c 8 c 0 First level four 8-bit adders with Carry lookahead c 32 P G P G 3 3 2 2PG 1 1P0 G0 c 0 c 24 P G 2 2PG 1 1P0 G0 c 16 c 0 PG P 1 1 0G0 c 0 P 0 G 0 c 0 Second level four Carry lookahead units
Hierarchical expansion C 8 = G 0 +P 0 c 0 C 16 = G 1 +P 1 G 0 +P 1 P 0 c 0 C 24 = G 2 +P 2 G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 c 0 C 32 = G 3 +P 3 G 2 +P 3 P 2 G 1 +P 3 P 2 P 1 G 0 +P 3 P 2 P 1 P 0 c 0 etc. More gates in sequential steps, but gates with fewer inputs can be used.
(Carry look ahead three level hierarchy) 16-bit LCU 64-bit adder 64-bit LCU
Carry-Select-Adder (CSA) Idea One divides an adder in two stages with the same number of bits To speed up the process so you calculate the results of the second step in advance for the two cases Carry-in = 0 Carry-in = 1 When the calculation of the carry bit is clear for the first step, then we choose the result of the second step depending on carry the bit value!
8-bit Carry-Select-Adder c 8-high b[7:4] a[7:4] a[3:0] b[3:0] 1 0 Add Add Add c 8-low c 0 a b a+b = s Mux c c 8 Mux c c 4 s[7:4] s[3:0] s
Ripple-Carry Adder Comparision T(n)= n*2.5*t NAND, A = n*12.5t NAND +T XOR T(4)= 14T NAND, A(4) = 50 A NAND Carry-Lookahead Adder (4bits) T(4)= ~8T NAND, A(4)= 43A NAND +4*4*A NAND = ~60A NAND Carry-Select Adder (8 bits) T(8)= ~(8+4)T NAND, A(8)= ~(120+20)A NAND
Which is the best adder? There is no clear answer! Ripple adder takes a minimum of space but is slow Carry-look-ahead adder take much space but it is fast Carry-select adder is a compromise One must make a trade-off between Area and speed
Subtraction Subtraction can be made by the addition of the two complement Invert all bits of the second operand and add one
Add/sub-unit y n 1 y 1 y 0 Add/Sub = 0: Addition Add/Sub = 1: Subtraction Add Sub control x n 1 x 1 x 0 c n n -bit adder c 0 s n 1 s 1 s 0
Arithmetic Logic Unit (ALU) Function selection f 0 f 1 AU LU A/L MUX f 0 f 1 A/L x ALU y c in Processors use to have an ALU, not only an adder. A/L f1 f0 Function 0 0 0 x+y 0 0 1 x+y+c in 0 1 0 x-y 0 1 1 x-y-c in 1 0 0 x or y 1 0 1 x and y 1 1 0 x xor y 1 1 1 inv x
Comparator Comparator is implemented as a subtractioncircuit???
Comparator Comparator is implemented as a subtractioncircuit
Summary Addition and subtraction of integers Two-complement Subtraction of a number is implemented as addition of it s two-complement Trade-Off: Area against Speed Different Adder-structures Ripple-Carry Adder (RCA) Carry-Lookahead Adder (CLA) Carry-Select Adder (CSA)