ELG 35 ELECTRONICS I SIXTH CHAPTER: DIGITAL CIRCUITS Session WINTER 003 Dr. M. YAGOUB
Sixh Chaper: Digial Circuis VI - _ This las chaper is devoed o digial circuis and paricularly o MOS digial inegraed circuis, by far he mos popular echnology for he implemenaion of digial sysems. A INTRODUCTION The concep of logic circuis refers o differen families depending on he used echnology and/or, srucure (Figure VI-). Digial inegraed circui echnologies and logic-circui families CMOS Bipolair BiCMOS AsGa Complemenary CMOS Pass-Transisor Logic TTL ECL Figure VI- Pseudo NMOS Dynamic Logic Each logic-circui family offers a unique se of advanages and disadvanages. A comparison beween he differen echnologies can highligh some poins: CMOS Technology: I is by a large margin he mos dominan of all he IC echnologies available for digial-circui design. Such circuis exhibi many advanages: - They dissipae much less power han bipolar logic circuis, and hus one can pack more CMOS circuis on a chip han is possible wih bipolar circuis. - They exhibi a high inpu impedance, which allow he designer o use charge sorage as a means for he emporary sorage of informaion in boh logic and memory circuis. - Their feaure size (ha is, MOS ransisor minimum channel lengh) has decreased dramaically over he years. This permis very igh circui packing and, correspondingly, very high levels of inegraion.
Sixh Chaper: Digial Circuis VI - 3 _ Bipolar Technology: Two logic-circui families based on he bipolar juncion ransisor are in use: TTL (Transisor-Transisor Logic) and ECL (Emier-Coupled Logic). TTL was for many years he mos widely used logic-circui family. Is decline was precipiaed by he adven of he VLSI ear. TTL manufacurers, however, fough back wih he inroducion of low-power and high-speed versions (e.g., uilizing Schoky diodes). ECL logic-circui family is based on he curren-swich implemenaion of he inverer we will sudy laer. Since ECL is he fases family, i is used in VLSI circui design when very high operaing speeds are required. BiCMOS Technology: This echnology combines he high operaing speeds possible wih BJTs (because of heir higher conducance) wih he low power dissipaion and oher excellen characerisics of CMOS. Like CMOS, BiCMOS allows for he implemenaion of boh analog and digial circuis on he same chip. AsGa Technology: Gallium arsenide devices exhibi a high carrier mobiliy which resuls in very speeds of operaion. B DIGITAL LOGIC INVERTER The logic inverer is he mos basic elemen in digial circui design. As is name implies, he logic inverer invers he logic value of he inpu signal (for a logic inpu, he oupu will be a logic «0» and vice versa). In erms of volage levels, a low inpu will generae a high oupu and vice versa. I Operaion Inverers are implemened using ransisors operaing as volage conrolled swiches (figure VI-). V C V C V C R R Faible v i R Fore v i Figure VI- R on v o v o v o v i V offse
Sixh Chaper: Digial Circuis VI - 4 _ In his Figure, when he inpu volage v i is low, he swich is open and v o V C. When v i is high, he swich will be closed and v o is almos zero. Since ransisor swiches are no perfec, he on swich has a finie closure resisance and an offse volage (V offse ). II Inverer volage ransfer characerisic To undersand he inverer behavior, le us consider he volage ransfer characerisic shown in Figure VI-3. V OH v o Figure VI-3 V OL NM L NM H V OL V IL V IH V OH v i For a low inpu v i, he oupu is high and equal o V OH. This value does no depend on he value of v i as long as v i does no exceed he value labeled V IL. This value is he maximum value ha v i can have while being inerpreed by he inverer as represening a logic «0». From his value, he inverer eners is amplifier region also called he ransiion region. On he oher hand, V IH is he minimum value ha v i can have while being inerpreed by he inverer as represening a logic. III Noise margins The insensiiviy of he inverer oupu o he exac value of v i wihin allowed regions is a grea advanage ha digial circuis have over analog circuis. In oher words, if some reason, a disurbing signal (called noise) is superimposed on he oupu of he driving inverer, he driven inverer would no be bohered so long as his noise does no decrease he volage a is inpu below V IH.
Sixh Chaper: Digial Circuis VI - 5 _ Thus, we can define a noise margin for high inpu, NM H of NM H V OH V IH () Similarly, a noise margin for low inpu can be defined as NM L V IL V OL () The four parameers, V OH, V OL, V IH and V IL define he volage ransfer characerisic (VTC) of an inverer and deermine is noise margins. Noe: In he case of an ideal VTC (Figure VI-4), a seep ransiion gives VC V IL VIH (3) V OL 0 (4) V OH V C (5) Thus VC NM L NM H (6) v o V OH V C Figure VI-4 V OL 0 V IL V IH V C / V C v i
Sixh Chaper: Digial Circuis VI - 6 _ III The BJT logic inverer The circui of a BJT logic inverer is shown in Figure VI-5. Figure VI-5 The operaion of he circui as a logic inverer makes use of he cuoff and sauraion modes. In fac, if he inpu volage is high, represening a logic, he ransisor will saurae. Thus, he oupu will be V CEsa (approximaely 0.V) represening a logic 0. Conversely, if he inpu volage is low, represening a logic 0, he ransisor will be cuoff. The collecor curren will be zero, and he oupu volage will be V CC, which represen a logic. Thus, he ransfer characerisic (VTC) is approximaed by hree sraigh-line segmens corresponding o he operaion of he BJT in he cuoff, acive and sauraion regions (figure VI-6). To illusrae his concep, le us consider he circui in figure VI-5 wih R B 0 kω R C kω β 50 V CC 5V
Sixh Chaper: Digial Circuis VI - 7 _ Figure VI-6 A v i V OL (low ampliude), we have v i VOL VCEsa 0.V (7) v o VOH VCC 5V (8) A v i V IL, he ransisor begins o urn on, hus v i V IL 0.7 V (9) For V IL < v i < V IH, he ransisor is in he acive mode. I operaes as an amplifier whose small-signal gain is A v v v o i RC β R + r B π (0) The gain depends on he value of r π, which in urn is deermined by he collecor curren and hence by he value of v i. As he curren hrough he ransisor increases, r π decreases and we can neglec r π relaive o R B.
Sixh Chaper: Digial Circuis VI - 8 _ Thus A v R β R C B 5 V/V () A v i V IH, he ransisor eners he sauraion region. Thus I B ( V V ) CC CEsa β / R C 0.096 ma () and V IH I B RB + VBE.66 V (3) A v i V OH (high ampliude), he ransisor will be deep ino sauraion v i V OH 5V (4) v o VOL VCEsa 0.V (5) Thus β ( VCC VCEsa ) ( V V )/ / R C forced OH BE RB. (6) The noise margins can now be compued NM H VOH VIH 5.66 3.34 V (7) NM L VIL VOL 0.7 0. 0.5 V (8) Obviously, he circui is no an ideal inverer. The volage gain in he ransiion region can be compued from he coordinaes of he breakpoins X and Y A v 5 0..66 0.7 5 V/V (9) which is equal o he approximae value found wih equaion ().
Sixh Chaper: Digial Circuis VI - 9 _ IV CMOS digial logic inverer The basic CMOS inverer is shown in Figure VI-7. Figure VI-7 I uilizes wo mached enhancemen-ype MOSFETs. One, Q N, wih an n channel and he oher, Qp, wih a p channel, is assimilaed o a load. As he body of each device is conneced o is source, we can use he simplified circui schemaic diagram shown in Figure VI-8. Figure VI-8
Sixh Chaper: Digial Circuis VI - 0 _ - Circui Operaion When he inpu is, v i V (Figure VI-9) and v GSN V and DSN vo v (0) Figure VI-9 corresponding o he curve in figure VI-0. Figure VI-0 Moreover, since v SGP < V, he load curve will be a horizonal sraigh line a almos zero curren level. This means ha he power dissipaion in he circui is very small.
Sixh Chaper: Digial Circuis VI - _ However, ha alhough Q N is operaing a nearly zero curren and zero drain-source volage, i provides a low resisance pah beween he oupu erminal and ground r DSN ' W kn L n ( V V ) n () Figure VI- shows he equivalen circui of he inverer when he inpu is high. Figure VI- When he inpu is «0», v i 0 V (Figure VI-) and vgsn 0 and v DSN V () Figure VI-
Sixh Chaper: Digial Circuis VI - _ In his case, he load curve is shown in Figure VI-3 wih v SGP V (high volage and small curren). Figure VI-3 Thus he power dissipaion in he circui of he inverer is very small in boh exreme cases. Q P provides a low-resisance pah beween he oupu erminal and he dc supply r DSP k ' p W L p ( V V ) p (3) The equivalen circui is shown in Figure VI-4. Figure VI-4
Sixh Chaper: Digial Circuis VI - 3 _ Noe : Wih he inpu high, Q N, wih is low oupu resisance can sink a relaively large load curren which can quickly discharge he load capaciance. Thus, i will pull he oupu volage down and hence is called «pull-down» device. Similarly, wih he inpu low, Q P can source a relaively large load curren which can quickly charge up a load capaciance, hus pulling he oupu volage up. Hence his ransisor is known as he «pull-up» device. Noe : The oupu volage levels are 0 and V, and hus he signal swing is he maximum possible. Noe 3: The low-resisance pahs ensure ha he inverer is less sensiive o he effecs of noise or oher disurbances. Noe 4: The inpu impedance of he inverer is infinie. Thus he inverer can drive an arbirarily large number of similar inverers wih no loss in signal level. - Volage ransfer characerisic The volage ransfer characerisic of he CMOS inverer can be obained by repeaing he graphical procedure for al inermediae values of v i. Thus, for Q N we have and ' W idn kn ( vi Vn ) vo vo for v o v i - V n (4) L n i DN ' W k ( ) n vi Vn for v o v i - V n (5) L n Similarly for Q P we have i DP k ' p W L p ( V v V )( V v ) ( V v ) i p o o and for v o v i + V p (6) i DP ( V v V ) ' W k p i p for v o v i + V p (7) L p
Sixh Chaper: Digial Circuis VI - 4 _ The inverer is usually designed o have V n V p (8) and ' W kn L n k ' p W L p (9) hus he inverer will have a symmeric ransfer characerisic (Figure VI-5) where he verical line is limied by V v + o ( B) V and vo ( C) V V (30) Figure VI-5 To deermine V IH and V OL we noe ha Q N is in he riode region and Q P in he sauraion region. Using he curren equaions (respecively (4) and (7)) we obain ( v V ) v v ( V v V ) i o o i (3)
Sixh Chaper: Digial Circuis VI - 5 _ Differeniaing boh sides relaive o v i resuls in o o ( v V ) + v v ( V v V ) i dv dv i o o dv dv i i (3) Wih v i V IH (33) and we have dv dv o i (34) v o V IH V (35) Subsiuing in equaion (3), we obain VIH 8 ( 5V V ) (36) Similarly, knowing ha V IH V V V IL (37) we have VIL 8 ( 3V + V ) (38) The noise margins can now be deermined as follows NM H VOH VIH V 8 8 ( 5V V ) ( 3V + V ) (39) and NM L VIL VOL 8 8 ( 3V + V ) 0 ( 3V + V ) (40)
Sixh Chaper: Digial Circuis VI - 6 _ As expeced, he symmery of he volage ransfer characerisic resuls in equal noise margins. 3- Dynamic operaion The speed of operaion of a digial sysem is deermined by he propagaion delay of he logic gaes used o consruc he sysem. The basic circui is shown in Figure VI-6. Figure VI-6 Wih an ideal pulse exciaion (Figure VI-7), he response shows rise and fall imes due o he charge and discharge of he capaciance. Figure VI-7 Since he wo imes are equal, we can wrie PLH CV ' W kn L n ( V V ) (4)
Sixh Chaper: Digial Circuis VI - 7 _ and PHL C ' W kn L n ( V V ) V V V + ln 3V 4V V (4) These poins are repored in he characerisic (Figure VI-8). Figure VI-8 C DYNAMIC OPERATION One of he applicaions of CMOS inverers is he one shown in Figure VI-9, where a firs inverer Q -Q drives a second inverer Q 3 -Q 4. The propagaion delay of he inverer Q -Q can be deermined using he circui in figure VI-6. We can show ha he oal capaciance of he load inverer Q 3 -Q 4 is equal o C + C (43) C gd + C gd + Cdb + Cdb + C g3 + C g 4 w which leads o he circuis in figures VI-0. Thus, PHL.6C ' W kn V L n (44) for a value of V 0. V.
Sixh Chaper: Digial Circuis VI - 8 _ Figure VI-9 Figure VI-0
Sixh Chaper: Digial Circuis VI - 9 _ An alernaive approximae expression for his ime PHL.7C ' W kn V L n (45) allows o obain a similar relaion for he second delay ime PLH k ' p.7c W V L p (46) The oal propagaion delay ime is hen P ( ) + PHL PLH (47) The dynamic power dissipaion is P f C D V (48) for an inpu signal of frequency f. C LOGIC GATES CIRCUITS I Single inpu gae From he inverer circui, i is possible o consruc differen logic circuis ha exhibi logic funcions. In fac, since he inverer consiss of an NMOS pull-down ransisor, and a PMOS pull-up ransisor, operaed by he inpu volage in a complemenary fashion, we have buil a CMOS logic gae ha consiss of wo neworks: he pull-down nework (PDN) consruced of NMOS ransisors, and he pull-up nework (PUN) consruced of PMOS ransisors.
Sixh Chaper: Digial Circuis VI - 0 _ - PDN Gaes The PDN conducs for all inpu combinaions ha require a low inpu. We can buil a NOR logic funcion Y A + B or Y A + B (49) shown in Figure VI-. In his configuraion, Q A will conduc when A is high (v A V ), and will hen pull he oupu node Y down o ground (v Y 0). Similarly, when Q B will conduc, Y is zero (v Y 0). Figure VI- The circui shown in Figure VI- is equivalen o he NAND funcion Y A B or Y A B (50) Figure VI-
Sixh Chaper: Digial Circuis VI - _ which will conduc only when A and B are boh high simulaneously. As a final example, he circui in Figure VI-3, gives Y A + BC or Y A + BC (5) Figure VI-3 - PUN Gaes Similarly, he circuis in Figures VI-4, VI-5 and VI-6 gives he following logic funcions : Y A + B (5) Y A B (53) Y A + BC (54)
Sixh Chaper: Digial Circuis VI - _ Figure VI-4 Figure VI-5 Figure VI-6
Sixh Chaper: Digial Circuis VI - 3 _ II Two-inpu circuis From he above examples, we can buil logic circuis ha have wo inpus. - Two-inpu NOR gae The circui in Figure VI-7 shows a wo-inpu NOR funcion Y A + B A B (55) Figure VI-7 - Two-inpu NAND gae The wo-inpu NAND funcion is described by (Figure VI-8) Y A B A + B (56)
Sixh Chaper: Digial Circuis VI - 4 _ Figure VI-8 III Exclusive-OR funcion Form he above funcions, i is possible o consruc he logic exclusive-or (Figure VI-9) : Y A B + A B (57) Using he Morgan s law, we can reforma his expression o Y A B + A B (58) The corresponding circui is shown in Figure VI-30. Once he gae synhesized, he significan sep remaining in he design is o decide on {W/L} raios for all devices. Le {W/L} p for a PMOS ransisor and {W/L} n for a NMOS ransisor. The purpose is o find he wors-case gae delay for a circui. This is done when he PDN will be able o provide a capacior discharge curren a leas equal o ha of an NMOS ransisor, and he when he PUN will be able o provide a capacior discharge curren a leas equal o ha of an PMOS ransisor. The derivaion of he equivalen {W/L} raio for he circui is based on he fac ha he on resisance is inversely proporional o {W/L}.
Sixh Chaper: Digial Circuis VI - 5 _ Figure VI-9 If a number of MOSFETs are conneced in series, he equivalen series resisance is equal o R series rds + rds +... (59) resuling in he following expression R series Consan / R ( W L) ( W L) series + Consan / Consan +... / + / +... Consan / ( W L) ( W L) ( W L) equivalen (60) Thus ( W / L) equivalen / / ( W L) ( W L) + +... (6) Similarly, a parallel connecion of ransisors resuls in an equivalen {W/L} of ( W L) ( W / L) + ( W / L)... / equivalen + (6)
Sixh Chaper: Digial Circuis VI - 6 _ Figure VI-30 From hese expressions, a logic circui can be buil. As an example of proper size, consider he fourinpu NOR gae shown in Figure VI-3 where he resuling equivalen {W/L} is equal o when conneced in series and 8 when conneced in parallel. This resul means ha we have o selec he {W/L} raion of each PMOS ransisor o be 4 imes ha of Q P of he basic inverer, ha is 4p. As anoher example, we show in Figure VI-3 he proper size for a four-inpu NAND gae. Noe: Because p is usually wo or hree imes n, he NOR gae will require much greaer area han he NAND gae. For his reason, NAND gaes are preferred for implemening combinaional logic funcions in CMOS. D PSEUDO-NMOS LOGIC CIRCUITS Despie is many advanages, CMOS suffers from increased area, and correspondingly, increased capaciance and delay, as he logic gaes become more complex. For his reason, digial inegraedcircui designers have been searching for forms of CMOS logic circuis ha can be used o supplemen he complemenary-ype circuis sudied above.
Sixh Chaper: Digial Circuis VI - 7 _ Figure VI-3 Figure VI-3 I Pseudo-NMOS inverer Figure VI-33 shows a modified form of he CMOS inverer. Here, only Q N is driven by he inpu volage while he gae of Q P is grounded, and Q P acs as an acive load for Q N. Each inpu mus be conneced o he gae of only one ransisor or, alernaively, only ONE addiional ransisor will be needed for each addiional gae inpu.
Sixh Chaper: Digial Circuis VI - 8 _ Figure VI-33 Since we have a driver ransisor and a load ransisor, his kind of circui is called a pseudo-nmos inverer. For comparison purposes, we shall briefly menion he wo older forms of NMOS logic. The earlies form uilized an enhancemen MOSFET for he load elemen. Such circuis suffer from a relaively small logic swing, small noise margins, and high saic power dissipaion. This echnology was replaced wih depleion-load NMOS circuis. I was iniially expeced ha he depleion NMOS wih V GS 0 would operae as a consan-curren source and would hus provide an excellen load elemen. However, he body effec in he depleion ransisor causes is i-v characerisic o deviae considerably from ha a consan-curren source. Alhough depleion-load NMOS has been virually replaced by CMOS, one can sill see some depleion-load circuis in specialized applicaions. The pseudo-nmos inverer we are abou o sudy is similar o depleion-laod NMOS bu has he advanage of being direcly compaible wih complemenary CMOS circuis. Is saic characerisics are given by Transisor N : - Sauraion region (v i V v o ) : i DN k n ( v V ) i (63)
Sixh Chaper: Digial Circuis VI - 9 _ - Triode region (v i V v o ) : i DN k n ( v V ) v v i o o (64) Transisor P : - Sauraion region (v o V ) : i DP k p ( V V ) (65) - Triode region (v o V ) : i DP k p ( V V )( V v ) ( V v ) o o (66) wih k n W k ' n and L n k p W k ' p (67) L p To obain he volage ransfer characerisic, we superimpose he load curve on he i-v characerisics of Q N (Figure VI-34). Figure VI-34
Sixh Chaper: Digial Circuis VI - 30 _ In his characerisic, we show he Q N curves for only he wo exreme values of v I, namely, 0 and V. We observe ha - The load curve represens a much lower sauraion curren han is represened by he corresponding curve for Q N (ha for v I V ). This is a resul of he fac ha he pseudo- NMOS inverer is usually designed so ha k n is greaer han k p by a facor of 4 o 0. Since he raio r k k n p (68) deermines all he breakpoins of he VTC, i.e., V IH, V IL,, and hus deermines he noise margins. Selecion of a relaively high value for r reduces V OL and widens he noise margins. - Q P operaes in sauraion for only a small range of v o (v o V ), For he remainder, i operaes in he riode region. When v I is zero, Q N is cu off and Q P is in he riode region, hough wih zero curren Poin A (Figure VI-35) v o V V OH. No saic power dissipaion. When v I is equal o V Poin E (Figure VI-35) v o V OL (he circui is no symmeric, which is an obvious disadvanage). The saic power dissipaion exiss wih P I * V (69) D sa
Sixh Chaper: Digial Circuis VI - 3 _ Figure VI-35 The inverer characerisic is divided ino four disinc regions lised in he following able: Region Segmen Q N Q P Condiion I AB Cu off Triode v I < V II BC Sauraion Triode v I - V v o III CD Triode Triode V v o v I - V IV DE Triode Sauraion v o V
Sixh Chaper: Digial Circuis VI - 3 _ This curve was ploed for V n p 5 V, r 9 and V V V Region I (segmen AB) : v o is consan v o V OH V (70) Region II (segmen BC) : Using equaions (64) and (67) wih he raio r defined by equaion (68), we obain v o V + ( V V ) r ( v V ) I (7) The value of V IL can be obained by differeniaing his equaion and subsiuing v v o I and v V (7) I IL as V IL V + V r V ( r +) (73) The hreshold volage V M is by definiion he value of v I for which v o v I, V M V V + V r + (74) Finally, he end of he region II, poin C, can be found by subsiuing he value of v o (v o v I - V ) in equaion (7). Region III (segmen CD) : This shor segmen has no grea ineres. Poin D is characerized by v o V.
Sixh Chaper: Digial Circuis VI - 33 _ Region IV (segmen DE) : Using equaions (65) and (66) gives v o ( v V ) ( v V ) ( V V ) I I r (75) The value of V IH can be found by differeniaing his equaion and seing he derivaive equal o - : V IH V ( V V ) + 3r (76) The value of V OL can be obained by subsiuing v I V in equaion (75) v OL ( V V ) (77) r The saic curren I sa conduced by he inverer in he low-oupu sae is found from equaion (65) I sa k p ( V V ) (78) Finally, NM L and NM H are deermined as follow: NM L : use equaions (73) and (77) NM L V ( V V ) r r ( r + ) (79) NM H : use equaions (70) and (76) : NM H ( V V ) (80) 3r When he inverer is loaded by a capaciance C, he imes are obained by PLH.7C k V p (8)
Sixh Chaper: Digial Circuis VI - 34 _ where we assume ha {V 0. V } for v o value over he range 0 o 0.V, and PHL k n.7c 0.46 V r (8) Noe : The raio r deermines all he breakpoins. The larger he value of r, he lower V OL is and he wider he noise margins are. However, a larger r increases he asymmery in he dynamic response and, makes he gae larger. Usually, r is seleced in he range 4 o 0. As an example, we show in Figure VI-36 a NOR gae and in Figure VI-37 a NAND gae wih pseudo-nmos ransisors. Figure VI-36
Sixh Chaper: Digial Circuis VI - 35 _ Figure VI-37 E PASS-TRANSISTOR LOGIC CIRCUITS A concepually simple approach for implemening logic funcions uilizes series and parallel combinaions of swiches ha are conrolled by inpu logic variables o connec he inpu and oupu nodes (Figure VI-38). For series connecions, he realized funcion is Y ABC (83) A B C Y Figure VI-38
Sixh Chaper: Digial Circuis VI - 36 _ For parallel connecions (Figure VI-39), he realized funcion is ( B C) Y A + (84) B A C Y Figure VI-39 Because his form of logic uilizes MOS ransisors in he series pah from inpu o oupu, o pass or block signal ransmission, i is known as pass-ransisor logic (PTL). As menioned, CMOS ransmission gaes is also employed o implemen he swiches. Two possible implemenaions of a swich are he one wih single NMOS ransisor (Figure VI-40) and wih CMOS ransmission gae (Figure VI-4). Figure VI-40 Figure VI-4
Sixh Chaper: Digial Circuis VI - 37 _ A basic design requiremen of PTL circuis is ha every node mus have a all imes a low-resisance pah o eiher ground or V. To appreciae his poin, le us consider he circui shown in Figure VI-4. Figure VI-4 In his circui, he swich S is used o form he AND funcion of is conrolling variable B and he variable A available a he oupu of a MOS inverer. The oupu of he PTL circui is shown conneced o he inpu of anoher inverer. If S is closed, B is high and he oupu Y is equal o A. Node Y will hen be conneced eiher o V (hrough Q if A is high) or o ground (hrough Q if A is low). If S is open, B is low and he node Y will now become a high-impedance node. If iniially v Y was zero, i will remain so. However, if iniially v Y was high a V, his volage will be mainained by he charge on he parasiic capaciance C bu for only a ime. Thus he capaciance will be discharged and v Y diminish correspondingly. In any case, he circui can no longer be considered a saic logic circui. The problem is solved by esablishing for node Y a low-resisance pah ha is acivaed when B goes low as shown in Figure VI-43. Here anoher swich S closes when B goes low and esablishes a lowresisance pah beween Y and ground. We have a low-resisance pah beween Y and ground.
Sixh Chaper: Digial Circuis VI - 38 _ Figure VI-43 I Operaion wih NMOS ransisors as swiches Implemening he swiches in a PTL circui wih single NMOS ransisors resuls in a simple circui wih small area and small node capaciances. To illusrae, consider he circui shown in Figure VI-44, where an NMOS ransisor Q is used o implemen a swich connecing an inpu node and an oupu node. When he swich is closed (v c is high), a 0, he oupu volage v o is iniially zero and he capaciance is fully discharged. When v I is high, he ransisor operaes in he sauraion mode and delivers a curren i D o charge C i D W k ( V v V ) k ( V v V ) ' n o L n n o (85) Figure VI-44
Sixh Chaper: Digial Circuis VI - 39 _ V is deermined by he body effec (using equaion (6) of chaper V) since he source is a a volage v o relaive o he body V V o ( v φ φ ) + γ o f f (86) where φ f is a physical parameer (φ f 0.6V) and V o is he hreshold volage for V SB 0. γ is a parameer relaed o he fabricaion process. Thus iniially, a 0, V is equal o V o and he curren i D is relaively large. However, as C charges up and v o rises, V increases and i D decreases (equaion (85)). I follows ha he process of charging he capacior will be relaively slow. The curren reduces o zero when {v o V D - V }. Thus V OH < V We refer o a «poor». This effec can cause Q P of he load inverer o conduc. The inverer will have a finie saic curren and saic power dissipaion. Moreover, he propagaion delay PLH can be deermined for v o V /. When v I is low (Figure VI-45), he ransisor is in sauraion and i D W k ( V V ) k ( V V ) ' n L n n (87) Figure VI-45 As C discharges, he ransisor eners he riode region {v o V D - V }. Thus V OL 0: The NMOS provides a «good 0». Again, he delay PHL is deermined for v o V /.
Sixh Chaper: Digial Circuis VI - 40 _ II Use of CMOS ransmission gaes as swiches We use he ransmission gae as a swich. When v I is high (Figure VI-46), i.e., when he swich is in he «on» posiion, we assume ha a 0 he oupu is zero. Q N will be operaing in sauraion and providing a charging curren i DN W k ( V v V ) k ( V v V ) ' n o n L n n o n (88) where V n V o ( v φ φ ) + γ o f f (89) Figure VI-46 Q N will conduc a diminishing curren ha reduces o zero a v o V V n (90) However, ha Q P operaes wih V SG V and is iniially in sauraion i DP k ' p W L p ( ) V V k ( V V ) p p p (9) Since he subsrae of Q P is conneced o V, V p remains consan a he value V o (assumed o be he same value as for he n-channel device). The oal capacior charging curren is he sum of i DN and i DP.
Sixh Chaper: Digial Circuis VI - 4 _ When Q P will ener he riode region a {v o V p }, i will coninue o conduc unil C is fully charged and {v o V OH V }. Thus, he p-channel device will provide he gae wih a «good». When v I goes low (Figure VI-47), Q N and Q P inerchange roles. Q P will cease conducion when v o falls o V p given by V p V o ( V v + φ φ ) + γ o f f (9) However, Q N will coninue o conduc unil C is fully discharged and {v o V OL 0}. Thus providing a «good 0». Transmission gaes provide far superior performance. Figure VI-47 III Pass-ransisor logic circui examples Figure VI-48 shows a PTL realizaion of a wo-o-one muliplexer. Based on he logic value of C, eiher A or B is conneced o he oupu Y, we obain he Boolean funcion Y CA + CB (93) Anoher example is an efficien realizaion of he exclusive-or (XOR) funcion. The circui, shown in Figure VI-49, uilizes four ransisors in he ransmission gaes and anoher four for he wo inverers needed o generae he complemens A and B, for a oal of eigh ransisors.
Sixh Chaper: Digial Circuis VI - 4 _ Figure VI-48 Figure VI-49 This should be compared o he welve ransisors needed in he realizaion wih complemenary CMOS o have he same funcion Y A B + A B (94)
Sixh Chaper: Digial Circuis VI - 43 _ A las example is he circui shown in Figure VI-50 ha uses NMOS swiches wih low or zero hreshold. Boh he inpu variables and heir complemens are employed and ha he circui generaes boh he Boolean funcion and is complemen. Thus his circui is known as CPL (Complemenary Pass-ransisor Logic). The circui consiss of wo idenical neworks of pass ransisors wih he corresponding ransisor gaes conrolled by he same signal (B and B ). The inpus of he PTL are complemened: A and B for he firs nework, and A and B for he second nework. The circui shown realizes boh he AND and NAND funcions. Figure VI-50 F DYNAMIC LOGIC CIRCUITS The logic circuis we have sudied hus far are of he saic ype. In a saic logic circui, every node has all imes a low-resisance pah o V or ground. Saic circuis do no need clocks (i.e., periodic iming signals) for heir operaion alhough clocks may be presen for oher purposes. In conras, he dynamic logic circuis rely on he sorage of signal volages on parasiic capaciances a cerain circui nodes. Since charge will leak wih ime, he circuis need o be periodically refreshed, and hus he presence of a clock wih a cerain specified minimum frequency is essenial. To place dynamic logic-circui echniques ino perspecive, we have o recall ha : - Complemenary CMOS excels in nearly every performance caegory: i is easy o design, has he maximum possible logic swing, is robus from a noise-immuniy sandpoin, dissipaes no saic power, and can be designed o provide equal low-o-high and high-o-low propagaion delays.
Sixh Chaper: Digial Circuis VI - 44 _ Is main disadvanage is he requiremen of wo ransisors for each addiional gae inpu, which increases he oal capaciance and correspondingly he propagaion delay and he dynamic power dissipaion. - Pseudo-NMOS reduces he number of required ransisors a he expense of saic power dissipaion. - Pass-ransisor logic can resul in simple, small area circuis bu is limied o special applicaions and requires he use of complemenary inverers o resore signal levels, especially when he swiches are simple NMOS ransisors. The dynamic logic echniques sudied in he nex secion mainain he low device coun of pseudo- NMOS while reducing he saic power dissipaion o zero. Bu his will be achieved a he expense of more complex and less robus design. I Basic principles Figure VI-5 shows he basic dynamic logic gae. I consiss of a pull-down nework (PDN) ha realizes he logic funcion in exacly he same way as he PDN of a complemenary CMOS gae or a pseudo-nmos gae. However, we have here wo swiches in series ha are periodically operaed by he clock signal φ whose waveform is shown in Figure VI-5. When φ is low, Q P is urned on and he circui is said o be in he seup or precharge phase. Q P charges capaciance C L so ha a he end of he precharge inerval he volage a Y is equal o V. Also, he inpus A, B and C are allowed o change and sele o heir proper values. Observe ha because Q E is off, no pah o ground exiss. When φ is high, Q p is off and Q E urns on, and he circui is in he evaluaion phase. Now, if he inpu combinaion is one ha corresponds o a high oupu, he PDN does no conduc and he oupu remains high a V. Thus {V OH V }. Observe ha no low-o-high propagaion delay is required, hus { PLH 0}. On he oher hand, if he combinaion of inpus is one ha corresponds o a low oupu, he appropriae NMOS ransisors in he PDN will conduc and esablish a pah beween he oupu node and ground hrough he on ransisor Q E. Thus C L will be discharged hrough he PDN, and he volage a he oupu node will reduce o V OL 0.
Sixh Chaper: Digial Circuis VI - 45 _ Figure VI-5 Figure VI-5 The high-o-low propagaion delay PHL can be calculaed in exacly he same way as for a complemenary CMOS circui expec ha here we have an addiional ransisor in he series pah o ground. As an example, we show in Figure VI-53 he circui ha realizes he funcion Y A + BC (95)
Sixh Chaper: Digial Circuis VI - 46 _ Figure VI-53 II Non ideal effecs Noise margins Various sources of non ideal operaion of dynamic logic circuis have o be considered. Since during he evaluaion phase he NMOS ransisors begin o conduc for {v I V n }, V IL V IH V n (96) Thus and NM L V n (97) NM H V V n (98) The noise margins are far from equal. Oupu volage decay In he absence of a pah o ground hrough he PDN, he oupu volage will ideally remain high a V. This, however, is based on he assumpion ha he charge on C L will remain inac. In pracice, here will be leakage curren ha will cause C L o slowly discharge and v Y o decay.
Sixh Chaper: Digial Circuis VI - 47 _ Thus he circui can malfuncion if he clock is operaing a a very low frequency and he oupu node is no refreshed periodically. 3 Charge sharing There is anoher and ofen more serious way for C L o lose some of is charge and hus cause v Y o fall significanly below V. To see how his can happen, refer o Figure VI-54 which shows only he wo op ransisors Q and Q of he PDN ogeher wih he precharge ransisor Q P. Figure VI-54 Here, C is he capaciance beween he common node of Q and Q and ground. The figure shows he siuaion a he beginning of he evaluaion phase afer Q p has urned off and wih C L charged o V. In his paricular siuaion, we assume ha C is iniially discharged and ha he inpus are such ha a he gae of Q we have a high signal, whereas a he gae of Q he signal is low. We can see ha Q will urn on, and is drain curren i D will flow as indicaed. Thus his curren will discharge C L and charge C. Alhough evenually his curren will reduce o zero, C L will have los some of is charge, which will be ransferred o C. This is he charge sharing phenomenon. In order o minimize his effec, one approach involves adding a p-channel device ha coninuously conducs a small curren o replenish he charge los by C L (Figure VI-55).
Sixh Chaper: Digial Circuis VI - 48 _ Figure VI-55 4 Cascading dynamic logic gaes Consider he circui in Figure VI-56 where wo single inpu dynamic gaes are conneced in cascade. During he precharge phase, C L and C L will be charged hrough Q P and Q P, respecively. Thus, a he end of he precharge phase, and v Y V (99) v Y V (00)
Sixh Chaper: Digial Circuis VI - 49 _ Figure VI-56 In he evaluaion phase, if A is high, he oupu Y should be low (v Y 0) and Y high (v Y V ). However, as he evaluaion phase begins, Q urns on and C L begins o discharge. Bu, simulaneously, Q urns on and C L also begins o discharge. Only when v Y drops below V n will Q urn off. Unforunaely, by ha ime, C L will have lis a significan amoun of is charge, and v Y will be less han he expeced value of V. This problem make simple cascading an impracical proposiion. In his case, Domino CMOS logic circuis have overcome his limiaion. 5 Domino CMOS logic circuis Domino CMOS logic circuis are a form of dynamic logic circuis ha resuls in cascadable gaes. Figure VI-57 shows he srucure of he Domino CMOS logic gae which is simply he basic dynamic logic gae of Figure VI-5 wih a saic CMOS inverer. During precharge, X will be raised o V, and he gae oupu Y will be a 0V. During evaluaion, depending on he combinaion of inpu variable, eiher X will remain high and hus he oupu Y will remain low, or X will be brough down o 0V and he oupu Y will rise o V. To see why Domino CMOS gaes can be cascaded, consider he siuaion in Figure VI-58.
Sixh Chaper: Digial Circuis VI - 50 _ Figure VI-57 Figure VI-58 In his circui, a he end of he precharge, X and X will be a V and Y and Y will be a 0V. As in he previous case, if A is high a he beginning of he evaluaion, hus, as φ goes up, capacior C L will begin discharging, pulling X down. Meanwhile, he low inpu a he gae of Q keeps he ransisor off, and C L remains fully charged. When v X falls below he hreshold volage of inverer I, Y will go up urning Q on, which in urn begins o discharge C L and pulls X low (evenually, Y rises o V ). Then, we see ha because he oupu of he domino gae is low a he beginning of evaluaion, no premaure capacior discharge will occur. As indicaed in Figure VI-59, oupu Y will make a 0-o-
Sixh Chaper: Digial Circuis VI - 5 _ ransiion PLH seconds afer he rising edge of he clock. Subsequenly, oupu Y makes a 0-o- ransiion afer anoher PLH inerval. The propagaion resembles dominoes falling over in a cascade manner, which is he origin of he name DOMINO CMOS logic. Figure VI-59 G LATCHES The logic circuis considered hus far are called combinaional (or combinaorial). Their oupu depends only on he presen value of he inpu. Thus, hese circuis do no have memory. Memory is a very imporan par of digial sysems. Is availabiliy in digial compuers allows for soring programs and daa. Furhermore, i is imporan for emporary sorage of he oupu produced by a combinaional circui for use a a laer ime in he operaion of a digial sysem. Logic circuis ha incorporae memory are called sequenial circuis. Tha is, heir oupu depends no only on he presen value of he inpu bu also on he inpu s previous values. Such circuis require a iming generaor (a clock) for heir operaion. There is basically wo approaches for providing memory o a digial circui. The firs relies on he applicaion of posiive feedback ha can be arranged o provide a circui wih wo sable saes: he bisable circui which can be used o sore one bi of informaion. One sable sae would correspond o a sored 0, and he oher o a sored. A bisable circui can remain in eiher sae indefiniely and hus belongs o he caegory of saic sequenial circuis. The oher approach o realizing memory uilizes he sorage of charge on a capacior. When he capacior is charged, i would be regarded as soring a ; when i is discharged, i would be soring a 0. Since he ineviable leakage effecs will cause he capacior o discharge, such a form of memory requires he periodic recharging of he capacior, a process known as refresh. Thus, memory based on charge sorage is known as dynamic memory and he corresponding sequenial circuis as dynamic sequenial circuis.
Sixh Chaper: Digial Circuis VI - 5 _ In his secion, we shall sudy he basic memory elemen, he lach. I Lach The basic memory elemen, he lach, is shown in Figure VI-60. Figure VI-60 I consiss of wo cross-coupled logic inverers ha form a posiive-feedback loop. To invesigae he operaion of he lach we break he feedback loop a he inpu of one of he inverers (Figure VI-6). Figure VI-6 Assuming ha he inpu of G is large, breaking he feedback loop will no change he loop volage ransfer characerisic, which can be deermined by ploing v Z -v W (Figure VI-6). This VTC consiss of hree segmens, wih he middle segmen corresponding o he ransiion region of he inverers. The sraigh line {v Z v W } is realized by reconnecing Z o W o close he feedback loop. Here, he poins A and C are sable operaing poins while he poin B is unsable. The lach canno operae a B for any period of ime. The reason poin B is unsable can be seen by considering he circui in Figure VI-59 and aking accoun of he inerference or noise ha is ineviably presen in any real circui.
Sixh Chaper: Digial Circuis VI - 53 _ Figure VI-6 Le he volage v W increase by a small incremen v w. The volage a poin X will increase significanly (produc v w *G, where G is he incremenal gain) The resuling signal will rise o an even larger signal a node Z {v w *G *G }. Since his poin is relaed o he inpu, he regeneraive process coninues, shifing he operaing poin from B upward o poin C (If we assume a negaive volage incremen he operaing poin will move downward from B o A). A poin C, v W is high, v X is low, v Y is low, and v Z is high. The reverse is rue a poin A. Thus, we see ha in one of he sable saes (e.g., ha corresponding o poin A), a high v W gives a low oupu v Z and in he oher sae (poin C), a low inpu v W implies a high oupu. We have wo sable saes and hus he lach is a bisable circui having wo complemenary oupus. Moreover, he lach operaes depends on he exernal exciaion. I memorizes his exernal acion by saying indefiniely in he acquired sae. II Flip-Flop I now remains o devise a mechanism by which he lach can be riggered o change sae. The lach ogeher wih he riggering circuiry forms a flip-flop. The simples ype of flip-flop ids he se/rese (SR) flip-flop shown in Figure VI-63. I is formed by cross-coupling wo NOR gaes, and hus i incorporaes a lach. The second inpu of each NOR gae ogeher serve as he rigger inpus of he flipflop. These wo inpus are labeled S (for se) and R (for Rese). The oupu are labeled Q and Q emphasizing he fac ha hese are complemenary. The flip-flop is considered se (ha is soring a logic ) when Q is high and Q is low.
Sixh Chaper: Digial Circuis VI - 54 _ When he flip-flop is in he oher sae (Q low, Q high), i is considered rese (soring a logic 0). Figure VI-63 In he case of logic 0, Q will be low and hus boh inpus o he NOR gae G will be low. To se he flip0-flop we raise S o he logic- level while leaving R a 0. The a he S erminal will force he oupu of G o «0». Thus he wo inpus o G will be «0» and is oupu Q will go o. The operaion of he flip-flop is summarized by he following ruh able III CMOS implemenaion of SR flip-flops The SR flip-flop can be implemened in CMOS by replacing each of he NOR gaes by is CMOS circui realizaion. Specifically, Figure VI-64 shows a clocked version of an SR flip-flop. This circui works perfecly, bu i is relaively complex. A simpler circui can be found by using pass-ransisors o implemen he clock circui. This circui is called he daa or D flip-flop (Figure VI-65).
Sixh Chaper: Digial Circuis VI - 55 _ Figure VI-64 Figure VI-65 IV D Flip-Flop Figure VI-66 shows a D flip-flop circui. I has wo inpus, he daa inpu D and he clock inpu φ and wo oupus (Q and is complemenary). When he clock is low, he flip-flop is in he memory, or res, sae. As he clock goes high, he flip-flop acquires he logic level ha exied on he D line jus before he riding edge of he clock. Such a flip-flop is said o be edge-riggered.
Sixh Chaper: Digial Circuis VI - 56 _ A simple implemenaion is shown in Figure VI-67. I consiss of wo inverers for he wo complemenary phases of he clock (Figure VI-68). Figure VI-66 Figure VI-67 Figure VI-68 When φ is high, he loop is opened, and D is conneced o he inpu of inverer G. The capaciance a he inpu node of he inverer is charged o he value of D, and he capaciance a he inpu node of G is charged o he value of D.
Sixh Chaper: Digial Circuis VI - 57 _ Then, when he clock goes low, he inpu line is isolaed from he flip-flop, he feedback loop is closed, and he lach acquires he sae corresponding o he value of D jus before he clock wen down, providing an oupu Q D. However, he proper operaion of his circui is based on he assumpion ha φ and φ mus no be simulaneously high a any ime. To solve his problem, we use he maser-slave configuraion (Figure VI-69) ha gives he clock waveforms shown in Figure VI-70 where here is non overlapping. Figure VI-69 Figure VI-70