ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design Space Exploration " Design Problem Example: Match Circuit 3 Total Power! P tot = P static + P sc + P dyn! P sw = P dyn + P sc = a(c load V 2 f) + C sc V 2 f Energy and Power Optimization! P tot a(c load V 2 f) + C sc V 2 f + VI s (W/L)e-Vt/(nkT/q)! Let a = activity factor a = average #tran 0#1 /clock 4 Worksheet Problem 1 Power Sources Review: P tot = P static + P dyn + P sc V in I static I dynamic I sc 0V 140mV 400mV 500mV 600mV 860mV 1V 7 1
Worksheet Problem 1 Energy and Power Optimization V in I static I dynamic I sc 0V 180pA 126uA 140mV 6nA 100uA 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA 860mV 6nA 100uA 1V 180pA 126uA 8 Reminder: Worksheet Problem 1 Reduce V dd (Worksheet #2)! V dd =520mV, V thn = V thp =300mV V in I static I dynamic I sc 0V 180pA 126uA 140mV 6nA 100uA 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA 860mV 6nA 100uA V in I static I dynamic I sc 0V 140mV 260mV 360mV 500mV 1V 180pA 126uA 10 11 Reduce V dd (Worksheet #2)! V dd =520mV, V thn = V thp =300mV Design Tradeoffs V in I static I dynamic I sc 0V 180pA 396uA 140mV 6nA 144uA 260mV 111nA 360mV 6nA 108uA 500mV 180pA 36uA 12 2
Reduce V dd! What happens as reduce V dd? " Energy? " Static " Switching " Delay? Reduce V dd :! τ gd =/I=(CV)/I! I d =(µc OX /2)(W/L)(V gs -V TH ) 2! τ gd impact?! τ gd 1 V 14 15 Reduce V dd : Reduce V dd (Worksheet #3)! τ gd =/I=(CV)/I! I d =(µc OX /2)(W/L)(V gs -V TH ) 2! τ gd impact?! V thn = V thp =300mV, V in =V dd, estimate Eτ V dd I ds τ/(τ@v dd =1) E switch / (E switch @V dd =1) Eτ 1V! τ gd 1 V! Ignoring leakage: E V 2 Eτ 2 Const 700mV 500mV 350mV 260mV 16 17 Reduce V dd (Worksheet #3) Reduce Short-Circuit Power?! V thn = V thp =300mV, V in =V dd, estimate Eτ! P sc = ac sc V 2 f V dd I ds τ/(τ@v dd =1) E switch / (E switch @V dd =1) Eτ 1V 126uA 1 1 1 700mV 72uA 1225 049 6 500mV 36uA 175 025 437 350mV 9uA 49 012 588 260mV 111nA 295 007 206 # # E = V dd I peak t sc % 1& & % (( $ $ 2' ' Vin Vdd Vdd-Vthp Vthn time Vdd Isc Vout tsc tsc time 18 19 3
Increase V th (Worksheet #4) Increase V th (Worksheet #4)! What is impact of increasing threshold on! What is impact of increasing threshold on " Delay? " Delay? " Leakage? " Leakage?! V dd =1V, V in =V dd! V dd =1V, V in =V dd V thn = -V thp I ds τ/(τ@v th =300mV) I static (I stat @V th =300mV) I stat / V thn = -V thp I ds τ/(τ@v th =300mV) I static (I stat @V th =300mV) I stat / 300mV 300mV 126uA 1 180pA 1 460mV 460mV 97uA 13 36pA 002 600mV 600mV 72uA 175 108fA 00006 20 21 Idea! Tradeoff " Speed Design Space Exploration " Switching energy " Leakage energy! Energy-Delay tradeoff: Eτ 2 22 23 Design Problem Idea: Design Space Explore! Function: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! Assumptions: Match case uncommon! Identify options " All the knobs you can turn! Explore space systematically " Ie Most of the time, the inputs won t be matched! Formulate continuum where possible " ie formulate trends! Deliberately focus on Energy to complement project " but will still talk about delay 24 25 4
Problem Solvable! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem? Problem Solvable! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem?! What look like built out of nand2 gates and inverters? 26 27 Total Power Knobs! Static CMOS: " P tot a(½c load +C sc )V 2 f+vi s(w/l)e -Vt/(nkT/q)! What are the options and knobs we can turn?! What can we do to reduce power? 28 29 Design Space Dimensions How Reduce Short-Circuit Power?! Vdd! Topology " Gate choice, logical optimization " Fanin, fanout, Serial vs parallel! Gate style / logic family " CMOS, Ratioed (N load, P load)! Transistor Sizing! Vth! P sc = ac sc V 2 f # # E = V dd I peak t sc % 1& & % (( $ $ 2' '! The choices you make impact area, speed (delay), power 30 31 5
Gate Logic Family! What gates might we build?! Considerations for each logic family? " CMOS! High fanin?! Serial-Parallel? " Ratioed with PMOS load " Ratioed with NMOS load 32 33 Sizing Reduce Vdd! How do we want to size gates?! What happens as reduce V? " Energy? " Dynamic " Static " Switching Delay?! How low can we push Vdd? 34 35 Reduce V dd Increase V th? $ τ gd =/I=(CV)/I! What is impact of increasing threshold on $ I d =(µc OX /2)(W/L)(V gs -V TH ) 2 $ τ gd impact? $ τ gd α 1/V " Dynamic Energy? " Leakage Energy? " Delay? 36 37 6
Design Problem Design Space Dimensions! Function: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! Assumptions: Match case uncommon " Ie Most of the time, the inputs won t be matched! Deliberately focus on Energy to complement project " but will still talk about delay! Vdd! Topology " Gate choice, logical optimization " Fanin, fanout, Serial vs parallel! Gate style / logic family " CMOS, Ratioed (N load, P load)! Transistor Sizing! Vth! The choices you make impact area, speed (delay), power 38 39 Ideas! Three components of power " P tot = P static + P dyn + P sc Sequential MOS Logic! We know many things we can do to our circuits! Design space is large! Systematically identify dimensions! Identify continuum (trends) tuning when possible! Watch tradeoffs " don t over-tune 40 Classes of Logic Circuits Functions Using Sequential Operations two stable op pts Latch level triggered Flip-Flop edge triggered one stable op pt One-shot single pulse output no stable op pt Ring Oscillator Combinational Circuits: a Current Output(s) depend ONLY on Current Inputs b Suited to problems that can be solved using truth tables Sequential Circuits or State Machines: a Current Output(s) depend on Current Inputs and Past Inputs via State(s) b Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner 42 43 7
Sequential Circuit (or State Machine) Construct Static Bistable Sequential Circuits Present State Inputs REGISTER V o1 Vo2 -> Register is used to Store Past Values of State(s) and Output(s) -> Synchronous Sequential Circuit clock, outputs change with clock event -> Asynchronous Sequential Circuit no clock, outputs change after inputs change 44 Outputs Next State Clock V o3 Basic Crosscoupled Inverter pair 45 Static Bistable Sequential Circuits Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Basic Crosscoupled Inverter pair 46 47 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair V OH = V DD Basic Sequential Circuits (Cells)! Latches! Registers V OL = 0 maintain stable state STATIC: V DD and GND are required to maintain a stable state Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State 48 49 8
Latch! Level-sensitive device! Positive Latch " Output follows input if CLK high! Negative Latch " Output follows input if CLK low = CLK + CLK In Register! Edge-triggered storage element! Positive edge-triggered " Input sampled on rising CLK edge! Negative edgetriggered " Input sampled on falling CLK edge 50 51 Shift Register Two Phase Non-Overlapping Clocks! How do you make a shift register out of latches?! Build master-slave register from pair of latches! Control with non-overlapping clocks 52 53 Two Phase Non-Overlapping Clocks Two Phase Non-Overlapping Clocks! Build master-slave register from pair of latches! Control with non-overlapping clocks! Build master-slave register from pair of latches! Control with non-overlapping clocks 54 55 9
Two Phase Non-Overlapping Clocks Clocking Discipline! What could go wrong if the overlap?! Follow discipline of combinational logic broken by registers! Compute " From state elements " Through combinational logic " To new values for state elements! As long as clock cycle long enough, " Will get correct behavior 56 57 Ideas Admin! Synchronize circuits " to external events (eg Clk) " disciplined reuse of circuitry! Leads to clocked circuit discipline " Uses state holding element (eg Latches and registers) " Prevents " Timing assumptions " (More) complex reasoning about all possible timings! HW 6 due 3/22 58 59 10