Characterization of Semiconductors by Capacitance Methods

University of Iceland 30th April 2007 Experimental physics Characterization of Semiconductors by Capacitance Methods Líney Halla Kristinsdóttir Pétur Gordon Hermannsson Sigurður Ægir Jónsson Instructor: Djelloul Seghier

Contents Contents 1 1 Introduction 2 2 Theoretical background 2 2.1 Schottky diodes................................ 2 2.2 DLTS..................................... 5 3 Measurments and devices 7 3.1 Capacitance-voltage proling (CV)...................... 7 3.2 DLTS..................................... 7 4 Results 8 4.1 Capacitance-voltage proling (CV)...................... 8 4.2 DLTS..................................... 12 5 Conclusion 14 References 15 1

1 Introduction Semiconductors are one of the greatest discoveries of the 20th century. Diodes and transistors, which are based on semiconductors, are now be found in almost all modern electrical devices, such as mobile phones and computers. Still today, semiconductors are an active eld of research and scientists are always on the lookout for new materials posessing distinct characteristics which can be useful in modern technology as well as being suited for production. In this report we examine the characteristics of Schottky diodes. We run a CV proling on a mass-produced silicon diode and DLTS (deep level transient spectoscopy) on a homemade diode made out of CdO (semiconductor) and gold (metal). 2 Theoretical background 2.1 Schottky diodes Figure 1. The various important energy levels in the metal and the semiconductor with respect to the vacuum level. Figure 2. The junction potential produced when the metal and semiconductor are brougt together. The Schottky diode has characteristics that are similar to those of the classical p n junction, except that for many applications it has a much faster response which can be desirable. When a semiconductor is brougt into a contact with a metal, a barrier is formed in the semiconductor from which charge carriers are severaly depleted. The barrier layer is called the depletion layer and can be seen in gures 1 and 2. There is also depletion layer in the metal which is so small that in most cases it can be completely ignored [2]. We may consider the bulk region to be electrically neutral and approximate the boundary between the bulk and the depletion region to be sharp. 2

In gures 1 and 2 an n-type semiconductor is brought into contact with a metal to form a Schottky diode. After the transfer of electrons to the conduction band of the metal the Fermi levels are coincident. Positively charged donor ions are left behind in this region which is practically stripped of electrons. Here the Poission equation is D = N de ɛ 0 (1) where D is the electric displacement and N d is the doping concentration. From 1 the electric potential is determined by d 2 φ dx 2 = N de ɛɛ 0 (2) where x is the distance from the junction into the semiconductor. If we assume N d to be constant we get φ = N de x 2 (3) 2ɛɛ 0 If we apply a reverse bias V r to the Schottky diode the total potential becomes V b + V r where V b is the built-in potential of the junction (see gure 2). From (3) we determine the thickness of the layer (see gure 2) to be 2ɛɛ 0 (V b + V r ) W = (4) N d e Therefore the stored charge in the depletion region can be found by (4) Q = W N d ea = A 2ɛɛ 0 N d e(v b + V r ) (5) where A is the cross sectional area of the junction. The capacitance of the junction then can be found by C = dq = 1 dv r 2 A 2ɛɛ0 N d e V b + V r = ɛɛ 0 A W W = ɛɛ 0 A C (6) From equation (6) it can be shown that 1 C = 2(V b + V r ) (7) 2 A 2 eɛn d It can also be shown [3] that N d (W ) = ( ) 1 C3 dc (8) eɛɛ 0 A 2 dv r It turns out that these equations give quite accurate results despite the assumption that N d is constant. 3

Figure 3. Equvalent circuit for the Schottky diode. Figure 4. of a diode. Typical characteristic In gure 1 we can see en equvalent circuit for the Schottky diode. There one can see that there are two resistances, R l connected in parallel (nonlinear leakage resistance) and R s connected in series. The total impedance is then Z = R l + R s (1 + ω 2 C 2 R 2 l ) + jωcr l 1 + ω 2 C 2 R 2 l (9) In the LCR meter we have to use the approximation that we have a resistance connected either serial or parallel, not both. If we dene C m to be the value measured by the LCR meter (where we ignore R s ) we can calculate the real capacitance C by C m C = 1 (1 + Rs R l ) 2 + ω 2 C 2 R 2 s if we somehow know the value of R s. If R s R l as expected at reverse voltage we see that C m C. A typical I-V diagram is shown in gure 4. By looking at the gure and equation 9 we see that if R l R s the diagram becomes nearly linear at high bias voltages. Then it is safe to assume the resistance in the circuit to only depend on R s. When we apply the reverse bias voltage a small saturation current I s appears. This current is given by I s = A T 2 e eφ b kt (11) where A is the area of the metal-semiconductor interface A multiplied by the so called Richarson constant R (A = AR ) [3], T is the temperature and φ b is the height of the barrier as shown in gure 2. (10) When R l R s at low bias the current is given by ( ev ) I = I s e nkt 1 (12) 4

where n is the ideality factor of the diode n = 1 φ b V For ideal diodes φ b does not depend on V and thus n = 1. For non-ideal diodes n > 1. 2.2 DLTS (13) Figure 5. Illustrates the repetitive lling and reverse bias pulse sequence [1]. Figure 6. Shows the diode capacitance transient as a function of time. [1]. Native crystallographic defects or impurities may create electically active centers with localized potentials in the lattice. These defects have rather high thermal ionization energies (deep defects). These defects can often be characterized by the DLTS technique. The DLTS technique works by observing the capacitance transient associated with the change in depletion region width as the diode returns to equlibrium from an initial nonequilibrium state. The capacitance transient is measured as a function of temperature. The bias on the test diode is pulsed between a bias near zero and some reverse bias V r with a repetation time t r as shown in gure 5. The zero bias condition is held for a time t f during which traps are lled with majority carriers. During the reverse bias pulse the trapped carriers are emitted at a rate e n producing exponential transient in the capacitance, which in general form can be written C(t) = C( ) + C 0 exp ( t/τ) (14) where the time constant τ is equal to e 1 n. This transient is illustrated in gure 6. The basis of the DLTS method is to feed this transient to a "rate window" which provides a maximum output when the time constant τ is equal to a known preset time constant τ ref. 5

Figure 7. Shows how the tranient is measured using two pulses [1]. This is done by sampling the signal with two gates set at time t 1 and t 2 from the beginning of the transient, and producing an output proportional to the dierence between these two signals. Then it can quite easily be shown that if τ t 1 or τ t 2 the dierence output is zero, whereas when τ t 1, t 2 an output is created. With a small gate width t τ an exponential capacitance transient gives a steady output signal S = g C 0 (exp t 1 τ exp t 2 τ ) (15) where g is a calibration factor which also accounts for the gain of the system. The signal varies as τ changes with temperature, and by dierentiating equation (15) with respect to τ we a get maximum where τ(t ) = τ ref = t 2 t 1 ln t 2 /t 1 (16) But now is it also known [1] that if we have a diode made of a certain material with a trap energy E na and capture cross section σ na then e n (T ) = γt 2 σ na exp E na kt where γ is a constant depending on the semiconductor properties and T is the temperature. This allows us to make measurments and see how the location of the maximum changes for dierent values of τ ref. Using the fact that τ = e 1 n and equation (17) we can t the data and estimate E na, and σ na if know the value of γ beforehand. We can also calculate the trap concentration N t by using the equation (17) where N d is the donor density. N t = 2N d C C (18) 6

3 Measurments and devices 3.1 Capacitance-voltage proling (CV) First we connected our diode (the mass-produces silicon diode) to a voltage source and to an ammeter and measured current vs voltage (I-V). We checked both polarities of bias by increasing the voltage V, and found both the forward and reverse characteristics. We were not able to determine the breakdown-voltage because the voltage-source couldn't reach a high enough voltage. By using a high forward voltage we could estimate the value of R s by observing how the current changed linearly with voltage. After that we connected our diode to an LCR-meter and measured the capacitance vs. voltage at reverse bias. The LCR-meter was on C R mode (we ignored the resistance R s in gure 3 since the I-V measurements showed it could be safely ignored). 3.2 DLTS Figure 8. Diagram of a DLTS system [1]. In gure 8 we see how the DLTS system works. The sample (now the CdO/Gold Schottky diode) was put in a cryostat in which the temperature was controlled with liquid nitrogen and a built-in heating element The polarity of the bias was checked to make sure it was reverse. The voltage values of the pulse and bias were xed using the oscilloscope. In our setup the ratio t 1 /t 2, was xed at 13/3. We cooled down the sample and measured for dierent values of t = t 2 t 1 using the DLTS program. 7

4 Results 4.1 Capacitance-voltage proling (CV) 0 10 0.1 0.2 0.3 9 8 7 6 I [na] 0.4 0.5 0.6 I [ma] 5 4 3 2 0.7 0.8 30 25 20 15 10 5 0 Figure 9. V [V] I-V for reverse bias. 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Figure 10. V [V] I-V for forward bias. In gure 10 we can see the I-V relation for a forward bias. By looking at the slope at the endpoints (high forward voltage) we applied Ohms law and determined 10 9 8 7 6 R s = (19 ± 1) Ω (19) I [ma] 5 4 3 2 1 0 1 30 25 20 15 10 5 0 5 Figure 11. V [V] I-V for both reverse and forward voltage. 8

4 6 8 10 ln(i) 12 14 16 18 20 22 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 V [V] Figure 12. Data from the I-V for forward bias tted to determine the ideality factor. By using the I-V for a forward bias and equation (12) we tted the data and determined the ideality factor (see gure 12) to be which is a little more than expected. n = 1.55 ± 0.05 (20) Looking at equation (7), we see that we should get straight line if we plot 1/C 2 vs V, but from gure 13 we see that clearly isn't the case, and therefore N d isn't constant. By tting the data for the low values of V (gure 14), where N d appears to be a constant, we determined V b to be V b = 0.3 V (21) And by using equations (8) and (6) we can get gure 15 from the data, where we see that the donor concentration is varying a little but is close too N d 10 13 cm 3 (22) 9

0.02 0.018 0.016 0.014 1/C 2 [1/pF 2 ] 0.012 0.01 0.008 0.006 0.004 0.002 Figure 13. 0 0 5 10 15 20 25 30 35 V [V] Data from the C-V measurement. 0.003 0.0025 0.002 1/C 2 [1/pF 2 ] 0.0015 0.001 0.0005 Figure 14. 0 0 0.5 1 1.5 2 2.5 3 V [V] The low voltage data from C-V measurements. 10

10 14 N d [cm 3 ] 10 13 10 12 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 W [m] x 10 5 Figure 15. Donor concentration. 11

4.2 DLTS 0-0.5-1 t=20.7 ms t=41.4 ms t=82.8 ms t=165.6 ms t=414.0 ms -1.5 C [pf] -2-2.5-3 -3.5-4 -4.5 320 330 340 350 360 370 380 390 400 Figure 16. The amplitude C 0 plotted as function of temperature T for dierent values of τ. In gure 17 we see how the amplitude C 0 changes with temperature T for few dierent values of t = t 2 t 1. The peak values were used to plot gure 17, from which we can determine the values of the trap energy E a and their capture cross section σ a. By using equations 16 and 17 we see that gure 17 where ln e n /T 2 is plotted vs 1000/T should give us straight line with slope 1000 E a /k and should intersect the y-axis at ln γσ a. We know that γ = 2.28 10 20 cm 2 s 1 K 2 and from gure 17 we nd T [K] E a = (0.70 ± 0.05) ev σ a = 3.5 10 15 cm 2 (23) and we see that E a is rather deep compared to the CdO band gap of 2.5 ev. By using equation 18 (where N d 10 15 cm 3 ) and C = S/0.43 where S is the height of the DLTS peak we can nd the trap concentration N t in each case τ [ms] N t [cm 3 ] 14.4 1.08 10 14 28.2 1.08 10 14 56.4 9.83 10 13 112.9 9.74 10 13 282.3 9.05 10 13 12

7.5 8 8.5 ln(e n /T 2 ) 9 9.5 10 10.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 Figure 17. determine E a and σ a. 1000/T [K 1 ] The peak values from gure 16 used to plot straight line and 13

5 Conclusion For our mass-produced silicon diode we got an ideality factor of n = (1.55 ± 0.05). However, we expected value closer to 1. We estimated that N d 10 13 cm 3 although it was varying a bit. For the CdO/Gold diode we found a defect at E a (0.7±0.5) ev having a capture cross section σ a = 3.5 10 15 cm 2 and a trap concentration of N t 10 14 cm 3. Líney Halla Kristinsdóttir Pétur Gordon Hermannsson Sigurður Ægir Jónsson 14

References [1] Blood, P., and J.W. Orton. 1992. The Electrical Characterization Of Semiconductors: Majority Carriers And Electon States. Academic Press, USA. [2] Kittel, C. 2005. Solid State Physics. John Wileys & Sons, USA. [3] Singh, J. 1994. Semiconductor Devices. McGraw-Hill, USA. [4] Wikipedia 2007. Internet: http://en.wikipedia.org/wiki/ Deep_Level_Transient_Spectroscopy. [5] Wikipedia 2007. Internet: http://en.wikipedia.org/wiki/schottky_diode. 15