Follow The Leader Architecture

Similar documents
HIGHER-ORDER FILTERS. Cascade of Biquad Filters. Follow the Leader Feedback Filters (FLF) ELEN 622 (ESS)

5.5 Application of Frequency Response: Signal Filters

SIMON FRASER UNIVERSITY School of Engineering Science ENSC 320 Electric Circuits II. Solutions to Assignment 3 February 2005.

ECEN620: Network Theory Broadband Circuit Design Fall 2018

6.447 rad/sec and ln (% OS /100) tan Thus pc. the testing point is s 3.33 j5.519

CHAPTER 13 FILTERS AND TUNED AMPLIFIERS

Lecture #9 Continuous time filter

EE 508 Lecture 16. Filter Transformations. Lowpass to Bandpass Lowpass to Highpass Lowpass to Band-reject

Linearteam tech paper. The analysis of fourth-order state variable filter and it s application to Linkwitz- Riley filters

Question 1 Equivalent Circuits

Lecture 10 Filtering: Applied Concepts

Lecture 4. Chapter 11 Nise. Controller Design via Frequency Response. G. Hovland 2004

Digital Control System

EE 508 Lecture 16. Filter Transformations. Lowpass to Bandpass Lowpass to Highpass Lowpass to Band-reject

EE247 Lecture 10. Switched-Capacitor Integrator C

SIMON FRASER UNIVERSITY School of Engineering Science ENSC 320 Electric Circuits II. R 4 := 100 kohm

into a discrete time function. Recall that the table of Laplace/z-transforms is constructed by (i) selecting to get

HOMEWORK ASSIGNMENT #2

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder

MAE140 Linear Circuits Fall 2012 Final, December 13th

Design of Digital Filters

Design By Emulation (Indirect Method)

ELECTRONIC FILTERS. Celso José Faria de Araújo, M.Sc.

Chapter 9: Controller design. Controller design. Controller design

EE 508 Lecture 16. Filter Transformations. Lowpass to Bandpass Lowpass to Highpass Lowpass to Band-reject

ECE 3510 Root Locus Design Examples. PI To eliminate steady-state error (for constant inputs) & perfect rejection of constant disturbances

ISSN: ISO 9001:2008 Certified International Journal of Engineering and Innovative Technology (IJEIT) Volume 5, Issue 5, November 2015

55:041 Electronic Circuits

Active Filters an Introduction

Homework 12 Solution - AME30315, Spring 2013

A Simple Approach to Synthesizing Naïve Quantized Control for Reference Tracking

Active Filters an Introduction

Chapter 4 Interconnection of LTI Systems

Gain and Phase Margins Based Delay Dependent Stability Analysis of Two- Area LFC System with Communication Delays

Massachusetts Institute of Technology Dynamics and Control II

CHAPTER 4 DESIGN OF STATE FEEDBACK CONTROLLERS AND STATE OBSERVERS USING REDUCED ORDER MODEL

General Topology of a single stage microwave amplifier

Summary of last lecture

Operational transconductance amplifier based voltage-mode universal filter

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder

Control Systems Engineering ( Chapter 7. Steady-State Errors ) Prof. Kwang-Chun Ho Tel: Fax:

EE C128 / ME C134 Problem Set 1 Solution (Fall 2010) Wenjie Chen and Jansen Sheng, UC Berkeley

RaneNote BESSEL FILTER CROSSOVER

Designing Circuits Synthesis - Lego

( ) 2. 1) Bode plots/transfer functions. a. Draw magnitude and phase bode plots for the transfer function

S_LOOP: SINGLE-LOOP FEEDBACK CONTROL SYSTEM ANALYSIS

Dynamic Simulation of a Three-Phase Induction Motor Using Matlab Simulink

CHAPTER 8 OBSERVER BASED REDUCED ORDER CONTROLLER DESIGN FOR LARGE SCALE LINEAR DISCRETE-TIME CONTROL SYSTEMS

Chapter 2 Sampling and Quantization. In order to investigate sampling and quantization, the difference between analog

376 CHAPTER 6. THE FREQUENCY-RESPONSE DESIGN METHOD. D(s) = we get the compensated system with :

ECE382/ME482 Spring 2004 Homework 4 Solution November 14,

Chapter 17 Amplifier Frequency Response

SKEE 3143 CONTROL SYSTEM DESIGN. CHAPTER 3 Compensator Design Using the Bode Plot

Solutions. Digital Control Systems ( ) 120 minutes examination time + 15 minutes reading time at the beginning of the exam

Evolutionary Algorithms Based Fixed Order Robust Controller Design and Robustness Performance Analysis

Chapter 2: Problem Solutions

Function and Impulse Response

SERIES COMPENSATION: VOLTAGE COMPENSATION USING DVR (Lectures 41-48)

Copyright 1967, by the author(s). All rights reserved.

Homework Assignment No. 3 - Solutions

Chapter 13. Root Locus Introduction

CONTROL SYSTEMS. Chapter 2 : Block Diagram & Signal Flow Graphs GATE Objective & Numerical Type Questions

No-load And Blocked Rotor Test On An Induction Machine

NAME (pinyin/italian)... MATRICULATION NUMBER... SIGNATURE

Root Locus Contents. Root locus, sketching algorithm. Root locus, examples. Root locus, proofs. Root locus, control examples

EE Control Systems LECTURE 14

Introduction to Laplace Transform Techniques in Circuit Analysis

Lecture 28. Passive HP Filter Design

Behavioral Modeling of Transmission Line Channels via Linear Transformations

Given the following circuit with unknown initial capacitor voltage v(0): X(s) Immediately, we know that the transfer function H(s) is

EE 4443/5329. LAB 3: Control of Industrial Systems. Simulation and Hardware Control (PID Design) The Inverted Pendulum. (ECP Systems-Model: 505)

EE/ME/AE324: Dynamical Systems. Chapter 8: Transfer Function Analysis

Spring 2014 EE 445S Real-Time Digital Signal Processing Laboratory. Homework #0 Solutions on Review of Signals and Systems Material

A PLC BASED MIMO PID CONTROLLER FOR MULTIVARIABLE INDUSTRIAL PROCESSES

Main Topics: The Past, H(s): Poles, zeros, s-plane, and stability; Decomposition of the complete response.

LOAD FREQUENCY CONTROL OF MULTI AREA INTERCONNECTED SYSTEM WITH TCPS AND DIVERSE SOURCES OF POWER GENERATION

A Simplified Methodology for the Synthesis of Adaptive Flight Control Systems

Adder Circuits Ivor Page 1

NOTE: The items d) and e) of Question 4 gave you bonus marks.

ME 375 FINAL EXAM SOLUTIONS Friday December 17, 2004

Root Locus Diagram. Root loci: The portion of root locus when k assume positive values: that is 0

Homework #7 Solution. Solutions: ΔP L Δω. Fig. 1

A Compensated Acoustic Actuator for Systems with Strong Dynamic Pressure Coupling

FUNDAMENTALS OF POWER SYSTEMS

Liquid cooling

THE PARAMETERIZATION OF ALL TWO-DEGREES-OF-FREEDOM SEMISTRONGLY STABILIZING CONTROLLERS. Tatsuya Hoshikawa, Kou Yamada and Yuko Tatsumi

Digital Control System

Digital Signal Processing

The Measurement of DC Voltage Signal Using the UTI

Hybrid Projective Dislocated Synchronization of Liu Chaotic System Based on Parameters Identification

CONTROL SYSTEMS, ROBOTICS AND AUTOMATION Vol. VIII Decoupling Control - M. Fikar

Wolfgang Hofle. CERN CAS Darmstadt, October W. Hofle feedback systems

Assessment of Performance for Single Loop Control Systems

Part A: Signal Processing. Professor E. Ambikairajah UNSW, Australia

Reference:W:\Lib\MathCAD\Default\defaults.mcd

A Simplified Dynamics Block Diagram for a Four-Axis Stabilized Platform

On Stability of Electronic Circuits

LTV System Modelling

Control Systems Analysis and Design by the Root-Locus Method

Control of Delayed Integrating Processes Using Two Feedback Controllers R MS Approach

Transcription:

ECE 6(ESS) Follow The Leader Architecture 6 th Order Elliptic andpa Filter A numerical example

Objective To deign a 6th order bandpa elliptic filter uing the Follow-the-Leader (FLF) architecture. The pecification are: Specification Value Order 6 Paband.9MHz to.mhz Paband Ripple 0.d Attenuation 0d at 0.6MHz

Realization of High Order Tranfer Function (N>) Cacade of nd order ection (one t order ection if N i odd) Leapfrog Follow-The-Leader Cacade FLF Leap-Frog Senitivity High Medium Low Eay to Tune Medium Eay Difficult

Primary Reonator loc -F -F V in P P P V out It provide compenatory internal interaction between the different filter ection through coupling the biquad building bloc.

Deign Quetion: How do we obtain the feedbac coefficient F and F? How do we determine the pecification for each biquadratic ection? Q ω o Gain

Deign Procedure Start with the Lowpa equivalent ytem. -F -F V in K 0 K K K V out ad New: Elliptic Filter need finite zero in their lowpa equivalent tranfer function.

Implementation of Finite Zero by the Summation Technique -F -F V in K 0 V 0 K V V V K K 0 V out

Deign Procedure Let for now K K K and () Applying Maon rule, the complete tranfer function i given by: () T ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( 0 0 F T F T T T T K V V H in out ( ) ( ) ( ) ( ) ( ) 0 0 F F K

Deign Procedure From Matlab or Fieta, we can obtain the lowpa prototype tranfer function of the deired 6 th Order Elliptic Filter: () Equating the denominator of equation () and (), we obtain the following et of equation from which we can olve for, F, and F. (4) Alo from equation () and () (5) 0 0 0 0 ) ( a a a b b b b b a m H ( ) 0 a F F a F a 0 0 0 b a K m

Deign Procedure To obtain the ummation coefficient, we equate the numerator of equation () and (). If H() i a bandpa: 0 b 0. Then, we obtain the following et of equation from which we can determine, and. (6) ( ) 0 0 0 b b b b

Deigning for Maximum Dynamic Range We need to ditribute the gain of each ection T(), i.e. K, K and K uch that we maximize the Dynamic Range. The maximum dynamic range will be obtained if the ignal pectra at the output of all ection have equal maxima, i.e. V out,max V,max V,max V,max V 0,max

Maximizing Dynamic Range To mae V,max V out,max where K0 K0 K0q (7) V q V out,max,max prior prior to to caling caling (8) We alo need to adjut the ummation coefficient to eep the overall gain: i (9) i i q If we aume a flat pectrum for the input, i.e. Vin(ω) V out, max Max H ( ω) V,max Max H( ω) (0)

Maximizing Dynamic Range Where () To obtain K, K and K : () 0 0 ) ( ) ( ) ( a a a K V V H in,,. ) ( ) ( 4 i for H Max H Max K i i i ω ω ω ω ω ω

Deign Procedure The feedbac coefficient need to be readjuted to eep the ame loop gain: () The ummation coefficient alo need to be readjuted again: (4) K K F F F K K K F F F q q K q K K

Summary of Deign Procedure Obtain from Matlab or Fieta the lowpa prototype for the deired filter. From equation (4), (5) and (6), obtain K 0, the feedbac and the ummation coefficient. To maximize dynamic range, obtain q uing equation (8). Recalculate K 0 uing equation (7). Calculate the gain of each ection, i.e. K, K and K uing equation (). Recalculate the feedbac and ummation coefficient uing equation () and (4). Finally, apply a lowpa-to-bandpa tranformation to obtain the deired bandpa filter pecification: ω 0 π Q Q0 where Q i the quality factor of the overall filter and Q 0 i that required for each biquad ection. Note: A Matlab program wa written to automate the deign procedure for an arbitrary filter pecification of order N. f L f U

Summary of Reult For the required pecification, the following value were obtained: Feedbac Coefficient F 0.657640 F 0.7545 Feedforward Coefficient 0 0 0.6979-0.657.984 Gain for the input and each biquad tage Center frequency and Q 0 of each biquad tage K0 0.604488 K.49 K.65 K f 0.9975MHz Q 0 5.7

Simulation Reult Sytem Level The complete filter wa imulated in Cadence at a ytem-level. The reult are hown below: Ripple 0.d Magnitude Repone Phae Repone

Tranitor Level Implementation To implement each biquadratic ection, a two-integrator loop biquad OTA-C filter wa ued. Advantage with repect to Active-RC: Eay Tunability by changing the bia current of the OTA. (Active-RC need the ue of varactor). Lower Power Conumption and Smaller Area. Diadvantage with repect to Active-RC: Smaller Dynamic Range Poorer Linearity

Tranitor Level Implementation of each iquad Section Vout Vin gm - OUT gm4 - OUT gm - OUT gm - OUT C C R R 4 ) ( C C g g C g C g H m m m m

Thi image cannot currently be diplayed. Deign of Lole Integrator The lole integrator wa deigned to have unity gain at f 0.9975MHz. g m H ( ω) ω C The following pecification are needed if a 5% variation in Q i allowed: Exce Phae : g m 76.5µA φ E C 0 pf Q Q Q a V.5 0 rad 0.086 DC Q Gain : AV 60 55. 58d Q Q a

Deign of Lole Integrator Due to the relatively high DC gain required for the OTA, a foldedcacode topology wa ued: VDD M4 M M M0 Vbp M Ibia Vin M M Vin- Vbn Vout M6 M7 M9 M8 M M4 M5 VSS Tranconductance DC Gain GW ia Current Power Conumption Active Area 76.5µA/V 64.d 6MHz 40µA 79µW 77µm

Simulation Reult of the Lole Integrator The exce phae without any compenation wa.7. Paive exce phae compenation wa ued R55Ω. Magnitude Repone Phae Repone

Deign of iquadratic andpa To reue the deigned OTA: Filter g m g m 76.5 µ A V C C 0 pf C g m 4 ω0. 87 µ A Q 0 V Tranconductance g m depend on K i g K m i m4 For demontration purpoe, g m g m4, i.e. K g

Deign of iquadratic andpa Filter Due to the relatively mall tranconductance required, ource degeneration wa ued. Alo, a PMOS differential pair wa more VDD uitable. M9 M8 MA M M4 M5 R M6 Vbp M7 Vin M M Vin- Vout Vbn Ibia M0 M M4 M M VSS Tranconductance DC Gain GW ia Current Power Conumption Active Area.87µA/V 6.5d 6.MHz 4µA 77.µW 80µm

Simulation Reult of the iquadratic andpa Filter Frequency Repone Step Repone

Summation Node To complete the tranitor-level deign, we need two ummation node: -F -F V in K 0 V 0 K V V V K K 0 V out

Summation Node The ummation node can be implemented with OTA in the following configuration: Vin K0 gm0 V gm0 OUT OUT - - V - F gm0 V - gm0 OUT OUT V - OUT F gm0 - gm0 V OUT gm0 - gm0 OUT V0 - OUT Vout Summation Node for the Feedbac Path Summation Node at the Output If g m0 i choen large enough, the output reitance of each OTA doe not need to be very high. Exce Phae of OTA can be a concern.

Summation Node Due to the deired low exce phae introduced by the OTA, it i more convenient to ue a imple differential pair. VDD M M Vout Ibia Vin M M Vin- M9 M VSS Tranconductance ia Current Power Conumption Active Area 00µA/V 40µA 64µW 69µm

Simulation Reult of the Complete FLF Filter (Tranitor v. Sytem Level) Ripple ~0.d Magnitude Repone Phae Repone

Simulation Reult of the Complete FLF Filter (Tranitor v. Sytem Level) Tranient Repone to a Sinewave Step Repone

Summary of Reult Specification Paband Paband Ripple Attenuation Power Conumption Value.9MHz to.mhz ~0.d 40d at 0.6MHz 8.5mW Active Area,44µm Total Area ~,549µm

Problem to be olved Voltage Swing: The allowable input voltage wing i only 00mV. A mall voltage wing i expected, ince the OTA have a mall linear range limited by ±VDSAT of the input tranitor (in cae no linearization technique i ued, uch a ource degeneration or other). Neverthele, 00mV i too mall and i baically becaue the OTA with g m 76.5µA/V ue input tranitor with a mall VDSAT and no linearization technique i being ued. I need to redeign thee OTA to increae the linear range. ia Networ: To deign the bia networ for the folded-cacode OTA capable of effectively tracing change of VT due to proce variation. Senitivity and Tunability: To characterize the complete filter in term of enitivity and tunability. Layout

Reference [] Sedra, racett. Filter Theory and Deign: Active and Paive. Matrix Serie in Circuit and Sytem. pp. 589-659. [] Deliyanni, Sun, Fidler. Continuou-Time Active Filter Deign. CRC Pre 999. pp. 5-80. [] G. Hurtig, III. The Primary Reonator loc Technique of Filter Synthei Proc. Int. Filter Sympoium, p.84, 97. [4] arbargire. Explicit Deign of General High-Order FLF OTA-C Filter. Electronic Letter. 5th Augut 999, Vol. 5, No. 6, pp. 89-90. [5] Jie Wu, Ezz I. El-Mary. Synthei of Follow-the-Leader Feedbac Log- Domain Filter. IEEE 998. 0-780-5008-/98. pp. 8-84.