Design of Combinational Logic - PDF Free Download

Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASHIK 3. Design of Combinational Logic By Prof. Anand N. Gharu (Assistant Professor) PVGCOE Computer Dept.. 30 th June 2017

CONTENTS :- 1. Code Converter - BCD - EXCESS-3 - Gray Code - Binary Code 2. Half Adder, Full Adder, Half Substractor, Full Substractor 3. Binary Adder (IC 7483) 4. BCD Adder 5. Look Ahead Carry Generator 6. Multiplexers (MUX) (IC 74151, 74153) 7. Demultiplexers (DEMUX) (IC 74138, 74154) 8. Comparators 9. Parity Generator and Checker

INTRODUCTION OF COMBINATIONAL CIRCUITS Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output variables 1. Combination Circuits : - The output of combinational circuit at any instant, depends only on the levels present at input terminals. - It does not use any memory - it can have number inputs and outputs. Example: 1. Adder, Substractor 2. Comparator 3. Code Converters 4. Encoders, Decoders 5. Multiplexers and Demutiplexers

Code Converters Code converters take an input code, translate to its equivalent output code. Input code Code converter Output code Example: BCD to Excess-3 Code Converter. Input: BCD digit Output: Excess-3 digit 4

Binary Codes An n-bit binary code is a group of n bits that assume up to 2 n distinct combinations of 1s and 0s, with each combination representing one element of the set being coded For the 10 digits need a 4 bit code. One code is called Binary Coded Decimal (BCD) 5

Binary Coded Decimal Decimal Digit 0 1 2 3 4 5 6 7 8 9 BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Note: 1010, 1011, 1100, 1101, 1110, and 1111 are INVALID CODE! Let s crack these ex1: dec-to-bcd ex2: BCD-to-dec (a) 35 (b) 98 (c) 170 (d) 2469 (a) 10000110 (b) 001101010001 (c) 1001010001110000

Excess-3 BCD Code Decimal digits Excess-3 BCD code 0 0011 1 0100 2 0101 3 0110 4 0111 5 1000 6 1001 7 1010 8 1011 9 1100

Excess-3 Code (XS-3) Decimal No. BCD Code Excess-3 Code= BCD + Excess-3 0 0000 0011 1 0001 0100 2 0010 0101 3 0011 0110 4 0100 0111 5 0101 1000 6 0110 1001 7 0111 1010 8 1000 1011 9 1001 1100 8/29/2017 Amit Nevase 8

Excess-3 Code (XS-3) Example 1: Obtain Xs-3 Code for 428 Decimal 8/29/2017 Amit Nevase 9

Excess-3 Code (XS-3) Example 1: Obtain Xs-3 Code for 428 Decimal 4 2 8 0100 0010 1000 + 0011 0011 0011 0111 0101 1011 8/29/2017 Amit Nevase 10

Exercise Convert following Decimal Numbers into Excess- 3 Code 1. (40) 10 2. (88) 10 3. (64) 10 4. (23) 10 8/29/2017 Amit Nevase 11

BCD-to-Excess-3 Code Converter Truth table: BCD Excess-3 A B C D W X Y Z 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 2 0 0 1 0 0 1 0 1 3 0 0 1 1 0 1 1 0 4 0 1 0 0 0 1 1 1 5 0 1 0 1 1 0 0 0 6 0 1 1 0 1 0 0 1 7 0 1 1 1 1 0 1 0 8 1 0 0 0 1 0 1 1 9 1 0 0 1 1 1 0 0 10 1 0 1 0 X X X X 11 1 0 1 1 X X X X 12 1 1 0 0 X X X X 13 1 1 0 1 X X X X 14 1 1 1 0 X X X X 15 1 1 1 1 X X X X W = S m(5,6,7,8,9) x = S m(1,2,3,4,9) y = S m(0,3,4,7,8) z = S m(0,2,4,6,8) 12

W = Sm(5,6,7,8,9)+ Sd(10,11,12,13,14,15) = a+bc+bd = a+b(c+d) AB 00 01 11 10 CD 00 x 1 01 11 10 0 1 3 2 AB 00 CD 00 1 01 11 10 1 1 1 4 5 7 6 x 1 x x 12 8 13 15 14 x x 9 11 10 y = Sm(0,3,4,7,8)+ Sd(10,11,12,13,14,15) 0 1 = c d +cd 01 11 10 1 1 1 3 2 4 5 7 6 x 1 x x x 12 8 13 15 14 x x 9 11 10 x =Sm(1,2,3,4,9)+ Sd(10,11,12,13,14,15) bc d +b d+b c=bc d +b (c+d) AB 00 01 11 10 CD Underlined 00 1 x 0 0 4 12 8 terms are 01 1 x 1 1 5 13 9 common 11 1 x x 10 1 3 2 7 6 x 15 14 x 11 10 = d AB 00 01 11 10 CD 00 1 1 x 1 01 11 10 z = Sm(0,2,4,6,8)+ Sd(10,11,12,13,14,15) 0 1 3 1 1 2 4 5 7 6 x x x 12 8 13 15 14 x x 9 11 10 13

The Excess-3 BCD system is formed by adding 0011 to each BCD value as in Table 2. For example, the decimal number 7, which is coded as 0111 in BCD, is coded as 0111+0011=1010 in Excess-3 BCD. Decimal Numerals Excess-3 0 0011 1 0100 2 0101 3 0110 4 0111 5 1000 6 1001 7 1010 8 1011 9 1100

THE BCD TO EXCESS 3 CODE CONVERTER BCD Excess-3 circuit will convert numbers from their binary representation to their excess-3 representation. Hence our truth table is as below: B3 B2 B1 B0 E3 E2 E1 E0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0

E2=B2^(B1+B0)

E1=(B1^B0)

E0=B0

Block diagram

Applications Excess-3 was used on some older computers Cash registers Hand held portable electronic calculators

BCD to XS 3 code converter- Design (1)... TRUTH TABLE FOR BCD TO XS3 CODE CONVERTER: Input ( Std BCD code) Output ( XS3 Code) A B C D w x y z 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 X X X X 1 0 1 1 X X X X 1 1 0 1 X X X X 1 1 1 0 X X X X 1 1 1 1 X X X X 21

BCD to XS 3 code converter- Design (2)... K-maps for simplification and simplified Boolean expressions 22

BCD to XS 3 code converter- Design (3)... After the manipulation of the Boolean expressions for using common gates for two or more outputs, logic expressions can be given by z=d y=cd+c D = (C+D) x= B C + B D + BC D = B (C+D) + BC D w= A + BC + BD = A + B (C+D) 23

BCD to XS 3 code converter- Design (4) 24

The Gray Code The Gray code is unweighted and is not an arithmetic code. o There are no specific weights assigned to the bit positions. Important: the Gray code exhibits only a single bit change from one code word to the next in sequence. o This property is important in many applications, such as shaft position encoders.

The Gray Code Decimal Binary Gray Code 0 0000 0000 1 0001 0001 2 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111 6 0110 0101 7 0111 0100 Decimal Binary Gray Code 8 1000 1100 9 1001 1101 10 1010 1111 11 1011 1110 12 1100 1010 13 1101 1011 14 1110 1001 15 1111 1000

The Gray Code Binary-to-Gray code conversion o The MSB in the Gray code is the same as corresponding MSB in the binary number. o Going from left to right, add each adjacent pair of binary code bits to get the next Gray code bit. Discard carries. ex: convert 10110 2 to Gray code 1 + 0 + 1 + 1 + 0 binary 1 1 1 0 1 Gray

The Gray Code Gray-to-Binary Conversion o o The MSB in the binary code is the same as the corresponding bit in the Gray code. Add each binary code bit generated to the Gray code bit in the next adjacent position. Discard carries. ex: convert the Gray code word 11011 to binary 1 1 0 1 1 Gray + + + + 1 0 0 1 0 Binary

Gray Code The gray code is non-weighted code. It is not suitable for arithmetic operations. It is a cyclic code because successive code words in this code differ in one bit position only i.e. unit distance code 8/29/2017 Amit Nevase 29

Binary to Gray Code Conversion If an n bit binary number is represented by Bn, Bn,... B 1 1 Gn, Gn,... G 1 1 and its gray code equivalent by Bn Gn where and are the MSBs, then gray code bits are obtained from the binary code as follows; G n Bn n 1 n n 1 G B B Gn 2 Bn 1 Bn 2 G1 B2 B1 *where the symbol represents Exclusive-OR operation 8/29/2017 Amit Nevase 30

Binary to Gray Code Conversion Example 1: Convert 1011 Binary Number into Gray Code 8/29/2017 Amit Nevase 31

Binary to Gray Code Conversion Example 1: Convert 1011 Binary Number into Gray Code Binary Number 1 0 1 1 8/29/2017 Amit Nevase 32

Example 1: Continue Binary Number 1 0 1 1 Gray Code 1 8/29/2017 Amit Nevase 33

Example 1: Continue Binary Number 1 0 1 1 Gray Code 1 1 8/29/2017 Amit Nevase 34

Example 1: Continue Binary Number 1 0 1 1 Gray Code 1 1 1 8/29/2017 Amit Nevase 35

Example 1: Continue Binary Number 1 0 1 1 Gray Code 1 1 1 0 8/29/2017 Amit Nevase 36

Example 1: Continue Binary Number 1 0 1 1 Gray Code 1 1 1 0 8/29/2017 Amit Nevase 37

Binary to Gray Code Conversion Example 2: Convert 1001 Binary Number into Gray Code 8/29/2017 Amit Nevase 38

Binary to Gray Code Conversion Example 2: Convert 1001 Binary Number into Gray Code Binary Number 1 0 0 1 Gray Code 1 1 0 1 8/29/2017 Amit Nevase 39

Binary to Gray Code Conversion Example 3: Convert 1111 Binary Number into Gray Code 8/29/2017 Amit Nevase 40

Binary to Gray Code Conversion Example 3: Convert 1111 Binary Number into Gray Code Binary Number 1 1 1 1 Gray Code 1 0 0 0 8/29/2017 Amit Nevase 41

Binary to Gray Code Conversion Example 4: Convert 1010 Binary Number into Gray Code 8/29/2017 Amit Nevase 42

Binary to Gray Code Conversion Example 4: Convert 1010 Binary Number into Gray Code Binary Number 1 0 1 0 Gray Code 1 1 1 1 8/29/2017 Amit Nevase 43

Binary and Corresponding Gray Codes Decimal No. Binary No. Gray Code 0 0000 0000 1 0001 0001 2 0010 0011 3 0011 0010 4 0100 0110 5 0101 0111 6 0110 0101 7 0111 0100 8 1000 1100 9 1001 1101 10 1010 1111 11 1011 1110 12 1100 1010 13 1101 1011 14 1110 1001 8/29/2017 Amit Nevase 44 15 1111 1000

Exercise Convert following Binary Numbers into Gray Code 1. (1011) 2 2. (110110010) 2 3. (101010110101) 2 4. (100001) 2 8/29/2017 Amit Nevase 45

Gray Code to Binary Conversion If an n bit gray code is represented by Gn, Gn,... G 1 1 Bn, Bn,... B 1 1 and its binary equivalent then binary bits are obtained from gray bits as follows; B n Gn n 1 n n 1 B B G Bn 2 Bn 1 Gn 2 B1 B2 G1 *where the symbol represents Exclusive-OR operation 8/29/2017 Amit Nevase 46

Gray Code to Binary Conversion Example 1: Convert 1110 Gray code into Binary Number. 8/29/2017 Amit Nevase 47

Gray Code to Binary Conversion Example 1: Convert 1110 Gray code into Binary Number. Gray Code 1 1 1 0 8/29/2017 Amit Nevase 48

Example 1: Continue Gray Code 1 1 1 0 Binary Number 1 8/29/2017 Amit Nevase 49

Example 1: Continue Gray Code 1 1 1 0 Binary Number 1 0 8/29/2017 Amit Nevase 50

Example 1: Continue Gray Code 1 1 1 0 Binary Number 1 0 1 8/29/2017 Amit Nevase 51

Example 1: Continue Gray Code 1 1 1 0 Binary Number 1 0 1 1 8/29/2017 Amit Nevase 52

Example 1: Continue Gray Code 1 1 1 0 Binary Number 1 0 1 1 8/29/2017 Amit Nevase 53

Gray Code to Binary Conversion Example 2: Convert 1101 Gray code into Binary Number. 8/29/2017 Amit Nevase 54

Gray Code to Binary Conversion Example 2: Convert 1101 Gray code into Binary Number. Gray Code 1 1 0 1 Binary Number 1 0 0 1 8/29/2017 Amit Nevase 55

Gray Code to Binary Conversion Example 3: Convert 1100 Gray code into Binary Number. 8/29/2017 Amit Nevase 56

Gray Code to Binary Conversion Example 3: Convert 1100 Gray code into Binary Number. Gray Code 1 1 0 0 Binary Number 1 0 0 0 8/29/2017 Amit Nevase 57

Exercise Convert following Gray Numbers into Binary Numbers 1. (1111) GRAY 2. (101110) GRAY 3. (100010110) GRAY 4. (11100111) GRAY 8/29/2017 Amit Nevase 58

FOUR BIT BINARY TO GRAY CODE CONVERTER DESIGN (1) TRUTH TABLE: INPUT ( BINARY) MSB + + + + 0 1 1 0 1 0 1 0 1 1 OUTPUTS (GRAY CODE) Binary code Gray code B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 59

Combinational Logic Circuits Introduction Standard representation of canonical forms (SOP & POS), Maxterm and Minterm, Conversion between SOP and POS forms K-map reduction techniques upto 4 variables (SOP & POS form), Design of Half Adder, Full Adder, Half Subtractor & Full Subtractor using k-map Code Converter using K-map: Gray to Binary, Binary to Gray Code Converter (upto 4 bit) IC 7447 as BCD to 7- Segment decoder driver IC 7483 as Adder & Subtractor, 1 Digit BCD Adder Block Schematic of ALU IC 74181 IC 74381 8/29/2017 60

Design of Binary to Gray Code Converter Block Diagram: Binary Inputs B 3 B 2 B 1 B 0 Binary to Gray Code converter G 3 G 2 G 1 G 0 Gray Outputs 8/29/2017 61

BINARY TO GRAY CONVERSION

Design of Binary to Gray Code Converter K-map for G 0 : B 3 B 2 BB 3 2 BB 3 2 B 1 B 0 00 01 BB 1 0 BB 1 0 BB 1 0 BB 1 0 00 01 11 10 0 0 1 1 0 3 1 2 0 4 1 5 0 7 1 6 G0 B1B 0 B1B0 BB 3 2 11 0 12 1 13 0 15 1 14 G0 B0 B1 BB 3 2 10 0 8 1 9 0 11 1 10 BB 1 0 BB 1 0 8/29/2017 63

Design of Binary to Gray Code Converter K-map for G 1 : B 3 B 2 BB 3 2 BB 3 2 B 1 B 0 00 01 BB 1 0 BB 1 0 BB 1 0 BB 1 0 00 01 11 10 0 0 0 1 1 3 1 2 1 4 1 5 0 7 0 6 G1 B2B1 B2B1 BB 3 2 11 1 12 1 13 0 15 0 14 G1 B2 B1 BB 3 2 10 0 8 0 9 1 11 1 10 BB 2 1 BB 2 1 8/29/2017 64

Design of Binary to Gray Code Converter K-map for G 2 : B 3 B 2 BB 3 2 BB 3 2 B 1 B 0 00 01 BB 1 0 BB 1 0 BB 1 0 BB 1 0 00 01 11 10 0 0 0 1 0 3 0 2 1 4 1 5 1 7 1 6 G2 B3B 2 B3B2 BB 3 2 11 0 12 0 13 0 15 0 14 G2 B3 B2 BB 3 2 10 1 8 1 9 1 11 1 10 BB 3 2 BB 3 2 8/29/2017 65

Design of Binary to Gray Code Converter K-map for G 3 : B 3 B 2 BB 3 2 BB 3 2 B 1 B 0 00 01 BB 1 0 BB 1 0 BB 1 0 BB 1 0 00 01 11 10 0 0 0 1 0 3 0 2 0 4 0 5 0 7 0 6 G3 B3 BB 3 2 BB 3 2 11 10 1 12 1 13 1 15 1 14 1 8 1 9 1 11 1 10 B3 8/29/2017 66

Design of Binary to Gray Code Converter Logic Diagram: B 3 B 2 B 1 B 0 G3 G B B 2 3 2 G B B 1 2 1 G B B 0 1 0 8/29/2017 67

Design of Gray to Binary Code Converter Block Diagram: Gray Inputs G 3 G 2 G 1 Gray to Binary Code B 3 B 2 B 1 Binary Outputs G 0 converter B 0 8/29/2017 68

GRAY TO BINARY CONVERSION

Design of Gray to Binary Code Converter K-map for B 0 : G 3 G 2 GG 3 2 GG 3 2 G 1 G 0 00 01 GG 1 0 GG 1 0 GG 1 0 GG 1 0 00 01 11 10 0 0 1 1 0 3 1 2 1 4 0 5 1 7 0 6 GG 3 2 GG 3 2 11 10 0 12 1 13 0 15 1 14 1 8 0 9 1 11 0 10 B0 G3G 2G1G 0 G3G 2G 1G 0 G3G 2G1G 0 G3G 2G1G 0 G3G 2G1G 0 G3G 2G 1G 0 G3G 2G1G 0 G3G 2G1G 0 B0 G3 G2 G1 G0 8/29/2017 70

Design of Gray to Binary Code Converter K-map for B 1 : G 3 G 2 GG 3 2 GG 3 2 G 1 G 0 00 01 GG 1 0 GG 1 0 GG 1 0 GG 1 0 00 01 11 10 0 0 0 1 1 3 1 2 1 4 1 5 0 7 0 6 GG 3 2 GG 3 2 11 10 0 12 0 13 1 15 1 14 1 8 1 9 0 11 0 10 B1 G3G 2G 1 G3G 2G1 G3G 2G1 G3G 2G1 B1 G3 G2 G1 8/29/2017 71

Design of Gray to Binary Code Converter K-map for B 2 : G 3 G 2 GG 3 2 GG 3 2 G 1 G 0 00 01 GG 1 0 GG 1 0 GG 1 0 GG 1 0 00 01 11 10 0 0 0 1 0 3 0 2 1 4 1 5 1 7 1 6 GG 3 2 GG 3 2 11 10 0 12 0 13 0 15 0 14 1 8 1 9 1 11 1 10 B G G G G 2 3 2 3 2 B G G 1 3 2 8/29/2017 72

Design of Gray to Binary Code Converter K-map for B 3 : G 3 G 2 GG 3 2 GG 3 2 G 1 G 0 00 01 GG 1 0 GG 1 0 GG 1 0 GG 1 0 00 01 11 10 0 0 0 1 0 3 0 2 0 4 0 5 0 7 0 6 GG 3 2 GG 3 2 11 10 1 12 1 13 1 15 1 14 1 8 1 9 1 11 1 10 B G 3 3 8/29/2017 73

Design of Gray to Binary Code Converter Logic Diagram: G 3 G 2 G 1 G 0 B3 B G G 2 3 2 B1 G1 G2 G3 B0 G0 G1 G2 G3 8/29/2017 74

Half Adder Half adder is a combinational logic circuit with two inputs and two outputs. It is a basic building block for addition of two single bit numbers. Inputs A B Half Adder Sum Carry Outputs 8/29/2017 75

Half Adder K-map for Sum Output: B B A B 0 1 0 1 A A 0 1 1 0 S AB AB S A B K-map for Carry Output: A A A B 0 1 B 0 0 0 C AB B 1 0 1 8/29/2017 77

Half Adder Logic Diagram: A B S A B C AB 8/29/2017 78

Half Adder Logic Diagram using Basic Gates: A B S A B C AB 8/29/2017 79

Full Adder Full adder is a combinational logic circuit with three inputs and two outputs. A Sum Inputs B Full Outputs Adder Carry Cin 8/29/2017 80

TRUTH TABLE

Full Adder K-map for Sum Output: A A BC BC BC BC BC A 00 01 11 10 0 1 0 1 0 1 1 0 1 0 S ABC ABC ABC ABC S ABC ABC ABC ABC S C( AB AB) C( AB AB) ABC ABC ABC ABC Let AB AB X S C( X ) C( X ) S C X Let X A B S C A B 8/29/2017 82

Full Adder K-map for Carry Output: A A BC BC BC BC BC A 00 01 11 10 0 1 0 0 1 0 0 1 1 1 C AB BC AC AC BC AB 8/29/2017 83

Full Adder Logic Diagram: A B C S A B C C AB BC AC 8/29/2017 84

Full Adder using Half Adders A B HA1 S 0 S 1 HA2 C 0 C 1 Sum C Carry 8/29/2017 85

Half Subtractor Half subtractor is a combinational logic circuit with two inputs and two outputs. It is a basic building block for subtraction of two single bit numbers. Inputs A B Half Subtractor Difference Borrow Outputs 8/29/2017 86

HALF SUBSTRACTOR

Half Subtractor K-map for Difference Output: B B A B 0 1 0 1 A A 0 1 1 0 D AB AB D A B K-map for Borrow Output: A A A B 0 1 B 0 0 1 B AB B 1 0 0 8/29/2017 88

Half Subtractor Logic Diagram: A B D A B B AB 8/29/2017 89

Half Subtractor Logic Diagram using Basic Gates: A B D A B B AB 8/29/2017 90

Full Subtractor Full subtractor is a combinational logic circuit with three inputs and two outputs. A Difference Inputs B Full Outputs Subtractor Borrow Bin 8/29/2017 91

FULL SUBSTRATOR

Full Subtractor K-map for Difference Output: A A BC BC BC BC BC A 00 01 11 10 0 1 0 1 0 1 1 0 1 0 D ABC ABC ABC ABC D ABC ABC ABC ABC D C( AB AB) C( AB AB) ABC ABC ABC ABC Let AB AB X D C( X ) C( X ) D C X Let X A B D C A B 8/29/2017 93

Full Subtractor K-map for Borrow Output: A A BC BC BC BC BC A 00 01 11 10 0 1 0 1 1 1 0 0 1 0 B0 AB BC AC AC BC AB 8/29/2017 94

Full Subtractor Logic Diagram: A B C D A B C B0 AB BC AC 8/29/2017 95

Full Subtractor using Half Subtractor A B HS1 D 0 D 1 HS2 B 0 B 1 Difference C Borrow 8/29/2017 96

Seven Segment Display a f e g b c d dp 8/29/2017 98

Seven Segment Display Segments a b c d e f g Display Number Seven Segment Display ON ON ON ON ON ON OFF 0 OFF ON ON OFF OFF OFF OFF 1 ON ON OFF ON ON OFF ON 2 ON ON ON ON OFF OFF ON 3 OFF ON ON OFF OFF ON ON 4 ON OFF ON ON OFF ON ON 5 ON OFF ON ON ON ON ON 6 ON ON ON OFF OFF OFF OFF 7 ON ON ON ON ON ON ON 8 ON ON ON ON OFF ON ON 9 8/29/2017 Amit Nevase 99

Types of Seven Segment Display Common Cathode Display Common Anode Display 8/29/2017 100

Common Anode Display +Vcc R R R R R R R R a b c d e f g dp 8/29/2017 101

Common Anode Display +Vcc BCD Input BCD to 7 Segment Decoder a b c d e f g R R R R R R R R 8/29/2017 102 dp

Common Cathode Display a b c d e f g dp R R R R R R R R 8/29/2017 103

R R R R R R R R Common Cathode Display a b c BCD Input BCD to 7 Segment Decoder d e f g 8/29/2017 104 dp

BCD to 7 Segment Decoder Driver ICs Sr. No. IC Number Specifications 1 IC 7446, IC 74246 Active Low open collector outputs, maximum voltage 30 V, maximum current sinking capability 40mA 2 IC 7447, IC 74247 Active Low open collector outputs, maximum voltage 15 V, maximum current sinking capability 40mA 3 IC 7448, IC 74248 Active High open collector outputs, Pull up resistor 2kohm, maximum voltage 5.5 V, maximum current sinking capability 6.4mA 8/29/2017 105

IC 7447 Pins A,B,C,D Description BCD Inputs a to g LT RBI BI Active Low Outputs Lamp Test Ripple Blanking Input Blanking Input RBO Ripple Blanking output 8/29/2017 106

RBI - Ripple Blanking Input For the normal decoding operation, this input should be connected to logic 1. If RBI is connected to ground, then it switches off the display when BCD inputs corresponding to 0. For non-zero BCD inputs, the decoder output will be normal and the BCD number will be displayed. RBI=0 is connected for blanking out the 8/29/2017 107 leading zeros in multidigit displays.

BI Blanking Input If BI is connected to 0, then the display will be switched off irrespective of the BCD input. This feature is used in the multiplexed display in order to save power. In the non-multiplexed displays this input is permanently connected to Vcc 8/29/2017 108

RBO Ripple Blanking Output This output is normally at logic 1. But it goes to logic 0 during the zero blanking interval when RBI is forced to a low level. RBO is used for cascading purpose and it is connected to RBI of the next stage. 8/29/2017 109

LT - Lamp Test This pin can be used to check whether all the segments of the display are working properly or not. If LT is forced low with RBO at logic 1 or open, then all the output terminals will be forced to their active state 8/29/2017 110

Circuit Diagram 8/29/2017 111 a b c d e f g dp R R R R R R R 1 2 6 7 3 5 4 13 12 11 10 9 15 14 16 8 BCD Inputs LSB MSB IC 7447 a b c d e f g dp LT RBI / BI RBO Vcc Gnd A0 A1 A2 A3 5V a b c d e f g Common

Display Configuration LTS 542 Common g f a b f e a g b c d dp e d c dp Common 8/29/2017 112

Display Configuration 8/29/2017 113

N Bit Parallel Adder The full adder is capable of adding two single digit binary numbers along with a carry input. But in practice we need to add binary numbers which are much longer than one bit. To add two n-bit binary numbers we need to use the n-bit parallel adder. It uses a number of full adders in cascade. The carry output of the previous full adder is connected to the carry input of the next full adder.. 8/29/2017 115

N Bit Parallel Adder A1 An 1 Bn 1 A2 B2 B1 A0 B0 FA-(n-1) FA-2 FA-1 FA-0 0 Cin Sn 1 S 2 S1 S 0 8/29/2017 116

4 Bit Parallel Adder using full adder A1 A3 B3 A2 B2 B1 A0 0 B C 0 FA-3 FA-2 FA-1 FA-0 Cin S 3 S 2 S1 S 0 8/29/2017 117

IC 7483 4 Bit Binary Parallel Adder A1 A3 B3 A2 B2 B1 A0 0 B C 0 FA-3 FA-2 FA-1 FA-0 Cin S 3 S 2 S1 S 0 8/29/2017 118

IC 7483 4 Bit Binary Parallel Adder A Binary number B Binary number A3 A2 A1 A0 B3 B2 B1 0 B C 0 Carry Output IC 7483 Cin Carry Input S 3 S 2 S1 S 0 Sum Output 8/29/2017 119

Cascading of IC 7483 If we want to add two 8 bit binary numbers using 4 bit binary parallel adder IC 7483, then we have to cascade the two ICs in following way Higher nibble of Higher nibble of A Binary number B Binary number A7 A6 A5 A4 B7 B6 B5 4 B Lower nibble of Lower nibble of A Binary number B Binary number A3 A2 A1 A0 B3 B2 B1 0 B C 0 IC 7483-II Cin C 0 IC 7483-I Cin Carry Carry Output Input S 7 S 6 S 5 S 4 S 3 S 2 S1 S 0 Sum Output 8/29/2017 120

Design of 1 Digit BCD Adder Block Diagram: A BCD no. B BCD no. C 0 IC 7483-I S 3 S 2 S1 S 0 Cin Logic Circuit Add 0110 Command C 0 IC 7483-II Cin S S 2 1 8/29/2017 3 S S 0 121

Design of 1 Digit BCD Adder As we know BCD addition rules, we understand that the 4 bit BCD adder should consists of following: A 4 bit binary adder to add the given two (4 bit numbers). A combinational logic circuit to check if sum is greater than 9 or carry 1. One more 4 bit binary adder to add 0110 to the invalid BCD sum or if carry is 1 8/29/2017 122

Design of 1 Digit BCD Adder Logic Table for design of Logic circuit: Inputs Y Inputs Y S 3 S 2 S 1 S 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 S 3 S 2 S 1 S 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 Sum is invalid 0 1 0 1 0 1 1 0 1 1 BCD 0 1 1 0 0 1 1 1 0 1 Number 0 1 1 1 0 1 1 1 1 1 8/29/2017 Amit Nevase 123 Y=1

Design of 1 Digit BCD Adder K-map for Logic circuit: S 3 s 2 SS 3 2 S 1 S 0 00 SS 1 0 SS 1 0 SS 1 0 SS 1 0 00 01 11 10 0 0 0 1 0 3 0 2 SS 3 2 01 0 4 0 5 0 7 0 6 SS 3 2 11 1 12 1 13 1 15 1 14 Y S 3S 2 S 3S1 SS 3 2 10 0 8 0 9 1 11 1 10 SS 3 2 SS 1 3 8/29/2017 124

4-BIT BCD ADDER

4 Bit Binary Parallel Subtractor using IC 7483 A Binary number B Binary number A3 A2 A1 A0 B3 B2 B1 0 B NOT gates for 1 s complement of B Vcc 5V C 0 Carry S 3 S 2 IC 7483 Output S1 It adds 1 to 1 s S 0 Cin 1 complement of B Difference Output 8/29/2017 127

IC 7483 as Parallel Adder/Subtractor B Binary number A Binary number A3 A2 A1 A0 B3 B2 B1 B0 M Mode Select C 0 Carry IC 7483 Cin Output S 3 S 2 S1 S 0 Sum or Difference Output Mode Select M=0 Addition M=1 Subtraction 8/29/2017 128

IC comparators provide outputs to indicate which of the numbers is larger or if they are equal. The bits are numbered starting at 0, rather than 1 as in the case of adders. Comparators Cascading inputs Cascading inputs are provided to expand the comparator to larger numbers. A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 COMP 0 A 3 A > B A > B A = B A = B A < B A < B 0 A 3 Outputs The IC shown is the 4-bit 74HC85/74LS85.

74LS85 (4 bit magnitude comparator) The 74LS85 compares two unsigned 4-bit binary numbers, the unsigned numbers are A 3, A 2, A 1, A 0 and B 3, B 2, B 1, B 0. Cascading Inputs Outputs 130

Comparators Use 74HC85 comparators to compare the magnitudes of two 8-bit numbers. Show the comparators with proper interconnections. A=A7A6A5A4A3A2A1A0 and B=B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 IC comparators can be expanded using the cascading inputs as shown. The lowest order comparator has a HIGH on the A = B input. +5.0 V LSBs A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 COMP 0 A 3 A > B A > B A = B A = B A < B A < B 0 A 3 MSBs A 4 A 5 A 6 A 7 B 4 B 5 B 6 B 7 COMP 0 A 3 A > B A > B A = B A = B A < B A < B 0 A 3 Outputs

IC 74181 Arithmetic Logic Unit A very popular & widely used combinational circuit is ALU which is capable of performing arithmetic as well as logical operation. Arithmetic Operating Modes: Addition Subtraction Shift Operation Magnitude Comparison 12 other arithmetic operations 8/29/2017 133

IC 74181 Logical Function Modes: Exclusive OR Comparator AND, NAND, OR, NOR 10 other arithmetic operations 8/29/2017 134

IC 74181 Pin Diagram 8/29/2017 135

IC 74181 Function Table 8/29/2017 136

IC 74381 4 Bit Arithmetic Logic Unit Features: Low input loading minimizes drive requirements Performs six arithmetic and logic functions Selectable LOW (clear) and HIGH (preset) functions Carry generate and propagate outputs for use with carry look ahead generator 8/29/2017 137

IC 74381 Pin Configuration 8/29/2017 138

IC 74381 Function Table 8/29/2017 139

Combinational Logic Circuits Necessity, Applications and Realization of following Multiplexers (MUX): MUX Tree Demultiplexers (DEMUX): DEMUX Tree, DEMUX as Decoder Study of IC 74151, IC 74155 Priority Encoder 8:3, Decimal to BCD Encoder Tristate Logic, Unidirectional & Bidirectional buffer ICs: IC 74244 and IC 74245 8/29/2017 140

Multiplexers Multiplexer is a circuit which has a number of inputs but only one output. Multiplexer is a circuit which transmits large number of information signals over a single line. Multiplexer is also known as Data Selector or MUX. 8/29/2017 141

Necessity of Multiplexers In most of the electronic systems, the digital data is available on more than one lines. It is necessary to route this data over a single line. Under such circumstances we require a circuit which select one of the many inputs at a time. This circuit is nothing but a multiplexer. Which has many inputs, one output and some select lines. Multiplexer improves the reliability of the digital system because it reduces the number 8/29/2017 142

Advantages of Multiplexers It reduces the number of wires. So it reduces the circuit complexity and cost. We can implement many combinational circuits using Mux. It simplifies the logic design. It does not need the k-map and simplification. 8/29/2017 143

Applications of Multiplexers It is used as a data selector to select one out of many data inputs. It is used for simplification of logic design. It is used in data acquisition system. In designing the combinational circuits. In D to A converters. To minimize the number of connections. 8/29/2017 144

Block Diagram of Multiplexer D 0 D 0 Data Inputs D 1 D 2 D 3... n:1 Mux Y Output D 1 D 2 D 3... Output D n-1 E Enable Input...... D n-1...... S m-1 S 2 S 1 s 0 S m-1 S 2 S 1 s 0 Select Lines Fig. General Block Diagram Fig. Equivalent Circuit 8/29/2017 145

Relation between Data Input Lines & Select Lines In general multiplexer contains, n data lines, one output line and m select lines. To select n inputs we need m select lines such that 2 m =n. 8/29/2017 146

Types of Multiplexers 2:1 Multiplexer 4:1 Multiplexer 8:1 Multiplexer 16:1 Multiplexer 32:1 Multiplexer 64:1 Multiplexer and so on 8/29/2017 147

2:1 Multiplexer Data Inputs D 0 D 1 E 2:1 Mux Y Output Block Diagram Enable Input s Select Lines Enable i/p (E) Select i/p (S) Output (Y) 0 X 0 Truth Table 1 0 D 0 1 1 D 1 8/29/2017 148

Realization of 2:1 Mux using gates S D 1 D 0 S SD0 Y Output SD1 E Enable Input 8/29/2017 149

4:1 MULTIPLEXER

Realization of 4:1 Mux using gates S 1 S 0 S1S 0D0 D 0 S1S 0D1 D 1 D 2 S1S 0D2 Y Output D 3 S1S 0D3 E Enable Input 8/29/2017 151

16:1 Multiplexer D 0 D 1 D 2 D 3 Data Inputs D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 16:1 Mux Y Output Block Diagram E Enable Input S 3 S 2 S 1 S 0 8/29/2017 152 Select Lines

Mux Tree The multiplexers having more number of inputs can be obtained by cascading two or more multiplexers with less number of inputs. This is called as Multiplexer Tree. For example, 32:1 mux can be realized using two 16:1 mux and one 2:1 mux. 8/29/2017 153

8:1 Multiplexer using 4:1 Multiplexer D 0 D 1 D 2 D 3 4:1 Mux Y 1 Select S 2 E S 1 S 0 Y Lines S 1 S 0 S 1 S 0 Output D 4 D 5 D 6 D 7 4:1 Mux Y 2 E 8/29/2017 154

8:1 Multiplexer using 4:1 Multiplexer D 0 D 1 D 2 D 3 4:1 Mux Y 1 S 1 S 0 E S 1 S 1 S 0 S 0 D 0 D 1 E 2:1 Mux Y Output D 4 D 5 4:1 S 2 D 6 Mux Y 2 D 7 E 8/29/2017 155

D 0 D 1 D 2 D 3 S 1 4:1 Mux S 0 Y 1 16:1 Mux using 4:1 Mux S 1 S 0 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 S 1 S 1 4:1 Mux 4:1 Mux S 0 S 0 Y 2 Y 3 D 0 D 1 D 2 D 3 S 1 S 3 4:1 Mux S 0 S 2 Y Output D 12 S 1 S 0 D 4:1 13 Y 4 D 14 Mux 8/29/2017 D 15 156

Realization of Boolean expression using Mux We can implement any Boolean expression using Multiplexers. It reduces circuit complexity. It does not require any simplification 8/29/2017 157

Example 1 Implement following Boolean expression using multiplexer f ( A, B, C) m(0,3,5,6) Since there are three variables, therefore a multiplexer with three select input is required i.e. 8:1 multiplexer is required The 8:1 multiplexer is configured as below to implement given Boolean expression 8/29/2017 158

Example 1 continue.. +V cc f ( A, B, C) m(0,3,5,6) D 0 D 1 D 2 D 3 D 4 D 5 8:1 Mux Y Output D 6 D 7 E S 2 S 1 S 0 A B C 8/29/2017 159

Example 2 Implement following Boolean expression using multiplexer f ( A, B, C, D) m(0,2,3,6,8,9,12,14) Since there are four variables, therefore a multiplexer with four select input is required i.e. 16:1 multiplexer is required The 16:1 multiplexer is configured as below to implement given Boolean expression 8/29/2017 160

Example 2 continue.. +V cc f ( A, B, C, D) m(0,2,3,6,8,9,12,14) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 D 12 D 13 D 14 D 15 16:1 Mux Y Output E S 3 S 2 S 1 S 0 A B C 8/29/2017 161 D

De-multiplexer A de-multiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it over several outputs. At a time only one output line is selected by the select lines and the input is transmitted to the selected output line. It has only one input line, n number of output lines and m number of select lines. 8/29/2017 163

Block Diagram of De-multiplexer Y 0 Y 0 Y 1 Y 1 Data Input 1:n De-mux... Y 2 Y 3 Outputs Data Input... Y 2 Y 3 Outputs. Y n-1. Y n-1 E.. Enable Input........ S m-1 S 2 S 1 s 0 S m-1 S 2 S 1 s 0 Select Lines Fig. General Block Diagram Fig. Equivalent Circuit 8/29/2017 164

Relation between Data Output Lines & Select Lines In general de-multiplexer contains, n output lines, one input line and m select lines. To select n outputs we need m select lines such that n=2 m. 8/29/2017 165

Types of De-multiplexers 1:2 De-multiplexer 1:4 De-multiplexer 1:8 De-multiplexer 1:16 De-multiplexer 1:32 De-multiplexer 1:64 De-multiplexer and so on 8/29/2017 166

1:2 De-mux

1:2 De-mux using basic gates E D in S S Y 0 Y 1 8/29/2017 168

1:4 De-mux

1:4 De-mux using basic gates E D in S1 S 0 S1 S 0 Y 0 Y 1 Y 2 Y 3 8/29/2017 170

1: 8 De-multiplexer Data D in Input E Enable Input 1:8 De-mux S 2 S 1 S 0 Select Lines Block Diagram Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 8/29/2017 171

1: 16 De-multiplexer Block Diagram Data Input E D in Enable Input 1:16 De-mux 8/29/2017 S S 172 3 S 2 S 1 0 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Y 8 Y 9 Y 10 Y 11 Y 12 Y 13 Y 14 Y 15

De-mux Tree Similar to multiplexer we can construct the de-multiplexer with more number of lines using de-multiplexer having less number of lines. This is call as De-mux Tree. 8/29/2017 173

1:4 De-mux using 1:2 De-mux Data Input Select S 1 D in E 1:2 De-mux S 0 Y 0 Y 1 Y 0 Y 1 Lines S 0 D in E S 0 1:2 De-mux Y 0 Y 1 Y 2 Y 3 8/29/2017 174

1:16 De-mux using 1:4 De-mux D in S 1 1:4 De-mux S 0 Y 0 Y 1 Y 2 Y 3 Data Input D in 1:4 De-mux S 1 S 0 Y 0 Y 1 Y 2 Y 3 D in S 1 S 0 1:4 De-mux Y 4 Y 5 Y 6 Y 7 S 3 S 2 D in S 1 1:4 De-mux S 0 Y 8 Y 9 Y 10 Y 11 D in Y 14 S 1 S 0 8/29/2017 De-mux Y 15 175 S 1 1:4 S 0 Y 12 Y 13

Decoder Decoder is a combinational circuit. It converts n bit binary information at its input into a maximum of 2 n output lines. For example, if n=2 then we can design upto 2:4 decoder 8/29/2017 176

De-multiplexer as Decoder It is possible to operate a de-multiplexer as a decoder. Let us consider an example of 1:4 de-mux can be used as 2:4 decoder 8/29/2017 177

1:4 De-multiplexer as 2:4 Decoder V cc Data Input E D in 1:4 De-mux Y 0 Y 1 Y 2 Y 3 Inputs A B S 1 S 0 D in 1:4 De-mux Y 0 Y 1 Y 2 Y 3 Enable Input S 1 S 0 Select Lines E Enable Input 1: 4 De-multiplexer 1: 4 De-multiplexer as 2:4 Decoder 8/29/2017 178

Realization of Boolean expression using De-mux We can implement any Boolean expression using de-multiplexers. It reduces circuit complexity. It does not require any simplification 8/29/2017 179

Example 1 Implement following Boolean expression using de-multiplexer f ( A, B, C) m(0,3,5,6) Since there are three variables, therefore a de-multiplexer with three select input is required i.e. 1:8 de-multiplexer is required The 1:8 de-multiplexer is configured as below to implement given Boolean expression 8/29/2017 180

Example 1 continue.. f ( A, B, C) m(0,3,5,6) +V cc Y 0 Data Input E Enable Input D in S 2 1:8 De-mux S 1 S 0 A B C Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Y 8/29/2017 181

Example 2 Implement following Boolean expression using de-multiplexer f ( A, B, C, D) m(0,2,3,6,8,9,12,14) Since there are four variables, therefore a demultiplexer with four select input is required i.e. 1:16 de-multiplexer is required The 1:16 de-multiplexer is configured as below to implement given Boolean expression 8/29/2017 182

Example 2 continue.. Data E +V cc Input D in Enable Input 1:16 De-mux S 3 S 2 A B C S 1 D Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Y 8 Y 9 Y 10 Y 11 Y 12 Y 13 Y 14 SY 0 15 f ( A, B, C, D) m(0,2,3,6,8,9,12,14) 8/29/2017 183 Y

Module III Combinational Logic Circuits Necessity, Applications and Realization of following (8 Marks) Multiplexers (MUX): MUX Tree Demultiplexers (DEMUX): DEMUX Tree, DEMUX as Decoder Study of IC 74151, IC 74155 Priority Encoder 8:3, Decimal to BCD Encoder Tristate Logic, Unidirectional & Bidirectional buffer ICs: IC 74244 and IC 74245 8/29/2017 184

Multiplexer ICs IC Number Description Output IC 74157 Quad 2:1 Mux Same as input IC 74158 Quad 2:1 Mux Inverted Output IC 74153 Dual 4:1 Mux Same as input IC 74352 Dual 4:1 Mux Inverted Output IC 74151 8:1 Mux Inverted Output IC 74152 8:1 Mux Inverted Output IC 74150 16:1 Mux Inverted Output 8/29/2017 185

IC 74151 General Description This Data Selector/Multiplexer contains full on-chip decoding to select one-of-eight data sources as a result of a unique three-bit binary code at the Select inputs. Two complementary outputs provide both inverting and non-inverting buffer operation. Y A Strobe input is provided which, when at the high level, disables all data inputs and forces the Y output to the low state and the output to the high state. 8/29/2017 186

IC 74151 - Features Advanced oxide-isolated, ion-implanted Schottky TTL process Switching performance is guaranteed over full temperature and VCC supply range Pin and functional compatible with LS family counterpart Improved output transient handling capability 8/29/2017 187

IC 74151 Pin Diagram V CC G ND D 0 D 1 D 2 Y Data Inputs D 3 D 4 D 5 8:1 Mux Y D 6 D 7 Pin Diagram E Enable Input Select Lines 8/29/2017 188 Equivalent Diagram S 2 S 1 S 0

De-multiplexer ICs IC Number Description IC 74138 1:8 De-multiplexer IC 74139 Dual 1:4 De-multiplexer IC 74154 1:16 De-multiplexer IC 74155 Dual 1:4 De-multiplexer 8/29/2017 189

IC 74155 General Description These monolithic TTL circuits feature dual 1 line to 4 line de-multiplexers with individual strobes and common binary address inputs in a single 16 pin package. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. 8/29/2017 190

8/29/2017 1 to 8 line de-multiplexer 191 IC 74155 - Features Input clamping diodes simplify system design. Choice of outputs : Totem pole ( LS155A) or open collector ( LS156). Individual strobes simplify cascading for decoding or de-multiplexing larger words. Applications: Dual 2 to 4 Line Decoder Dual 1: 4 De-multiplexer 3 to 8 line Decoder

IC 7155 Pin Diagram 8/29/2017 192

Combinational Logic Circuits Necessity, Applications and Realization of following (8 Marks) Multiplexers (MUX): MUX Tree Demultiplexers (DEMUX): DEMUX Tree, DEMUX as Decoder Study of IC 74151, IC 74155 Priority Encoder 8:3, Decimal to BCD Encoder Tristate Logic, Unidirectional & Bidirectional buffer ICs: IC 74244 and IC 74245 8/29/2017 193

Encoder Encoder is a combinational circuit which is designed to perform the inverse operation of decoder. An encoder has n number of input lines and m number of output lines. An encoder produces an m bit binary code corresponding to the digital input number. The encoder accepts an n input digital word and converts it into m bit another digital word 8/29/2017 194

Encoder n inputs.. Encoder.. m outputs.. 8/29/2017 195

Types of Encoders Priority Encoder Decimal to BCD Encoder Octal to BCD Encoder Hexadecimal to Binary Encoder 8/29/2017 196

Priority Encoder This is a special type of encoder. Priorities are given to the input lines. If two or more input lines are 1 at the same time, then the input line with highest priority will be considered. 8/29/2017 197

Priority Encoder 8:3 Highest Priority 8 inputs D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Priority Encoder 8:3 Y 2 Y 1 Y 0 3 outputs Lowest Priority 8/29/2017 198

Decimal to BCD Encoder 9 inputs D 1 D 2 D 3 D 4 D 5 D 6 D 7 Decimal to BCD Encoder A B C D BCD outputs D 8 D 9 8/29/2017 200

Tristate Logic In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. 8/29/2017 202

Digital Buffer Sometimes in digital electronic circuits we need to isolate logic gates from each other or have them drive or switch higher than normal loads, such as relays, solenoids and lamps without the need for inversion. One type of single input logic gate that allows us to do just that is called the Digital Buffer. 8/29/2017 203

Digital Buffer Unlike the single input, single output inverter or NOT gate such as the TTL 7404 which inverts or complements its input signal on the output, the Buffer performs no inversion or decision making capabilities (like logic gates with two or more inputs) but instead produces an output which exactly matches that of its input. In other words, a digital buffer does nothing as its output state equals its input state. Then digital buffers can be regarded as Idempotent gates applying Boole s Idempotent Law because when an input passes through this device its value is not changed. So the digital buffer is a non-inverting device and will therefore give us the Boolean expression of: Q = A. 8/29/2017 204

Tri-state Buffer As well as the standard Digital Buffer seen above, there is another type of digital buffer circuit whose output can be electronically disconnected from its output circuitry when required. This type of Buffer is known as a 3-State Buffer or more commonly a Tri-state Buffer. A Tri-state Buffer can be thought of as an input controlled switch with an output that can be electronically turned ON or OFF by means of an external Control or Enable ( EN ) signal input. This control signal can be either a logic 0 or a logic 1 type signal resulting in the Tri-state Buffer being in one state allowing its output to operate normally producing the required output or in another state were its output is blocked or disconnected. 8/29/2017 205

Tri-state Buffer - Equivalent 8/29/2017 206

What is Parity Generator? A Parity Generator is a Combinational Logic Circuit that Generates the Parity bit in the Transmitter. A Parity bit is used for the Purpose of Detecting Errors during Transmissions of binary Information. It is an Extra bit Included with a binary Message to Make the Number of 1 s either Odd or Even.

Two Types of Parity In Even Parity, the added Parity bit will Make the Total Number of 1 s an Even Amount. In Odd Parity, the added Parity bit will Make the Total Number of 1 s an Odd Amount.

Parity Generator Truth Table and Logic Diagram 3-bit Message Odd X Y Z Parity Bit Even Parity Bit 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1

Boolean Expression K-Map Simplification Even Pair P =XYZ + XYZ + XYZ + XYZ X YZ 00 01 11 10 0 1 0 1 =X YZ + YZ + X YZ + YZ =X Y Z + X Y Z =X (Y Z) Odd Pair P =XYZ + XYZ + XYZ + XYZ =X YZ + YZ + X YZ + YZ =X Y Z + X Y Z =X (Y Z) YZ X 0 1 1 0 1 0 00 01 11 10 1 0 1 0 0 1 0 1

Parity Checker A Circuit that Checks the Parity in the Receiver is called Parity Checker. The Parity Checker Circuit Checks for Possible Errors in the Transmission. Since the Information Transmitted with Even Parity, the Received must have an even number of 1 s.if it has odd number of 1 s, it indicates that there is a Error occurred during Transmission. The Output of the Parity Checker is denoted by PEC(Parity Error Checker).If there is error, that is,if it has odd number of 1 s, it will indicate 1.If no then PEC will indicate 0.

Even Parity Checker Truth Table Decimal Equivalent Four Bits Received Parity Error P A B C PEC 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 0 4 0 1 0 0 1 5 0 1 0 1 0 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 0 10 1 0 1 0 0 11 1 0 1 1 1 12 1 1 0 0 0 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 0

Logic Diagram K-Map Simplification PA 00 01 11 10 BC 00 01 11 10 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 Boolean Expression PEC = PA BC + BC + PA BC + BC + PA BC + BC + PA (BC + BC) =PA B C + PA B C + PA B C + PA B C =(PA + PA) B C + PA + PA B C =(P A) B C + P A B C =(P A) (B C)

Bi-directional Buffer It is also possible to connect Tri-state Buffers back-to-back to produce what is called a Bi-directional Buffer circuit with one active-high buffer connected in parallel but in reverse with one active-low buffer. Here, the enable control input acts more like a directional control signal causing the data to be both read from and transmitted to the same data bus wire. In this type of application a tri-state buffer with bi-directional switching capability such as the TTL 74245 can be used. 8/29/2017 214

References Digital Principles by Malvino Leach Modern Digital Electronics by R.P. Jain Digital Electronics, Principles and Integrated Circuits by Anil K. Maini Digital Techniques by A. Anand Kumar 8/29/2017 215

Online Tutorials http://nptel.ac.in/video. php?subjectid=1171060 86 http://www.electronicstutorials.ws/combinatio n/comb_1.html http://www.electronicstutorials.ws/combinatio n/comb_2.html 8/29/2017 Amit Nevase 216

Thank You 8/29/2017 217