Building a Computer I wonder where this goes? B LU MIPS Kit Quiz # on /3, open book and notes (This is the last lecture covered) Comp 4 Fall 7 /4/7 L6- Building a Computer
THIS IS IT! Motivating Force or Inciting Incident This is the point in the course where the PLOT actually begins. We are now ready to build a computer. The ingredients are all in place, now it is time to build a legitimate computer. One that executes instructions, much the way any other desktop, P, or other computer does. Comp 4 Fall 7 /4/7 L6- Building a Computer
The MIPS IS OP 6 5 5 5 5 6 6 6 r s r t r d shamt func R-type: LU with Reguster operands Reg[rd] Reg[rs] op Reg[rt] r s r t immediate I-type: LU with constant operand Reg[rt] Reg[rs] op (immediate) r s r t immediate I-type: Load and Store Reg[rt] Mem[Reg[rs] + (immediate)] Mem[Reg[rs] + (immediate)] Reg[rt] r s r t immediate I-type: Branch s if (Reg[rs] == Reg[rt]) + 4 + 4*(immediate) if (Reg[rs]!= Reg[rt]) + 4 + 4*(immediate) 6-bit constant J-type: jump ( & xf) 4*(immediate) Comp 4 Fall 7 /4/7 The MIPS instruction set as seen from a Hardware Perspective classes classes distinguished distinguished by by types: types: ) ) 3-operand 3-operand LU LU ) ) LU LU w/immediate w/immediate 3) 3) Loads/Stores Loads/Stores 4) 4) Branches Branches 5) 5) Jumps Jumps L6- Building a Computer 3
esign pproach Incremental Featurism Each instruction class can be implemented using a simple component repertoire. We ll try implementing data paths for each class individually, and merge them (using MUes, etc). Steps:. 3-Operand LU instructions. LU w/immediate instructions. Load & Store s 3. Jump & Branch instructions 4. Exceptions 5. Merge data paths Our Bag of Components: s Muxes B LU LU & adders + R R W W (3-port) R R Memories W R R/W ata Comp 4 Fall 7 /4/7 L6- Building a Computer 4
Few LU Tweaks Let s review the LU that we built a few lectures ago. (With a few minor additions) B Sub Bool Shft Math dd/sub Bidirectional Barrel Shifter Boolean 5-bit Sub Bool Shft Math OP +B -B B<< B>> B>>> & B B ^ B B Flags V,C N Flag Comp 4 Fall 7 /4/7 R Flag L6- Building a Computer 5
Fetch/ecode Use a counter to FETCH the next instruction: PROGRM COUNTER () + 3 Can be built with half-adders OP[3:6], FUNC[5:] INSTRUCTION WOR FIELS CONTROL SIGNLS use as memory address add 4 to, load new value at end of cycle fetch instruction from memory º use some instruction fields directly (register numbers, 6-bit constant) º use bits <3:6> and <5:> to generate controls Comp 4 Fall 7 /4/7 L6- Building a Computer 6
3-Operand LU ata Path r s r t r d R-type: LU with Reguster operands Reg[rd] Reg[rs] op Reg[rt] Rs: <5:> Rt: <:6> Rd: <5:> R R W W R R B LU! Comp 4 Fall 7 /4/7 L6- Building a Computer 7
Shift s r s r t r d shamt R-type: LU with Reguster operands sll: Reg[rd] Reg[rt] (shift) shamt sllv: Reg[rd] Reg[rt] (shift) Reg[rs] Rs: <5:> Rt: <:6> Rd: <5:> R R W W R R shamt:<:6> SEL SEL! B LU SEL Comp 4 Fall 7 /4/7 L6- Building a Computer 8
LU with Immediate r s r t immediate I-type: LU with constant operand Reg[rt] Reg[rs] op (immediate) Rs: <5:> Rt: <:6> Rd:<5:> Rt:<:6> R R W W W R R imm: <5:> shamt:<:6> SEL! SEL B LU... 5 4 3 3 3 3 7 6 5 4 3 3 Comp 4 Fall 7 /4/7 L6- Building a Computer 9
Load r s r t immediate I-type: Load Reg[rt] Mem[Reg[rs] + (immediate)] Rs: <5:> Rt: <:6> Rd:<5:> Rt:<:6> R R W W W R R Imm: <5:> shamt:<:6> SEL SEL B LU W R/W ata dr R Comp 4 Fall 7 /4/7 L6- Building a Computer
Store r s r t immediate I-type: Store Mem[Reg[rs] + (immediate)] Reg[rt] Rs: <5:> Rt: <:6> Rd:<5:> Rt:<:6> R R W W W R R Imm: <5:> shamt:<:6> SEL B LU W R/W ata dr R No! SEL Comp 4 Fall 7 /4/7 L6- Building a Computer
JMP s <3:9>:J<5:>: SEL 6 5 4 3 6-bit constant J-type: j: ( & xf) 4*(immediate) jal: ( & xf) 4*(immediate); Reg[3] + 4 J:<5:> Rd:<5:> Rt:<:6> 3 7 WSEL 3 Rs: <5:> R R W W W R R Rt: <:6> Imm: <5:> shamt:<:6> SEL SEL WSEL SEL B LU W R/W ata dr R Comp 4 Fall 7 /4/7 L6- Building a Computer
BEQ/BNE s <3:9>:J<5:>: BT SEL 6 5 4 3 That x4 unit is trivial. I ll just wire the input shifted over bit positions. J:<5:> r s r t immediate R-type: Branch s if (Reg[rs] == Reg[rt]) + 4 + 4*(immediate) Rd:<5:> Rt:<:6> 3 7 if (Reg[rs]!= Reg[rt]) + 4 + 4*(immediate) WSEL 3 Rs: <5:> R R W W W R R Rt: <:6> Imm: <5:> Why add, another adder? Couldn t we reuse the one in the LU? Nope, it needs to do a subtraction. SEL WSEL SEL x4 + BT B LU shamt:<:6> SEL W R/W ata dr R Comp 4 Fall 7 /4/7 L6- Building a Computer 3
Jump Indirect s <3:9>:J<5:>: JT BT SEL 6 5 4 3 r s r t r d R-type: Jump Indirect, Jump and Link Indirect jr: Reg[rs] jalr: Reg[rs], Reg[rd] + 4 J:<5:> Rd:<5:> Rt:<:6> 3 7 WSEL 3 Rs: <5:> R R W W W R R Rt: <:6> Imm: <5:> JT SEL WSEL SEL x4 + BT B LU shamt:<:6> SEL W R/W ata dr R Comp 4 Fall 7 /4/7 L6- Building a Computer 4
Loose Ends <3:9>:J<5:>: JT BT SEL 6 5 4 3 r s r t immediate I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < (imm)) Reg[rt] ; else Reg[rt] sltiu: if (Reg[rs] < (imm)) Reg[rt] ; else Reg[rt] N V J:<5:> C Rd:<5:> Rt:<:6> 3 7 Imm: <5:> WSEL 3 JT Rs: <5:> R R W W W R R Rt: <:6> Reminder: To evaluate ( < B) we first compute -B and look at the flags. SEL WSEL SEL x4 + BT B LU NV shamt:<:6> C SEL W R/W ata dr R LT = N V LTU = C Comp 4 Fall 7 /4/7 L6- Building a Computer 5
More Loose Ends <3:9>:J<5:>: JT BT SEL 6 5 4 3 r s r t r d R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd] ; else Reg[rd] sltu: if (Reg[rs] < Reg[rt]) Reg[rd] ; else Reg[rd] J:<5:> Rd:<5:> Rt:<:6> 3 7 WSEL 3 Rs: <5:> R R W W W R R Rt: <:6> Imm: <5:> JT N V C SEL WSEL SEL x4 + BT B LU N V C shamt:<:6> SEL W R/W ata dr R Comp 4 Fall 7 /4/7 L6- Building a Computer 6
LUI Ends <3:9>:J<5:>: JT BT SEL 6 5 4 3 r t immediate I-type: Load upper immediate lui: Reg[rt] Immediate << 6 J:<5:> Rd:<5:> Rt:<:6> 3 7 WSEL 3 Rs: <5:> R R W W W R R Rt: <:6> Imm: <5:> JT N V C SEL WSEL SEL x4 + BT shamt:<:6> B LU N V C 6 SEL W R/W ata dr R Comp 4 Fall 7 /4/7 L6- Building a Computer 7
Reset, Interrupts, and Exceptions FIRST, we need some way to get our machine into a known initial state. This doesn t mean that all registers will be initialized, just that we ll know where to fetch the first instruction. We ll call this control input, RESET We d also like RECOVERBLE INTERRUPTS for FULTS (eg, Illegal ) - CPU or SYSTEM generated [synchronous] TRPS & system calls (eg, read-a-character) - CPU generated [synchronous] (Implemented as an agreed upon Illegal instruction) I/O events (eg, key struck) - externally generated [asynchronous] ECEPTION GOL: Interrupt running program, invoke exception handler, return to continue execution. These are Software notions of synchrony and asynchrony. Comp 4 Fall 7 /4/7 L6- Building a Computer 8
Exceptions x8 x84 x88 <3:9>:J<5:>: JT BT SEL 6 5 4 3 Reset: x8 Bad Opcode: Reg[7] ; x84 IRQ: Reg[7] ; x88 These inputs should probably be registered a few times to avoid metastability problems RESET IRQ J:<5:> N V C SEL WSEL SEL LSEL Rd:<5:> Rt:<:6> Imm: <5:> 3 7 x4 + BT WSEL 3 JT R R W W W R R B LU N V C Rs: <5:> shamt:<:6> 6 SEL Rt: <:6> W R/W ata dr R Comp 4 Fall 7 /4/7 L6- Building a Computer 9
MIPS: Our Final Version x8 x84 x88 <3:9>:J<5:>: JT BT SEL 6 5 4 3 RESET IRQ J:<5:> N V C SEL WSEL SEL Rd:<5:> Rt:<:6> 3 7 Imm: <5:> x4 + BT WSEL 3 JT This is a complete -bit processor. lthough designed in one class lecture, it executes the majority of the MIPS R instruction set. R R W W W R R Rs: <5:> B LU N V C shamt:<:6> 6 SEL Rt: <:6> W R/W ata dr R Executes one instruction per clock ll that s left is the control logic design Comp 4 Fall 7 /4/7 L6- Building a Computer
L6- Building a Computer Comp 4 Fall 7 /4/7 MIPS Control The control unit can be built as a large ROM B S E L beq sw S E L lw andi sll add Sub Bool Shft Math 3 6 4 W E R F W R W S E L W S E L S E T P C S E L C V N I R Q R E S E T