ISLV K x LOW VOLTAGE CMOS STATIC RAM FEATURES High-speed access time: 0,,, and 0 ns CMOS low power operation 0 mw (typical) operating 0 µw (typical) standby TTL compatible interface levels Single.V ± 0% power supply Fully static operation: no clock or refresh required Three state outputs Industrial temperature available Available in -pin 00mil SOJ package and -pin TSOP- FUTIONAL BLOCK DIAGRAM DESCRIPTION The ICSI ISLV is a high-speed, K static RAM organized as, words by bits. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields fast access times with low power consumption. When is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, and. The active LOW Write Enable () controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte () access. The ISLV is packaged in the JEDEC standard -pin 00mil SOJ and -pin 00mil TSOP-. A0-A DECODER K x MEMORY ARRAY VCC I/O0-I/O Lower Byte I/O-I/O Upper Byte I/O DATA CIRCUIT COLUMN I/O 0 UB CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright, Integrated Silicon Solution Inc. Integrated Circuit Solution Inc.
PIN CONFIGURATIONS -Pin SOJ -Pin TSOP- A0 A A A A I/O0 I/O I/O I/O I/O I/O I/O I/O A0 A A A 0 0 0 0 A A UB I/O I/O I/O I/O I/O I/O0 I/O I/O A A A A A A A A I/O0 I/O I/O I/O I/O I/O I/O I/O A0 A A A 0 0 0 0 A0 A A UB I/O I/O I/O I/O I/O I/O0 I/O I/O A A A A PIN DESCRIPTIONS A0-A Address Inputs Lower-byte Control (I/O0-I/O) I/O0-I/O Data Inputs/Outputs UB Upper-byte Control (I/O-I/O) Chip Enable Input No Connection Output Enable Input Power Write Enable Input Ground TRUTH TABLE I/O PIN Mode UB I/O0-I/O I/O-I/O Current Not Selected X H X X X High-Z High-Z ISB, ISB Output Disabled H L H X X High-Z High-Z ICC X L X H H High-Z High-Z Read H L L L H DOUT High-Z ICC H L L H L High-Z DOUT H L L L L DOUT DOUT Write L L X L H DIN High-Z ICC L L X H L High-Z DIN L L X L L DIN DIN Integrated Circuit Solution Inc.
ABSOLUTE MAXIMUM RATINGS () Symbol Parameter Value Unit VCC Supply Voltage with Respect to 0. to +. V VTERM Terminal Voltage with Respect to 0. to + 0. V TSTG Storage Temperature to +0 C PT Power Dissipation.0 W IOUT DC Output Current (LOW) 0 ma OPERATING RANGE Range Ambient Temperature VCC Commercial 0 C to +0 C.V ± 0% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH =.0 ma. V VOL Output LOW Voltage VCC = Min., IOL =.0 ma 0. V VIH Input HIGH Voltage. VCC + 0. V VIL Input LOW Voltage () 0. 0. V ILI Input Leakage VIN VCC µa ILO Output Leakage VOUT VCC, Outputs Disabled µa. VIL (min.) =.0V for pulse width less than 0 ns. POR SUPPLY CHARACTERISTICS () (Over Operating Range) Note:. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. -0 ns - ns - ns -0 ns Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit ICC Dynamic Operating VCC = Max., Com. 0 00 0 0 ma Supply Current IOUT = 0 ma, f = fmax Ind. 0 00 0 ISB TTL Standby Current VCC = Max., Com. 0 0 0 0 ma (TTL Inputs) VIN = VIH or VIL Ind. 0 0 0 VIH, f = 0 ISB CMOS Standby VCC = Max., Com. ma Current (CMOS Inputs) VCC 0.V, Ind. 0 0 0 VIN VCC 0.V, or VIN 0.V, f = 0 Note:. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 0 Integrated Circuit Solution Inc.
CAPACITAE () Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 0V pf COUT Input/Output Capacitance VOUT = 0V pf Note:. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS () (Over Operating Range) -0 - - -0 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit trc Read Cycle Time 0 0 ns taa Address Access Time 0 0 ns toha Output Hold Time ns ta Access Time 0 0 ns td Access Time ns thz () to High-Z Output 0 0 0 0 ns tlz () to Low-Z Output 0 0 0 0 ns thz ( to High-Z Output 0 0 0 0 ns tlz () to Low-Z Output ns tba, UB Access Time ns thzb, UB to High-Z Output 0 0 0 0 ns tlzb, UB to Low-Z Output ns. Test conditions assume signal transition times of ns or less, timing reference levels of.v, input pulse levels of 0 to.0v and output loading specified in Figure a.. Tested with the load in Figure b. Transition is measured ±00 mv from steady-state voltage. Not 00% tested.. Not 00% tested. AC TEST CONDITIONS Parameter Unit Input Pulse Level 0V to.0v Input Rise and Fall Times ns Input and Output Timing.V and Reference Level Output Load See Figures a and b AC TEST LOADS 0 Ω 0 Ω V V OUTPUT OUTPUT 0 pf Including jig and scope Ω pf Including jig and scope Ω Figure a. Figure b. Integrated Circuit Solution Inc.
AC WAVEFORMS READ CYCLE NO. (,) (Address Controlled) ( = = VIL, UB or = VIL) ADDRESS taa toha toha DOUT PREVIOUS DATA VALID DATA VALID READ CYCLE NO. (,) trc ADDRESS trc taa toha, UB DOUT HIGH-Z tlzb tlz td tlz ta tba DATA VALID thz thz thzb. is HIGH for a Read Cycle.. The device is continuously selected.,, UB, or = VIL.. Address is valid prior to or coincident with LOW transition. 0 Integrated Circuit Solution Inc.
WRITE CYCLE SWITCHING CHARACTERISTICS (,) (Over Operating Range) -0 - - -0 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit twc Write Cycle Time 0 0 ns ts to Write End 0 ns taw Address Setup Time 0 ns to Write End tha Address Hold from Write End 0 0 0 0 ns tsa Address Setup Time 0 0 0 0 ns tpwb, UB Valid to End of Write 0 ns tp Pulse Width 0 ns tsd Data Setup to Write End ns thd Data Hold from Write End 0 0 0 0 ns thz () LOW to High-Z Output ns tlz () HIGH to Low-Z Output ns. Test conditions assume signal transition times of ns or less, timing reference levels of.v, input pulse levels of 0 to.0v and output loading specified in Figure a.. Tested with the load in Figure b. Transition is measured ±00 mv from steady-state voltage. Not 00% tested.. The internal write time is defined by the overlap of LOW and UB or, and LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Integrated Circuit Solution Inc.
AC WAVEFORMS WRITE CYCLE NO. ( Controlled) (,) ADDRESS twc ts tha tpwb, UB taw tp tsa WRITE () DIN tsd thd DOUT HIGH-Z thz UNDEFINED tlz HIGH-Z UNDEFINED. WRITE is an internally generated signal asserted during an overlap of the LOW states on the and inputs and at least one of the and UB inputs being in the LOW state.. WRITE = () [ () = (UB) ] (). 0 Integrated Circuit Solution Inc.
ORDERING INFORMATION Commercial Range: 0 C to +0 C Speed (ns) Order Part No. Package 0 ISLV-0T 00mil TSOP- 0 ISLV-0K 00mil SOJ ISLV-T 00mil TSOP- ISLV-K 00mil SOJ ISLV-T 00mil TSOP- ISLV-K 00mil SOJ 0 ISLV-0T 00mil TSOP- 0 ISLV-0K 00mil SOJ ORDERING INFORMATION Industrial Range: 0 C to + C Speed (ns) Order Part No. Package ISLV-TI 00mil TSOP- ISLV-KI 00mil SOJ ISLV-TI 00mil TSOP- ISLV-KI 00mil SOJ 0 ISLV-0TI 00mil TSOP- 0 ISLV-0KI 00mil SOJ Integrated Circuit Solution Inc. HEADQUARTER: NO., TECHNOLOGY RD. V, SCIEE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: --0 Fax: --000 BRAH OFFI: F, NO. 0, SEC., HSIN-TAI TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: --0 FAX: -- http://www.icsi.com.tw Integrated Circuit Solution Inc.