Sequential Logic Circuits

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Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit, on the other hand, depends both on the current input values as well as the past inputs. This dependence on past inputs gives the property of memory for sequential circuits. 4 2 The sequence of past inputs is encoded into a set of variables. The feedback circuit stores this information and feeds it to the input. 4 3 When the propagation delay is zero, theoretically, signals at the input and output of the inverter change at the same time. This means the output of the ND gate is always zero. 4 4 When S and R are 1, both outputs are forced to take 0. To see why this combination is undesirable, consider what happens when S and R inputs are changed from S = R = 1 to S = R = 0. It is only in theory that we can assume that both inputs change simultaneously. In practice, there is always some finite time difference between the two signal changes. If the S input goes low earlier than the R signal, the sequence of input changes is SR = 11! 01! 00. Because of the intermediate SR = 01, the output will be =0and = 1. If, on the other hand, the R signal goes low before the S signal does, the sequence of input changes is SR = 11! 10! 00. Because the transition goes through the SR = 10 intermediate, the output will be = 1 and = 0. Thus, when the input changes from 11 to 00, the output is indeterminate. This is the reason for avoiding this. 4 5 The truth table is shown below: S R 0 0 0 1 1 0 1 1 n+1 1 0 1 n 1

2 Chapter 4 It can se seen from this truth table that is not exactly the same as that given for the NOR gate version. However, it is closely related in the sense it is the dual of the other truth table. 4 6 The D-latch avoids the SR = 11 input combination by using a single inverter to provide only complementary inputs at S and R inputs of the clocked SR latch as shown below: S R Clock 4 7 Flip-flops are edge-triggered devices whereas latches are level sensitive. 4 8 The circuit is shown below: 0 1 2 3 S S S S Clock Reset C FF0 C FF1 C FF2 C FF3 4 9 The circuit is shown below: 0 1 2 3 4 Clock 4 10 The circuit is shown below:

Chapter 4 3 D C B Clock C C C C 4 11 We need four flip-flops to implement this four-bit counter. The design table is shown below: Next flip-flop inputs B C D B C D B B C C D D 0 0 0 0 0 0 1 0 0 d 0 d 1 d 0 d 0 0 0 1 d d d d d d d d 0 0 1 0 0 1 0 0 0 d 1 d d 1 0 d 0 0 1 1 d d d d d d d d 0 1 0 0 0 1 1 0 0 d d 0 1 d 0 d 0 1 0 1 d d d d d d d d 0 1 1 0 1 0 0 0 1 d d 1 d 1 0 d 0 1 1 1 d d d d d d d d 1 0 0 0 1 0 1 0 d 0 0 d 1 d 0 d 1 0 0 1 d d d d d d d d 1 0 1 0 1 1 0 0 d 0 1 d d 1 0 d 1 0 1 1 d d d d d d d d 1 1 0 0 1 1 1 0 d 0 d 0 1 d 0 d 1 1 0 1 d d d d d d d d 1 1 1 0 0 0 0 0 d 1 d 1 d 1 0 d 1 1 1 1 d d d d d d d d

4 Chapter 4 Using the arnaugh map method, we can get the simplified logical expressions for the and inputs as follows: = BC; = BC B = C, B = C C =1; C =1 D =0; D = d Notice that the D flip-flop is not necessary as its output is always 0. The circuit is shown below: D C B C C C Clock 4 12 We need three flip-flops to implement this four-bit counter. The design table is shown below: Next flip-flop inputs B C B C B B C C 0 0 0 0 0 1 0 d 0 d 1 d 0 0 1 0 1 1 0 d 1 d d 0 0 1 0 1 1 0 1 d d 0 0 d 0 1 1 0 1 0 0 d d 0 d 1 1 0 0 0 0 0 d 1 0 d 0 d 1 0 1 1 0 0 d 0 0 d d 1 1 1 0 1 1 1 d 0 d 0 1 d 1 1 1 1 0 1 d 0 d 1 d 0 Using the arnaugh map method, we can get the simplified logical expressions for the and inputs as follows:

Chapter 4 5 = BC; = B C B = C; B = C C = B + B; C = B + B The circuit is shown below: C B C C C Clock 4 13 The table is shown below: Next Output X=0 X=1 X=0 X=1 S0 S0 S1 0 1 S1 S1 S0 1 0 Simple assignment: S0 = 0 and S1 = 1. Next flip-flop inputs X Y 0 0 0 0 0 d 0 1 1 1 1 d 1 0 1 1 d 0 1 1 0 0 d 1

6 Chapter 4 Using the arnaugh map method, we can get the simplified logical expressions for the and inputs and the output Y as follows: = X; = X Y = X + X The circuit is shown below: Y Clock C X 4 14 The arnaugh map for the assignment is shown below: BC 00 01 11 10 0 S0 S3 S5 1 S1 S6 S4 S2 Final assignment is shown below: State B C S0 = 0 0 0 S1 = 1 0 0 S2 = 1 1 0 S3 = 0 0 1 S4 = 1 1 1 S5 = 0 1 0 S6 = 1 0 1 The design table is shown below:

Chapter 4 7 Next flip-flop inputs B C X B C Y B B C C 0 0 0 0 1 1 0 0 1 d 1 d 0 d 0 0 0 1 1 0 0 0 1 d 0 d 0 d 0 0 1 0 1 1 1 0 1 d 1 d d 0 0 0 1 1 0 0 1 0 0 d 0 d d 0 0 1 0 0 1 1 1 1 1 d d 0 1 d 0 1 0 1 0 0 1 0 0 d d 1 1 d 1 0 0 0 1 1 1 0 d 0 1 d 1 d 1 0 0 1 0 0 1 0 d 1 0 d 1 d 1 0 1 0 1 0 1 0 d 0 0 d d 0 1 0 1 1 0 1 0 1 d 1 1 d d 1 1 1 0 0 1 0 1 0 d 0 d 1 1 d 1 1 0 1 0 1 0 0 d 1 d 0 0 d 1 1 1 0 1 0 1 1 d 0 d 1 d 0 1 1 1 1 0 1 0 0 d 1 d 0 d 1 Using the arnaugh map method, we can get the simplified logical expressions for the and inputs as follows: = X + B C; = X B = C X + X + CX; C = B + B + X; B = X + X C = X The Y output logical expression is: Y = B CX + BCX + B X It is straightforward to complete the solution using these expressions (similar to what is shown in Figures 4.27 and 4.28). 4 15 We can use the same circuit; all we have to do is invert the input. 4 16 The diagram is shown below:

8 Chapter 4 You can see from this diagram that the design remains the same as that for the pattern recognition example on page 134 (see Example 2). However, we need to modify the output Y. In the Y column in Table 4.8, the last two 1s should be zero. This gives us the following expression for the only 1 in that column: Y = BCX. The implementation is as shown in Figure 4.28 (substitute the following circuit for the Y logic circuit given in Figure 4.8b): B C Y X 4 17 The diagram is shown below:

Chapter 4 9 Next Output X=0 X=1 X=0 X=1 S0 S1 S0 0 0 S1 S1 S2 0 0 S2 S0 S0 1 0 Heuristic 1 groupings: (S0, S1) (S0, S2) Heuristic 2 groupings: (S0, S1) (S0, S2) These groupings suggest the following assignment: B 0 1 0 S0 S1 1 S2 Final assignment is shown below: State B S0 = 0 0 S1 = 0 1 S2 = 1 0 The design table is shown below:

10 Chapter 4 Next flip-flop inputs B X B Y B B 0 0 0 0 1 0 0 d 1 d 0 0 1 0 0 0 0 d 0 d 0 1 0 0 1 0 0 d d 0 0 1 1 1 0 0 1 d d 1 1 0 0 0 0 1 d 1 0 d 1 0 1 0 0 0 d 1 0 d Using the arnaugh map method, we can get the simplified logical expressions for the and inputs as follows: = BX; =1 B = X; B = X The Y output logical expression is: Y = X The implementation is shown below: C B C Y X Clock 4 18 The diagram is shown below:

Chapter 4 11 01/0 01/0 01/0 01/0 01/0 01/1 00/0 S0 S1 S2 S3 S4 S5 00/0 00/0 00/0 00/0 00/0 10/1 10/0 10/0 10/0 10/1 10/0 The table is shown below: Next Output Z XY=00 XY=01 XY=10 XY = 00 XY = 01 XY = 10 S0 S0 S1 S2 0 0 0 S1 S1 S2 S3 0 0 0 S2 S2 S3 S4 0 0 0 S3 S3 S4 S5 0 0 0 S4 S4 S5 S5 0 1 1 S5 S5 S1 S2 0 0 0 Heuristic 1 groupings: (S0, S5) 2 (S3, S4) Heuristic 2 groupings: (S1, S2) 3 (S2, S3) 2 (S4, S5) 2 (S3, S4) 2 Heuristic 3 groupings: None These groupings suggest the following assignment:

12 Chapter 4 BC 00 01 11 10 0 S0 S3 S2 1 S5 S4 S1 Final assignment is shown below: State B C S0 = 0 0 0 S1 = 1 1 1 S2 = 0 1 1 S3 = 0 0 1 S4 = 1 0 1 S5 = 1 0 0 The design table is shown below:

Chapter 4 13 Next flip-flop inputs B C XY B C Z B B C C 0 0 0 00 0 0 0 0 0 d 0 d 0 d 0 0 0 01 1 1 1 0 1 d 1 d 1 d 0 0 0 10 0 1 1 0 0 d 1 d 1 d 0 0 1 00 0 0 1 0 0 d 0 d d 0 0 0 1 01 1 0 1 0 1 d 0 d d 0 0 0 1 10 1 0 0 0 1 d 0 d d 1 0 1 1 00 0 1 1 0 0 d d 0 d 0 0 1 1 01 0 0 1 0 0 d d 1 d 0 0 1 1 10 1 0 1 0 1 d d 1 d 0 1 0 0 00 1 0 0 0 d 0 0 d 0 d 1 0 0 01 1 1 1 0 d 0 1 d 1 d 1 0 0 10 0 1 1 0 d 1 1 d 1 d 1 0 1 00 1 0 1 0 d 0 0 d d 0 1 0 1 01 1 0 0 1 d 0 0 d d 1 1 0 1 10 1 0 0 1 d 0 0 d d 1 1 1 1 00 1 1 1 0 d 0 d 0 d 0 1 1 1 01 0 1 1 0 d 1 d 0 d 0 1 1 1 10 0 0 1 0 d 1 d 1 d 0 Using the arnaugh map method, we can get the simplified logical expressions for the and inputs as follows: = B Y + CX; = BX + BY + C X B = C X + C Y; B = X + Y C = X + Y; C = B CXY + B C X Y The Z output logical expression is: Z = B C (X Y + X Y) It is straightforward to complete the solution using these expressions (similar to what is shown in

14 Chapter 4 Figures 4.27 and 4.28). 4 19 The diagram is shown below: 01/00 01/00 01/00 01/00 01/00 01/00 01/01 00/00 S0 S1 S2 S3 S4 S5 S6 00/00 00/00 00/00 00/00 00/00 00/00 10/00 10/00 10/00 10/10 10/11 10/00 10/00 Note that the output is represented by two bits: CZ. The C bit indicates change due and the Z bit indicates activation of the selection circuit (as in the last exercise). The table is shown below: Next Output CZ XY=00 XY=01 XY=10 XY = 00 XY = 01 XY = 10 S0 S0 S1 S2 00 00 00 S1 S1 S2 S3 00 00 00 S2 S2 S3 S4 00 00 00 S3 S3 S4 S5 00 00 00 S4 S4 S5 S5 00 01 11 S5 S5 S1 S2 00 00 00 S6 S6 S1 S2 00 00 00 Heuristic 1 groupings: (S0, S5, S6) 2 (S3, S4) Heuristic 2 groupings: (S1, S2) 4 (S2, S3) 2 (S4, S5) 2 (S3, S4) 2

Chapter 4 15 Heuristic 3 groupings: None These groupings suggest the following assignment: BC 00 01 11 10 0 S0 S3 S2 1 S5 S4 S1 S6 Final assignment is shown below: State B C S0 = 0 0 0 S1 = 1 1 1 S2 = 0 1 1 S3 = 0 0 1 S4 = 1 0 1 S5 = 1 0 0 S6 = 1 1 0 The design table is shown below:

16 Chapter 4 Next flip-flop inputs B C XY B C CZ B B C C 0 0 0 00 0 0 0 00 0 d 0 d 0 d 0 0 0 01 1 1 1 00 1 d 1 d 1 d 0 0 0 10 0 1 1 00 0 d 1 d 1 d 0 0 1 00 0 0 1 00 0 d 0 d d 0 0 0 1 01 1 0 1 00 1 d 0 d d 0 0 0 1 10 1 0 0 00 1 d 0 d d 1 0 1 1 00 0 1 1 00 0 d d 0 d 0 0 1 1 01 0 0 1 00 0 d d 1 d 0 0 1 1 10 1 0 1 00 1 d d 1 d 0 1 0 0 00 1 0 0 00 d 0 0 d 0 d 1 0 0 01 1 1 1 00 d 0 1 d 1 d 1 0 0 10 0 1 1 00 d 1 1 d 1 d 1 0 1 00 1 0 1 00 d 0 0 d d 0 1 0 1 01 1 0 0 01 d 0 0 d d 1 1 0 1 10 1 0 0 11 d 0 0 d d 1 1 1 0 00 1 1 0 00 d 0 d 0 0 d 1 1 0 01 1 1 1 00 d 0 d 0 1 d 1 1 0 10 0 1 1 00 d 1 d 0 1 d 1 1 1 00 1 1 1 00 d 0 d 0 d 0 1 1 1 01 0 1 1 00 d 1 d 0 d 0 1 1 1 10 0 0 1 00 d 1 d 1 d 0 Using the arnaugh map method, we can get the simplified logical expressions for the and inputs as follows: = B Y + CX; B = C X + C Y; = BX + BCY + C X B = X + Y

Chapter 4 17 C = X + Y; C = B CXY + B C X Y The C and Z output logical expressions are: C = BC X Y Z = B C (X Y + X Y) It is straightforward to complete the solution using these expressions (similar to what is shown in Figures 4.27 and 4.28).

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