Lecure 5: ifferenial Pairs (Par ) Gu-Yeon Wei ivision of Enineerin and Applied Sciences Harvard Universiy uyeon@eecs.harvard.edu Wei
Overview eadin S&S: Chaper 6.6 Suppleenal eadin S&S: Chaper 6.9 azavi, esin of Analo CMOS neraed Circuis: Chaper 4 Backround Our reaen of MOS differenial pairs has assued ideal eleens. However, real devices suffer a variey of isaches. This lecure will invesiae how isaches in he load resisor and ransisors affec perforance of he differenial pair. We will hen conclude our discussion of differenial pair aplifiers wih an acive-load differenial pair ha only uses MOS devices. Wei ES54 - Lecure 5
Anoher Way o Analyze MOS ifferenial Pairs Le s invesiae anoher echnique for analyzin he MOS differenial pair For he differenial pair circui on he lef (driven by wo independen sinals), copue he oupu usin superposiion Sar wih in, se in 0 and firs solve for X w.r.. in educes o a deeneraed coon-source ap nelecin channel-lenh odulaion and bodyeffec, S / so in ou ou X Y ou X Y ou in in ou ou X Y ou X X in + S + in M M S in S Wei ES54 - Lecure 5 3
Now, solve for Y w.r.. in eplace circui wihin box wih a Thevenin equivalen M is a source follower wih T in T / The circui reduces o a coon-ae aplifier where ou X Y ou M M Y in + So, overall (assuin ) in X Y due o in + in in by syery Y ou X Y due o in in T A d X in Y in T Wei ES54 - Lecure 5 4
Offses in MOS ifferenial Pair There are 3 ain sources of offse ha affec he perforance of MOS differenial pair circuis Misach in load resisors Misach in W/L of differenial pair devices Misach in of differenial pair devices Le s invesiae each individually Wei ES54 - Lecure 5 5
esisor Misach For he differenial pair circui shown, consider he case where Load resisors are isached by, ± All oher devices paraeers are perfecly ached Wih boh inpus rounded, /, bu O is no zero due o differences in he volaes across he load resisors O O is coon o find he inpu-referred offse which is calculaed as A OS O d since A d OS Wei ES54 - Lecure 5 6
W/L Misach Now consider wha happens when device sizes W/L are isached for he wo differenial pair MOS devices M and M W L, W L This isach causes isach in he currens ha flow hrouh M and M, W L ± ± ( W L) ( W L) This isach resuls in O O ( W L) ( W L) So in he inpu referred offse is OS O A d OS ( W L) ( W L) Wei ES54 - Lecure 5 7
ES54 - Lecure 5 Wei 8 Misach Lasly, consider isaches in he hreshold volae Aain, currens and will differ accordin o he followin sauraion curren equaion For sall << ( - ) Aain, usin OS O /A d (A d and O ) we e, ± ( ) ( ) ox n ox n L W C L W C µ µ ( ), L W C ox n µ ( )( ) d OS A
Misach Suary The 3 sources of isach can be cobined ino one equaion: OS + + ( W L) ( W L) arisin fro,, and W/L isaches Noice ha offses due o and W/L are funcions of he overdrive volae Wei ES54 - Lecure 5 9
ifferenial Pair wih MOS Loads b ou ou in in Consider he above wo MOS loads in place of resisors Lef: a diode conneced pmos has an effecive resisance of / P N Ad N ( P ron rop ) P ih: pmos devices in sauraion have effecive resisance of r op A r r d N ( ) on op Wei ES54 - Lecure 5 0
Acive-Loaded CMOS ifferenial Aplifier A coonly used aplifier opoloy in CMOS echnoloies Oupu is aken sinle-endedly for a differenial inpu wih a v id / a he ae of M, i flows i v id ( ) M3 M4 i i is also irrored hrouh he M3-M4 curren irror a v id / a he ae of M causes i o also flow hrouh M i v id ( ) v id M i M i v o Given ha / (noinally) The volae a he oupu hen is iven by ( i + i )( r r ) i ( r r ) v o o o4 o o ro Ad ( ro ro 4 ) 4 Wei ES54 - Lecure 5
Nex Tie eadin: S&S: Chaper 6.6 Suppleenal eadin: S&S: Chaper 6.4 azavi: Chaper 5 Overview We have seen ha ransisor ransconducance and he effecive load resisance se he ain of differenial aplifiers. We will nex invesiae a echnique called cascodin ha can increase he oupu resisance of MOS devices in sauraion. Uilizin his echnique, we can build hiher qualiy curren sources and aplifiers (w/ MOS loads) wih hiher ain. We will also see he rade offs his echnique iposes. Wei ES54 - Lecure 5