IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 15, NO. 3, SEPTEMBER 2015 319 Analysis of Intrinsic Charge Loss Mechanisms for Nanoscale NAND Flash Memory Jun Yeong Lim, Student Member, IEEE, Pyung Moon, Student Member, IEEE, Sang Myung Lee, Student Member, IEEE, Keum-Whan Noh, Tae-Un Youn, Jong-Wook Kim, and Ilgu Yun, Senior Member, IEEE Abstract In the current memory market, many researchers have analyzed the data retention characteristic and predicted the related leakage mechanism. Most studies have shown that the dominant degradation of retention characteristics of Flash memory occurs in the tunneling oxide after program/erase cycling. However, serious degradation of the retention characteristics is also seen in the intrinsic situation before program/erase cycling of devices through the oxide nitride oxide (ONO) interpoly dielectric. In this paper, we analyze that degradation by examining the various charge loss mechanisms of the device before cycling and extract two appropriate charge loss mechanisms by comparing the measured V th data with the TCAD simulation data, and we verify the mechanisms by extracting the activation energy of each mechanism. We also analyze the effects on those two mechanisms as the ONO thickness and temperature are changed. Based on the results, we establish the intrinsic leakage mechanism through the ONO layers and predict the change in leakage mechanism as the thickness of the ONO layers is decreased. Index Terms Activation energy, charge loss, NAND flash, program/erase cycling, degradation, TCAD. I. INTRODUCTION AS nonvolatile NAND flash memory has been scaled down, retention has become a more serious problem due to the charge loss of the floating gate due to interference with the close cell and leakage through the tunneling oxide or oxide nitride oxide (ONO) inter-poly dielectric (IPD) [1], [2]. This has long been a significant problem for memory devices because it is impossible to determine the exact leakage mechanism of charge loss in the low-electric field region, which is the retention state, due to the limitations of instrument resolution of measurement. Accordingly, active analyses of the degradation TABLE I SAMPLE THICKNESSES OF ONO LAYERS of the retention characteristic through insulators have been performed for various stress conditions and using various methods, including the floating gate technique [3], fitting of the standard equation of V th [4], and Arrhenius law [5]. Until now, researchers have generally given priority to the degradation of tunneling oxide after baking and cycling, because the basic principle of flash memory is using the tunneling through the tunneling oxide [6]. However, it is also important to analyze the generated charge loss through the ONO layers [7] before program/erase cycling, since it is continuously generated at the operating device together with the charge loss through the tunneling oxide after program/erase cycling. Therefore, in this paper, the conduction mechanisms at the retention state that induced the degradation of the charge loss of the device before cycling will be studied by comparing the measured V th data with the TCAD simulation data, which is more reliable and exact than the methods described above. In addition, the variations in retention characteristics of devices as changing thickness of ONO or temperature are also studied using the leakage mechanisms at TCAD. II. EXPERIMENT Manuscript received December 1, 2014; revised May 7, 2015; accepted May 13, 2015. Date of publication May 25, 2015; date of current version September 1, 2015. This work was supported in part by SK Hynix, by IC Design Education Center, and by the Institute of BioMed IT, Energy IT and Smart IT Technology (BEST), a Brain Korea 21 plus program, Yonsei University. J. Y. Lim, P. Moon, S. M. Lee, and I. Yun are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: iyun@yonsei.ac.kr). K.-W. Noh, T.-U. Youn, and J.-W. Kim are with the Research and Development Division, SK Hynix Semiconductor Inc., Chungcheongbuk 361-725, Korea. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TDMR.2015.2437364 The test structure was fabricated on a 12-inch wafer using the nano-scale NAND Flash process by SK Hynix Semiconductor Inc. The tunneling oxide was grown on a Si-substrate, and the test structure of the IPD was constructed with an ONO stack sandwiched with two heavily doped poly-si layers acting as the floating gate and the control gate. The silicon oxide (bottom), silicon nitride, and silicon oxide (top) of the ONO stack were grown sequentially by LPCVD [8]. Based on these processes, we fabricated three test samples with different equivalent oxide thickness (EOT) of the ONO, as shown in Table I. Here, the sample S1 had the smallest EOT, sample S3 had the largest EOT, and the EOT of sample S2 was between those of S1 and S3. 1530-4388 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
320 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 15, NO. 3, SEPTEMBER 2015 Fig. 1. Data retention characteristics at various charge s state of the floating gate at room temperature [8]. Based on this structure, we measured the intrinsic retention characteristics of the multi-layer cell (MLC) NAND flash memory at baking temperatures of 300 K, 365 K, 400 K, and 425 K and various ONO thicknesses. These cells on wafer were equally programmed at initial stage. Fig. 1 shows the charge loss of the MLC NAND flash cells of the device before cycling [8]. Among the MLC states, the PV3 state generated more tail bits after baking at room temperature than the PV1 and PV2 states because of its larger internal electric field induced by the large amount of stored charge. Therefore, we analyzed the intrinsic retention characteristic of the PV3 state, which has the largest number of tail bits. TheaveragevalueofΔV th of 4000 tail bits was extracted as the baking temperature changed, and we measured the ΔV th at several retention times. The TCAD structure was designed to be similar to a real cell using the sentaurus TCAD workbench [9], as shown in Fig. 2. We inserted charges to the floating gate based on the measured data and modeled the intrinsic retention characteristic by analyzing the degradation of V th according to time for various leakage mechanisms. Fig. 2. The simulation structure of the FG NAND flash memory for TCAD. III. RESULTS AND DISCUSSION Fig. 3 shows the degradation of V th of the intrinsic cells of the PV3 state versus bake time. It is generally known that the degradation of V th is due to defects in the tunneling oxide after program/erase cycling [10], [11]. However, the charge loss of the device before cycling is different with the device after cycling. Fig. 4 shows the average and the standard deviation of ΔV th on tail bits when the thicknesses of the tunneling oxide and ONO are changed. It is observed that the effect of charge loss by varying the thickness of tunneling oxide is negligible as shown in Fig. 4(a). However, the effect of charge loss by varying the ONO thickness, it is found that ΔV th increases as the EOT of ONO decreases as shown in Fig. 4(b). It indicates that the charge loss of the device before cycling in retention mode is generated through the ONO Fig. 3. Intrinsic retention characteristic of sample S1 according to the bake time at various temperatures. layer. Therefore, the degradation in Fig. 3 indicates leakage through the ONO layers [7]. In addition, the reason why leakage currents only take place through the IPD layers even though the thickness of the tunneling oxide is thinner than IPD layers is due to the stacked structure of IPD layer. In the measurement process of retention characteristic of the floating gate (FG) flash memory devices, FG only has voltage corresponding to the stored charges. Therefore, in IPD layers between FG and the control gate (CG), it is found that almost no voltage applied to the CG, which
LIM et al.: CHARGE LOSS MECHANISMS FOR NANOSCALE NAND FLASH MEMORY 321 Fig. 5. The retention characteristic of sample S3 modeled by the trap-assisted tunneling mechanism at 425 K. Fig. 4. The effect of (a) tunneling oxide and (b) inter-poly dielectric layers to the charge loss of device. correspondingly represented to the top oxide and mid nitride layers altogether. Then, it indicates that the electric field is only applied to the bottom oxide layer between FG and nitride layer. Therefore, this electric field is larger than the electric field applied to the tunneling oxide between FG and the substrate because the thickness of bottom oxide alone in IPD layers is thinner than the tunneling oxide. Thus, it is concluded that the charge loss is generated mainly through the IPD layers not the tunneling oxide. The degradation of V th can be divided into the rapid charge loss at the initial transient time period and the consistent charge loss for the steady-state time period [4]. The rapid charge loss at the initial time period is usually explained by the interfacestates annealing or recovery [12], [13]. The generated electronhole pairs during program/erase or native defects are detrapped at the trap sites, and then these make the rapid V th shift at the initial time period. However, it is shown that the shift gradually saturates to the specific level because recovery of interface traps or native defects have the limitation when the trap sites and defects are reached to the steady-state after a specific time elapses. Therefore, it just affects the entire V th shift as much as a specific quantity. However, in case of the consistent charge loss, the charge loss is gradually generated along the time through the leakage mechanisms. Therefore, it is more feasible to analyze the consistent retention characteristic of device than the rapid charge loss of interface traps. In addition, the V th shift at the initial time period is easily varied due to the trap recovery, native defects, and generated electron-hole pair during fabrication and program/erase. As shown in Fig. 3, we divide the total charge loss ΔV th into two phases based on the 12 hours. The 1st phase represents the rapid charge loss of V th and the 2nd phase represents the consistent charge loss and we intensively analyzed the mechanisms of the 2nd phase charge loss. Additionally, 12 hours is enough time for interface traps and defects to become a steady state [14], so we can determine that the remaining V th shift which is second phase does not have the recovery characteristics. Fig. 5 shows the adjusted floating gate voltage (V fg ) of the second phase shift with respect to bake time. The floating gate voltage has a linear relation with threshold voltage, because both terms are related to the stored charge in a device [15], [16]. Fowler Nordheim (FN) tunneling, direct tunneling, ohmic emission, trap-assisted tunneling (TAT) and Poole Frenkel (PF) mechanisms [17], which are conduction mechanisms through an insulator, are selected as possible candidates to explain the charge loss mechanism, and they were simulated using TCAD [9]. To date, the leakage mechanism for a low-electric field was generally explained using one dominant mechanism [4], [10], [18]. In the case of sample S3, which has the thickest EOT of ONO, the ΔV th degradation at 425 K is sufficient to note that the dominant mechanism of the sample is TAT, as shown in Fig. 5. This means that the stored charges of the device before cycling also leak through the defect or the trap from the FG to the ONO layers [4]. However, a single mechanism cannot completely explain the degradation in sample S1 and sample S2, which had thinner EOT of the ONO than sample S3. As illustrated in Fig. 6, when we model the retention characteristic using just the TAT mechanism, it is difficult to model ΔV th due to the excessive
322 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 15, NO. 3, SEPTEMBER 2015 Fig. 6. Comparing the suggested mechanism and TAT on sample S2 at 425 K. Fig. 8. The variations in the portion of PF and TAT according to EOT at 300 K, 365 K, 400 K, and 425 K. Fig. 7. The simulation results using the suggested mechanism on sample S1 for the bake time of 300 K, 365 K, and 425 K. charge loss of the FG. However, the charge loss for the thinner EOT of the ONO can be explained by the combination of two mechanisms, TAT and PF, as presented in (1), and the combined mechanisms agree with the measured data when the baking temperature is changed from 300 K to 425 K, as shown in Fig. 7. However, when we inserted mechanisms, except TAT and PF mechanisms, it is unable to fit V th loss data. For example, in case of the Fowler Nordheim mechanism, V th loss induced is very small because it has small current at the low electric field region even if it has large current at high electric field region, so it is unsuitable to the measured data. In case of the ohmic emission and direct tunneling, it is also unsuitable because the generated V th loss is too small ΔV th,total =ΔV th,tat +ΔV th,pf (1) where ΔV th,tat is induced by the trap-assisted tunneling mechanism, ΔV th,pf is induced by the Poole Frenkel mecha- nism [17]. We derive the results by adjusting the trap parameter of each mechanism in the simulation. The parameter of TAT mechanism is empty trap density, and the parameter of PF is filled trap density. Fig. 8 shows that how much portion each mechanism occupies in the fixed quantity of ΔV th,total according to the EOT of ONO layer and temperature. At first, when the EOT of ONO layer changes, it is shown that the portion of each mechanism is considerably changed. As shown in Fig. 8, the thickest sample S3 has a higher portion of TAT and a lower portion of PF. On the other hand, sample S1 has a lower portion of TAT and a higher portion of PF than the others. The reason why the portion of each mechanism is changed with varying the thickness is due to the change of inside region of IPD. As the thickness of IPD is increased, both the empty trap and filled trap sites inside the region of IPD are also increased due to the thicker IPD region than thin IPD region. Furthermore, in case of before cycling, the thicker IPD region has larger empty trap density than filled trap density because the step of UV process before initial program or erase emits all trapped charges from the intrinsically filled trap sites. Therefore, the portion of TAT mechanism which uses the empty trap density grows when the thickness of IPD increases and it is the reason why the leakage mechanism of a low-electric field was generally explained using one dominant mechanism in past devices [4], which had thicker ONO than current devices. Therefore, to reduce the EOT to satisfy the market trends, the PF mechanism as well as TAT mechanism becomes influential mechanism with regard to the charge loss of the floating gate. Secondly, the effect of temperature to the charge loss is examined. Fig. 9 shows the normalized ratio of ΔV th for both mechanisms at each temperature for samples S1 and S2. The ratio indicates the induction of ΔV th compared with that at 300 K for each mechanism. As shown in Fig. 9, the ratio of the TAT mechanism increases only slightly as temperature increases, while the ratio of the PF mechanism has a larger variation than TAT mechanism. In other words, as the temperature increases,
LIM et al.: CHARGE LOSS MECHANISMS FOR NANOSCALE NAND FLASH MEMORY 323 Fig. 9. The ratio of TAT and PF mechanisms according to temperature for samples (a) S1 and (b) S2. Fig. 10. Arrhenius plots of samples (a) S1 and (b) S2 with E a values of TAT and PF mechanisms using the simulation results. the portion of the PF mechanism increases, but the portion of the TAT mechanism relatively decreases. The reason why the portion of each mechanism is changed with varying temperature is related with the temperature parameter of PF mechanism. Current density of PF mechanism exponentially depend on the temperature parameter and it is related with time constant (τ) of trap sites. The time constant of PF decreases when temperature goes up and it makes easier for charges to emit the filled trap sites. However, the time constant of TAT has only dependency with not temperature but the distance between two interfaces [19]. Accordingly, the PF portion increases relatively that of TAT. This indicates that PF, which uses the thermal excitation gradually, becomes an important factor with TAT as temperature increases in the intrinsic characteristic of NAND flash memory. Of course, in TAT, the current density also increases due to the shallow trap sites add to the mechanism. However, it is relatively low because the effect of temperature to the PF is exponential function. Based on these simulation results, we have drawn Arrhenius plots, as shown in Fig. 10. The activation energy values of PF using 1/T model are very similar to the standard value [20]. However, in case of TAT, it is a little impractical extraction of activation energy by just using a single line because the Arrhenius plot represents the curved line which has different activation energy at low and high temperature since the activation energy increases with temperature. It is generally explained using deep and shallow traps. In general, the deep traps which align with the average energy level of the electrons in the FG contribute to loss of stored charges [12]. As temperature increases, shallow traps which have strong temperature acceleration gradually attend to the leakage characteristic and more traps can be used for the conductive traps to TAT mechanism [7], [19]. Therefore, the V th degradation is generated faster than at the situation of low temperature due to the characteristic of TAT mechanism. Finally, the roll-off E a is generated at high temperature like a T model [5], [7].
324 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 15, NO. 3, SEPTEMBER 2015 IV. CONCLUSION In this paper, we proposed the intrinsic charge loss mechanisms for the nano-scale FG NAND flash memory. We found that the degradation characteristic of the nano-scale devices cannot be sufficiently explained by only one mechanism as the scaling down was progressed. The combination of the TAT and PF mechanisms satisfactorily explained the charge loss of the floating gate according to the bake time at various temperatures and thicknesses. The portion of each mechanism changed in accordance with the temperature and the EOT of the ONO. As the temperature increased, the portion of PF increased based on the time constant characteristic of each mechanism. As the EOT of the ONO decreased, the PF mechanism also became an important leakage factor of the retention characteristic with the TAT mechanism. Therefore, for the nano-scale FG NAND flash memory or even modern 3D NAND flash memory, these data trends allow more accurate prediction of the retention characteristic of memory cells. REFERENCES [1] K. Naruke, S. Taguchi, and M. Wada, Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness, in Proc. IEDM, 1988, pp. 424 427. [2] S. Mori et al., ONO inter-poly dielectric scaling for nonvolatile memory applications, IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 386 391, Feb. 1991. [3] B. Salvo, G. Ghibaudo, G. Pananakakis, and B. Guillaumot, Investigation of low field and high temperature SiO 2 and ONO leakage currents using the floating gate technique, J. Non-Cryst. Solids, vol. 245, pp. 104 109, Feb. 1999. [4] K. Wu, C.-S. Pan, J. J. Shaw, P. Frelberger, and G. Sery, A model for EPROM intrinsic charge loss through oxide nitride oxide (ONO) interpoly dielectric, in Proc.Int.Reliab.Phys.Symp., 1990, pp. 145 149. [5] B. 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Soin, Dependency of threshold voltage on floating gate and inter-polysilicon dielectric thickness for nonvolatile memory devices, in Proc. Int. Conf. Semicond. Electron., 2010, pp. 83 87. [16] J. D. Lee, S. H. Hur, and J. D. Choi, Effects of floating-gate interference on NAND flash memory cell operation, IEEE Electron Device Lett., vol. 23, no. 5, pp. 264 266, May 2002. [17] B. L. Yang, P. T. Lai, and H. Wong, Conduction mechanisms in MOS gate dielectric films, Microelectron. Reliab., vol. 44, no. 5, pp. 709 718, May 2004. [18] L.-C. Hu, A.-C. Kang, J. R. Shih, Y.-F. Lin, K. Wu, and Y.-C. King, Statistical modeling for postcycling data retention of split-gate Flash memories, IEEE Trans. Device Mater. Rel., vol. 6, no. 1, pp. 60 66, Mar. 2006. [19] Y. Yang and M. H. White, Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures, Solid-State Electron., vol. 44, no. 6, pp. 949 958, Jun. 2000. [20] H. Garcia et al., Influence of interlayer trapping and detrapping mechanisms on the electrical characterization of hafnium oxide/silicon nitride stacks on silicon, J. Appl. Phys., vol. 104, no. 9, 2008, Art. ID. 094107. Jun Yeong Lim (S 11) received the B.S. degree in electrical and electronic engineering from Yonsei University, Seoul, Korea, where he is currently working toward the joint M.S./Ph.D. degree in electrical and electronic engineering. His research interests include characterization, modeling, and simulation of semiconductor devices and statistical modeling of semiconductor devices using technology computer-aided design. Pyung Moon (S 07) received the B.S. and M.S. degrees in electrical and electronic engineering in 2007 and 2009, respectively, from Yonsei University, Seoul, Korea, where he is currently working toward the Ph.D. degree with the Department of Electrical and Electronic Engineering. His research interests include nonlinear modeling and statistical variations of semiconductor processes and characterization of high-k dielectrics. Sang Myung Lee (S 13) received the B.S. degree in electronic communication engineering in 2013 from Hanyang University, Seoul, Korea, where he is currently working toward the joint M.S./Ph.D. degree in electrical and electronic engineering. His research interests include characterization, modeling, and simulation of semiconductor devices and statistical modeling of semiconductor devices using technology computer-aided design. Keum-Whan Noh received the Ph.D. degree from Seoul National University, Seoul, Korea, in 1999. He joined SK Hynix Semiconductor Inc., Chungcheongbuk, Korea, in 2000. His main research activities focus on the reliability of Flash memory cell.
LIM et al.: CHARGE LOSS MECHANISMS FOR NANOSCALE NAND FLASH MEMORY 325 Tae-Un Youn received the B.S. degree from Inha University, Incheon, Korea, in 1998. He joined SK Hynix Semiconductor Inc., Chungcheongbuk, Korea, in 1998. He is currently participating in the Flash memory reliability. Jong-Wook Kim received the M.S. degree from Seoul National University, Seoul, Korea, in 2010. He joined SK Hynix Semiconductor Inc., Chungcheongbuk, Korea, in 2010. He is currently participating in the Flash memory reliability. Ilgu Yun (SM 03) received the B.S. degree in electrical engineering from Yonsei University, Seoul, Korea, in 1990 and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 1995 and 1997, respectively. He was previously a Research Fellow at the Microelectronics Research Center, Georgia Institute of Technology, during 1997 1999; a Senior Research Staff at the Electronics and Telecommunications Research Institute, Daejeon, Korea, during 1999 2000; and a Visiting Scholar at the Department of Industrial and Manufacturing Engineering, University of Wisconsin-Milwaukee, Milwaukee, WI, USA, during 2006 2007. He is currently a Professor of electrical and electronic engineering at Yonsei University. He was an Associate Dean of International Affairs for the College of Engineering, Yonsei University. He is currently with the Department Head of Electrical and Electronic Engineering, Yonsei University. His research interests include material characterization, statistical (and nonlinear) modeling and variations of semiconductor processes, devices, and IC modules and process modeling, control, and simulation applied to computer-aided manufacturing of integrated circuits. Prof. Yun is currently an Educational Activity Chair in the IEEE SSCS Seoul Chapter and an Editor of the Korean Electrical and Electronic Material Engineers (KIEEME) and the Institute of Electronics Engineers in Korea (IEEK).