P-M-IO igital IO Module User Manual This document contains information on the IO digital IO module for the RS P system. Version v.0, 0/0/00
P-M-IO Manual ontents. igital IO Module. igital Outputs.... Using Multiple igital IO Modules.... Software rivers or igital Module.... igital IO Module onnectors..... 00m Outputs..... I PIO Outputs (m)..... I PIO Inputs (unprotected)..... Protected igital Inputs..... Location Of Module Jumpers nd onnectors.... etailed Notes On onfiguring The IO Module or Use..... IO ompatibility..... ontrolling The IO igital I/O Module..... igital Outputs..... igital Inputs..... Mapping Of PU Peripheral Pins To The igital Module.... Setting The Jumpers nd Solder ridges.... igital IO Module Jumper Settings... lectrocomponents plc Page
P-M-IO Manual. igital IO Module The digital module provides a means to apply digital signals to the M and drive world devices from it. There are input channels with overvoltage protection and optional pull-ups, plus another TTL inputs accessible only via I. outputs are present each with a current drive capability of 00m, plus another, m logic outputs. The first inputs and outputs are derived from the M (where possible), although the protected input stages and high-current output stages can be connected to the I IO expander also. The input I ports can generate an interrupt request. This is disabled by default as it could result in a high PU interrupt loading. n R colour L may be fitted for experimental purposes. igital Outputs The 00m outputs are simple low-side drives and are in the O state at power-up. They are designed to drive relays and solenoids and in fact can sink up to but the user may need to attach a mini-heatsink to the driver I if high duty ratios are expected. It is up to the user to program the digital output pins of the PU to a logic to turn the outputs on. There is a net inversion through the drivers so that a logic at the PU output pin will result in a low (i.e. current sink enabled) at the output connector. The user is provided with a software suite of drivers to allow the pins of the IO module to be controlled both by I and also via direct port manipulation of the MU s IO pins. ll of the Ms provided by itex provide software support for the igital IO Module epending on the PU module being used, not all of the inputs and outputs can be controlled independently. This is due to a potential shortage of IO pins on the PU itself. In such cases, the duplicated or unavailable channels should be routed to one of the two I PIO devices to make up the shortfall.. Using Multiple igital IO Modules Up to igital IO Modules may be fitted to a single baseboard ( if no PU is fitted). Typically, the first module would make use of the PU module s own port pins. Other modules would rely on the I PIO devices for their connection to the PU. The full I slave address variations is available to all these devices (via solder links on the M). The user must make sure that there are no conflicts on IO pins on the backplane when more than one module is fitted. lternatively, all digital IO modules could use I, freeing up PU pins for other purposes. Where a second P baseboard is available, the I_N_0 I bus can be used to connect further digital IO modules.. Software rivers or igital Module The module has two I PIO devices, both of which require special software drivers to access. These are provided for each of the PU Modules. The software allows for control from both I bus commands and also via direct port control from the PU. lectrocomponents plc Page
P-M-IO Manual. igital IO Module onnectors.. 00m Outputs X0 escription X0 escription O0 output O output O output O output O output O0 output O output O output O output 0 O 00m output O output O 00m output O output O 00m output O output O 00m output O_L logic output O_L logic output O_L logic output 0 O 00m output PU Vcc V PU Vcc +V Note: lthough the outputs O0 O are rated at mp you should take care that the maximum total ULN00 power dissipation is not exceeded... I PIO Outputs (m) X0 escription X0 escription PIO OUT_P00 PIO OUT_P0 PIO OUT_P0 PIO OUT_P PIO OUT_P0 PIO OUT_P PIO OUT_P0 PIO OUT_P PIO OUT_P0 0 PIO OUT_P PIO OUT_P0 PIO OUT_P PIO OUT_P0 PIO OUT_P PIO OUT_P0 PIO OUT_ PU Vcc +V +V 0 S lectrocomponents plc Page
P-M-IO Manual.. I PIO Inputs (unprotected) X0 escription X0 escription PIO IN_P00 PIO IN_P0 PIO IN_P0 PIO IN_P PIO IN_P0 PIO IN_P PIO IN_P0 PIO IN_P PIO IN_P0 0 PIO IN_P PIO IN_P0 PIO IN_P PIO IN_P0 PIO IN_P PIO IN_P0 PIO IN_P PU Vcc +V +V 0 S.. Protected igital Inputs X0 escription X0 escription I0 input I input I input I input I input I0 input I input I input I input 0 I input I input I input I input I input I input I input PU Vcc +V +V 0 S lectrocomponents plc Page
P-M-IO Manual.. Location Of Module Jumpers nd onnectors Top View ottom View lectrocomponents plc Page
P-M-IO Manual. etailed Notes On onfiguring The IO Module or Use.. IO ompatibility The IO module has been designed as a universal module which can accept any processor modules designed for the P system. s such it is important to note that there are a few limitations which the user needs to be aware of. You must check that the IO is correctly configured for your PU before fitting it to the P baseboard!.. ontrolling The IO igital I/O Module This module can be controlled by the PU in several ways. On board the module are two independent serial I/O latch devices. ach of these devices has an input mode and an output mode function. The P has been designed such that one device is dedicated to output mode and the other device is dedicated for input mode. The chip used is the NXP P device. The P device can be controlled via the I0 channel on the PU via the back plane. This I0 channel is referred to as the NTRL I channel on the aseboard. ach of the two P devices has its own unique I address to communicate on... igital Outputs The P device can be used to output data, the raw logic level output signals for this are referred to as OUT_P0(x) and OUT_P(x) where x = 0 to. These signals are available to probe on connector X0, and there are logic level outputs in total. These raw logic level outputs can be fed into a high current arlington driver of the type ULN00. This however is a board option and the user has to configure the board to do this via a series of solder bridges. These bridges are 0-0 and 0-0. heck the board to ensure they are configured how you want them. The arlington drive output from the ULN00 appears on another connector X0, as signal O(y) where y = 0 to. Note the output drive of O(0)-O() is double that of O()-O(), due to the way the hardware has been implemented. The PU also has some direct I/O capability and this feature is bought out onto the aseboard. The igital I/O Module has access to these signals and the user can use these rather than the signals produced by the I P digital latches. On the igital I/O Module these signals are referred to as P_O(y) where y = 0 to. The mapping between the PU s port pins and the Output on the 0(y) pins is given later... igital Inputs The igital I/O Module can also read in external input signals via an input buffer. The real world signals are referred to as I(y) where y = 0 to. Signals I(0) to I() have an input protection stage and hex Schmitt trigger inverting buffer input whilst signals I() to I() have a different input protection arrangement. There are no buffers or inversion of these signals. The input signals after the protection stage can be routed via jumper links to either the serial input latches or to the STR MU I/O pins. Jumpers J00 and J0 provide routing for inputs I(0) to I() whilst input I() to I() have no routing capability and are fed directly into one of the P serial latch device. The signals which are passed into the latches are referred to as IN_P0(x) and IN_P(x) where x = 0 to, whilst the signals which pass directly into the MU pins are referred to as P_I(z) where z=0 to. lectrocomponents plc Page
P-M-IO Manual There is no problems at all when the devices are configured as serial latch input device, although it s worth noting that the same logic level when presented to I(0) to I() will read differently when presented to I() to I(). This is because the I(0) to I() inputs have the Schmitt inverter in series with them. When the link options are organised for direct input digital reading it s worth noting that there may be a share conflict with other modules that may require these I/O pins as output pins... Mapping Of PU Peripheral Pins To The igital Module The mapping of the various PU modules to the backplane is different for each PU Module. This means the digital IO Module appears slightly differently for each M that is fitted. n example of the mapping is shown below for two PU modules. The provided software allows for easy reading and writing of values to the igital IO Module. The software is different for each ommand Module. X Pin llocation STR Pin llocation P M IO llocation Vcc to Vcc V or V, Vcc V or V, supplied by M supplied by M P. P. IRQ_PIO_I N0 INT P. P. IRQ_PIO_NTRL I INT P./IO P.0 P_O P./IO P. P_O P./IO P. P_O P./IO P. P_O P./IO P. P_O P./IO P. P_O P./IO P. P_O P.0/0IO P.0 P_O P./IO P. P_O P./IO P. P_O P./IO P. P_O 0 P./IO P. P_O0 0 P./IO P. P_O P./IO P.0 P_O0 P. P. P_I igital igital igital Vcc V from reg V from baseboard V from baseboard regulator regulator Vcc V from reg V from baseboard V from baseboard regulator regulator V Power V Power V Power V Power V Power V Power +V +V +V +V +V +V lectrocomponents plc Page
P-M-IO Manual X Pin llocation STR Pin llocation P M IO llocation Vcc to Vcc V or V, Vcc V or V, supplied by M supplied by M P./IO P.0 N P./IO P0. P_O P./IO P. P_O P.0/IO P. P_O P./IO P. P_O P./IO P. P_O P./IO P. P_I P./IO P. P_I P./IO P. P_I P./IO P. P_I P./IO P. P_I P./IO P. P_I P./0IO P. (PY disabled) P_I P./IO (S00 INT) P.0 P_I PL./IO P0. (PY disabled) P_I0 PL./IO P0. (PY disabled) P_I P.0/IO P0. (PY disabled) P_I0 igital igital igital Vcc V from reg V from baseboard V from baseboard regulator regulator Vcc V from reg V from baseboard V from baseboard regulator regulator V Power V Power V Power V Power V Power V Power +V +V +V +V +V +V X Pin llocation STR Pin llocation P M IO llocation Vcc V from reg Vcc V from reg Vcc V from reg Vcc V or V, supplied by PU Vcc V or V, supplied by PU Vcc V or V, supplied by PU Vcc V from reg Vcc V from reg Vcc V from reg SL P.0 PON. S P. PON. SL P. PON. S P. PON. igital igital igital Note: The shaded signals are not available with certain PU modules. These inputs and outputs are recommended to be connected to the appropriate I PIO device rather than relying on the PU s own port pins.. Setting The Jumpers nd Solder ridges To make the igital I/O Module compatible with direct MU drive from the I/O pins the solder jumpers mentioned above, 0-0 and 0-0 need to be set accordingly. This means the user has the option to drive the output directly from the MU s or via the P serial latch depending on the jumper options. In terms of compatibility with other modules it is worth noting that the STR has on board. These channels are on Port, so there is a potentially conflicting situation when used with the nalogue Module. I.e. The analogue module will present analogue values to Port whilst Port is trying to drive lectrocomponents plc Page
P-M-IO Manual the igital Module outputs. It is therefore prudent to reserve the Port pins for analogue input whilst using the Port pins for digital output. This means having some idea of what MU system resources you will require in your design and modifying both the source code and the hardware to suite. The low level hardware drivers may therefore need to be modified when mixing modules to avoid this potential conflict. The igital I/O Module can also read in external input signals via an input buffer. The real world signals are referred to as I(y) where y = 0 to. Signals I(0) to I() have an input protection stage and hex Schmitt trigger inverting buffer input whilst signals I() to I() have a different input protection arrangement. There are no buffers or inversion of these signals. The input signals after the protection stage can be routed via jumper links to either the serial input latches or to the STR MU I/O pins. Jumpers J00 and J0 provide routing for inputs I(0) to I() whilst input I() to I() have no routing capability and are fed directly into one of the P serial latch device. The signals which are passed into the latches are referred to as IN_P0(x) and IN_P(x) where x = 0 to, whilst the signals which pass directly into the MU pins are referred to as P_I(z) where z=0 to. There is no problems at all when the devices are configured as serial latch input device, although it s worth noting that the same logic level when presented to I(0) to I() will read differently when presented to I() to I(). This is because the I(0) to I() inputs have the Schmitt inverter in series with them. When the link options are organised for direct input digital reading it s worth noting that there may be a share conflict with other modules that may require these I/O pins as output pins. lectrocomponents plc Page 0
P-M-IO Manual. igital IO Module Jumper Settings efore fitting the IO module to your P baseboard, you must configure the jumpers and solder bridges to suit the PU module you are intending to use. The possible settings are given in the following table. Jumper Type Purpose efault State efault 00 ut & Solder Set operating voltage of I PIO devices Use PU's Vcc - 0 ut & Solder Select which I channel interrupt to use with both I PIO devices I_TRL INT - 0 ut & Solder Set address bit 0 for U00 (input) I PIO device 0=0-0 ut & Solder Set address bit for U00 (input) I PIO device = - 0 ut & Solder Set address bit for U00 (input) I PIO device =0-0 ut & Solder Set address bit 0 for U0 (output) I PIO device 0= - 0 ut & Solder Set address bit for U0 (output) I PIO device = - 0 ut & Solder Set address bit for U0 (output) I PIO device =0-0 ut & Solder Select I_TRL bus or I N0 bus I_TRL - 0 ut & Solder Select I_TRL bus or I N0 bus I_TRL - 0 Solder ypass P0 Not ypassed Open Solder ypass P0 Not ypassed Open Solder onnect blue L in R array to O0 Not connected Open Solder onnect green L in R array to O0 Not connected Open Solder onnect red L in R array to O0 Not connected Open 00 ut Pull up I0 digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I digital input to IO module Pulled-up losed 0 ut Pull up I0 digital input to IO module Pulled-up losed ut Pull up I digital input to IO module Pulled-up losed ut Pull up I digital input to IO module Pulled-up losed ut Pull up I digital input to IO module Pulled-up losed ut Pull up I digital input to IO module Pulled-up losed ut Pull up I digital input to IO module Pulled-up losed = PU output option may not be available with all P PU modules lectrocomponents plc Page
P-M-IO Manual Jumpe r Type Purpose efault State efaul t 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - 0 ut & onnect ULN00 input to either PU output pin or U0 I PIO PU output - J00 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Use PU - input J00 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Use PU - input J00 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Use PU - input J00 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Use PU - input J00 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Use PU - input J00 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Use PU - input J0 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Not fitted Open J0 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Not fitted Open J0 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Not fitted Open J0 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Not fitted Open J0 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Not fitted Open J0 Jumper Route I0 input to PU digital input pin via P or to I PIO U00 Not fitted Open = PU output option may not be available with all P PU modules lectrocomponents plc Page
P-M-IO Manual IO igital I/O Module Inputs to RS P ackplane X0 igital Input onnector VM0_PIO VM_PIO VM_PIO_P VM_PIO VM_PIO VM_PIO VM_PIO VM_PIO VM_PIO VM_PIO VM0_PIO_SO_TS J00 J00 J00 J00 J00 J00 J0 J0 J0 J0 J0 0 0 I(0) I() I() I() I() I() I() I() I() I() I(0) IRQ_PIO_I_INT J0 I() IRQ_PIO_NTRL_I_INT IRQ_PIO_I_N0_INT 0 I() I() I() I() 0 NTRL I I N0 0 I ata I LK I I(0) I() can be read via I or via backplane by the MU I() I() can only be read via I. Mapping id summary of igital Input jumpers and IO configuration You can see from this diagram that inputs I(0) to I() provide the digital input pins to the system. The processed inputs are then made available on the backplane via the link options marked above as a diamond. If the inputs are required to be read via the I bus then the link can be set differently. I() to I() can only be read via the back plane and no I read option is available to them. The I interface can be selected as either NTRL_I, which is the main I bus within the RS-P system or via the I_N0 bus which is usually provided as the user own I independent I bus. Not all Ms have two I channels so the default is usually NTRL_I. Software drivers are provided for all the Ms to talk to the igital IO Modules over the I protocol. The I device can generate an interrupt if required. The user can select this interrupt source via the link options shown above. lectrocomponents plc Page
P-M-IO Manual IO igital I/O Module Outputs to RS P ackplane X0 igital Output onnector V0_PIO0 V_PIO V_PIO V_PIO V_PIO V_PIO0 V_PIO V_PIO V_PIO V0_PIO V_PIO0 V_PIO 0 0 0 0 0 0 0 0 0 0 0 0 O(0) O() O() O() O() O() O() O() O() O() O(0) O() V_PIO V_PIO V_PIO V_PIO 0 0 0 0 O() O() O() O() V_PIO V_PIO V_PIO NTRL I I N0 0 0 I ata I LK I 0 O() O() O() X00 Terminal X00 V O(0) O() are arlington outputs, controlled by either I or direct MU control O() O() are MU logic level outputs controlled only by direct MU Mapping id summary of igital Output jumpers and IO configuration s you can see from the diagram above the igital IO Module can be fed with output data either directly from the back plane signals V0 to V or via I packets from the I buses. The user can select which of these two he wishes to use via the link options shown in the diamonds above. The diagram shows the same I bus interface which can be selected to be the same as the input module. i.e. NTRL_I or I_N0 Note also the large X00 ground terminal which can be used to terminate large high current switching loads. s the backplane connections are only rated for up to, for higher current loads the user should connect the high side load to the IO pin and use the X00 ground terminal for the return current from the load. Software drivers are provided for each M to talk directly to the igital IO Outputs both by I and also by direct MU port control. lectrocomponents plc Page
0 P igital I/O Module RS-P-IO- [] ontents [] onnectors [] I to bit us; Ls [] Input Protection [] Output rivers (Part ) [] Output rivers (Part ) Rev. ate Name 0.0.00 r hitex VLOPMNT TOOLS Title ontents This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating oard this stipulation will result in the liability to pay damages. ll rights reserved in case of a patent registration or registered design. ile modified 0.0.00 :0:00 RS-P-IO- 0 Sheet 0 of 0
0, OUT_P0 +V O O[0] O[] O[] O[] O[] O[] O[] O[] O_L O_L OUT_P0[0] OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] P_V IN_P0 +V +V IN_P0[0] IN_P0[] IN_P0[] IN_P0[] IN_P0[] IN_P0[] IN_P0[] IN_P0[] I[0] I[] I[] I[] I[] I[] I[] I[] X0 X0 0 0 S*0/,/TSM 0 0 S*0/,/TSM X0 X0 0 0 S*/./SM 0 0 S*0/,/TSM O[] O[] O[0] O[] O[] O[] O[] O[] O_L O[] OUT_P[0] OUT_P[] OUT_P[] OUT_P[] OUT_P[] OUT_P[] OUT_P[] OUT_P[] IN_P[0] IN_P[] IN_P[] IN_P[] IN_P[] IN_P[] IN_P[] IN_P[] I[] I[] I[0] I[] I[] I[] I[] I[] +V IN_P +.V I +.V OUT_P +.V,, (Vcc supplied by M) (.V from baseboard regulator) (V from baseboard regulator) (igital ) (+V ) (+V ) X00 0 0 0 PON. P_I PON. 0 P_I[0] P_I[] P_I[] P_I 0 P_O 0 P_O[0] P_I[] P_O[] P_I[] P_O[] P_I[] P_O[] P_I[] P_O[] 0 P_I[] P_O[] P_I[] P_O[] P_I[] P_O[] P_I[] P_O P_O[] P_O[] 0 P_O[] P_O[0] P_O[] P_O[] P_O[] P_O[] P_O[] P_O[] P_O[] 0 P_I[0] 00 0 0 0 0 0 0 0 0 0 0 0 +.V +.V +V 0 +V (igital ) +V +V (+V ) +V +V (+V ) PV PV PV 0 PV S*0/S/MP (Vcc supplied by M) (.V from baseboard regulator) (V from baseboard regulator) Rev. ate Name 0.0.00 r (igital ) PON. PON. PON. PON. (Vcc supplied by M) (.V from baseboard regulator) +.V (V from baseboard regulator) +V (igital ) hitex 0 0 0 0 0 0 0 0 0 00 VLOPMNT TOOLS This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. ll rights reserved in case of a patent registration or registered design. Title oard onnectors (Vcc supplied by M) +.V (.V from baseboard regulator) +V (V from baseboard regulator) (igital ) RS-P-IO- ile modified 0.0.00 :0:00 0, X0 S*0/S/MP (igital ) Sheet 0 of 0
0 +V 00 P_V PON. PON. PON. PON. 0 0 +.V U0 0 00n VR VR S SL P0P 0 N S SL P_V R 0K R K R K, IN_P0 PON. PON. IN_P0[0] IN_P0[] IN_P0[] IN_P0[] IN_P0[] IN_P0[] IN_P0[] IN_P0[] OUT_P0[0] OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] N.M. 0 R00 0K P_V 00 00n *00R R00 *00R R0 P_V 0 00n *00R R0 *00R R0 V VSS 0 U0 INT_N S SL P00 P0 P0 P0 P0 P0 P0 P0 U00 V VSS 0 INT_N S SL P00 P0 P0 P0 P0 P0 P0 P0 0 PTS 0 PTS P0 P P P P P P 0 P P0 P P P P P P 0 P P_V 0 0 0,, *00R R0 *00R R0 P_V 0 0 0 *00R R0 *00R R0 IN_P IN_P[0] IN_P[] IN_P[] IN_P[] IN_P[] IN_P[] IN_P[] IN_P[] OUT_P[0] OUT_P[] OUT_P[] OUT_P[] OUT_P[] OUT_P[] OUT_P[] OUT_P[] OUT_P, +V OUT_P0, O[0] 00 R R O[] O[] P V R R R 0R SURK L_R_ O Rev. ate Name 0.0.00 r hitex I to bit us; VLOPMNT TOOLS Ls Title This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating oard this stipulation will result in the liability to pay damages. ll rights reserved in case of a patent registration or registered design. ile modified 0.0.00 :0:00 RS-P-IO- 0 Sheet 0 of 0
0 V00 V0 V0 V0 V0 V0 N N N N N N I I[0] I[] I[] I[] I[] I[] R00 00 0 0 *K K R0 0 0 K R 0 *0K R0 0K R0 0K R0 00 00n, U00 Y Y Y Y 0 Y Y PW P_I P_I[0] P_I[] P_I[] P_I[] P_I[] P_I[] J00 0 S*/,/TSM IN_P0[0] IN_P0[] IN_P0[] IN_P0[] IN_P0[] IN_P0[] IN_P0 V N V N V N N V I[] I[] I[] I[] I[0] I[] 0 K R V N N V R K 0 N V N V N V N V R0 0 0 0 *K ZMV V0 *0K R0 0K R 0K R V0 ZMV V0 ZMV V0 ZMV V0 ZMV 0 00n V ZMV U0 Y Y Y Y 0 Y Y PW P_I[] P_I[] P_I[] P_I[] P_I[0] P_I[] 0 J0 S*/,/TSM IN_P0[] IN_P0[] IN_P[0] IN_P[] IN_P[] IN_P[] IN_P I I[] I[] I[] I[] R0 *K R0 *0K ZMV V V ZMV ZMV V0 ZMV V R R R R 0R 0R 0R 0R n 0 n 0 n 0 n 0 IN_P[] IN_P[] IN_P[] IN_P[] IN_P V ZMV ZMV V ZMV V0 ZMV V ZMV V ZMV V Rev. ate Name 0.0.00 r hitex VLOPMNT TOOLS Title Input Protection This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating oard this stipulation will result in the liability to pay damages. ll rights reserved in case of a patent registration or registered design. ile modified 0.0.00 :0:00 RS-P-IO- 0 Sheet 0 of 0
0 O0-L O-L O-L O-L P_O OUT_P0 R00 *K +V U0 OM O, P_O[0] P_O[] P_O[] P_O[] 0 0 0 0 OUT_P0[0] OUT_P0[] OUT_P0[] OUT_P0[] V O[0] O[] O[] 0 O[] ULN00 O-L O-L O-L O-L +V R0 *K U0 OM P_O[] P_O[] P_O[] P_O[] 0 0 0 0 OUT_P0[] OUT_P0[] OUT_P0[] OUT_P0[] V 0 ULN00 O[] O[] O[] NN X00 0 PV, LM.//0 V Rev. ate Name 0.0.00 r hitex VLOPMNT TOOLS This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. ll rights reserved in case of a patent registration or registered design. Title oard Output rivers (Part ) RS-P-IO- ile modified 0.0.00 :0:00 0 Sheet 0 of 0
0 O-L O-L O0-L O-L +V, P_O P_O[] P_O[] P_O[0] 0 0 0 OUT_P[0] OUT_P[] OUT_P[] OUT_P R00 *K NN U0 OM ULN00 V 0 O[] O[] O[] O[0] O P_O[] 0 OUT_P[] O-L O-L O-L O-L +V P_O[] P_O[] P_O[] P_O[] 0 0 0 0 OUT_P[] OUT_P[] OUT_P[] OUT_P[] R0 *K U0 OM V 0 ULN00 O[0] O[] O[] O[] O[] O[] K0 R K0 R K0 R P_O P_O[] P_O[] P_O[] R0 R R 00R 00R 00R O_L O_L O_L Rev. ate Name 0.0.00 r hitex VLOPMNT TOOLS This document may not be passed on, duplicated or its contents utilized, unless expressly permitted. Violating this stipulation will result in the liability to pay damages. ll rights reserved in case of a patent registration or registered design. Title oard Output rivers (Part ) RS-P-IO- ile modified 0.0.00 :0:00 0 Sheet 0 of 0
ssembly Plan Top 0 0 0 R0 0 X0 X0 S*0/,/TSM S*0/,/TSM *K X00 N V N V N V V N S*/,/TSM LM.//0 0 0 0 0 0 0 0 0 0 R00 0 R0 0 R00 0 R0 *K *K *K *K S*/,/TSM 0 0 0 0 J00 J0 U0 ULN00 ULN00 U0 U0 ULN00 ULN00 U0 L_R_ R R S*0/,/TSM X0 X0 S*/./SM 00 R 0R R R O0-L O-L O-L O-L O-L O-L O-L O-L O-L O-L O0-L O-L O-L O-L O-L O-L irectory Module Status ate / Name : : : : P Modules RS-P-IO- 0.0.00 / r Variant : -- ocument : PL Usage : external Page : / itex evelopment Tools
ssembly Plan ottom V0 V U0 ZMV N 0 R0 U00 PTS *00R *00R 00 0 0K 0 R0 R0 *00R *00R K0 R0 R R R0 00R ZMV R R V 00 N R K0 V0 n R 0 K0 V0 00R N R X0 S*0/S/MP 0 PW 0 R0 I J K *0K L M N O P W X Q R S T U V 0K 00R R 0K U00 U0 PW 00 0 0 0 0 0 N *00R *00R PTS N V00 N V0 N V0 *K R00 N V R0 *K Y Z N V N K V R N R00 R0 R0 0 V *00R *00R *0K n *0K R0 R0 R0 0 R V K 0 0 0K R00 0 0 0 V0 N 0 U0 P0P 0 X00 S*0/S/MP 0 0 00 : V0 ZMV : V0 ZMV : V0 ZMV : V0 ZMV : R0 0K : R0 0K : R K : R0 K I: R 0R J: R 0R K: 0 n L: 0 n M: R 0R N: R 0R O: V ZMV P: V0 ZMV Q: V ZMV R: V ZMV S: V ZMV T: V ZMV U: V ZMV V: V0 ZMV W: V ZMV X: V ZMV Y: R K Z: R K ll capacitors without value indication: 00n irectory Module Status ate / Name : : : : P Modules RS-P-IO- 0.0.00 / r Variant : -- ocument : PL Usage : external Page : / itex evelopment Tools