中華民國第三十一屆電力工程研討會台灣台南 00 年 月 -4 日 charged. The inductr vltage V L and V L can be derived by Figure 4(b), as shwn in Equatins () and (4). V V V L in c V

中華民國第三十一屆電力工程研討會台灣台南 00 年 月 -4 日 Vltage-Lp Cmpensatr Design fr Cnstant On-Time Cntrl Based CCM Buck-Bst Cnverter with Lw Output-Vltage Ripple Ray-Lee Lin Department f Electrical Engineering Natinal Cheng Kung University Tainan City, TAIWAN raylin@ieee.rg Wei-Cheng Chen Department f Electrical Engineering Natinal Cheng Kung University Tainan City, TAIWAN Abstract This paper presents the vltage-lp cmpensatr design fr Cnstant On-Time cntrl based CCM Buck-Bst cnverter with lw utput-vltage ripple. Due t the system in the pen-lp vltage mde cntrl, the utput-vltage is nt regulated fr different lads. Therefre, this paper aims t examine hw the principles f the cmpensatr design fr Cnstant On-Time cntrl f clsed-lp system. In rder t design the cmpensatr, SIMPLIS and MathCAD sftware will be used t analyze and design the parameters. Finally, the vltage-lp cmpensatr fr Cnstant On-Time cntrl based CCM Buck-Bst cnverter with lw utput-vltage ripple is built t verify the system stability and utput-vltage regulatin fr different lads by SIMPLIS sftware. Keywrds: vltage-lp, cmpensatr, cnstant n-time, Buck-Bst, lw utput-vltage ripple 摘要 本文主旨係提出具低輸出電壓漣波之降昇壓型電壓模式變頻控制電能轉換器之電壓迴路補償器設計 由於轉換器之輸出電壓於電壓模式開迴路控制下, 輸出電壓會因負載變動而不穩定, 使得輸出電壓無法維持定值 因此, 本文將設計一使用於變頻閉迴路控制之補償器, 以達到穩定輸出電壓之效果 首先, 利用 SIMPLIS 電路模擬軟體模擬系統之特性波德圖, 觀察分析其變頻開迴路之控制對輸出波德圖 根據此分析, 選定所需使用之補償器類型, 再輔以 MathCAD 數學運算軟體設計補償器參數諸元 最後, 利用 SIMPLIS 電路模擬軟體進行變頻閉迴路模擬, 針對補償前後加以探討其差異, 以驗證所設計之補償器可有效提升電路穩定度 關鍵字 : 電壓模式 補償器 變頻控制 降昇壓型轉換器 低輸出電壓漣波 I. INTRODUCTION Since the wide input vltage range fr many electrnic prducts, Buck-Bst cnverter is emplyed t prvide a stable utput vltage [-6]. Figure shws the cnventinal Buck-Bst cnverter [-4], the cnverter has the disadvantage f large utput vltage ripple. Fr that reasn, this paper presents the Buck-Bst cnverter with lw utput-vltage ripple, as shwn in Figure. The prpsed circuit f this paper adds an additinal inductr L and capacitr C cmpared t the cnventinal Buck-Bst cnverter. Figure shws the cmparisn f utput-vltage ripple between the cnventinal Buck-Bst cnverter and the Buck-Bst cnverter with lw utput-vltage ripple. By this figure, the circuit f this paper has smaller utput-vltage ripple than the cnventinal Buck-Bst cnverter. Figure. Cnventinal Buck-Bst cnverter [-4]. Figure. Buck-Bst cnverter with lw utput-vltage ripple [7]. Figure. Cmparisn f utput-vltage ripple. The peratinal principle f the Buck-Bst with lw utput-vltage ripple in CCM is shwn in Figure 4. A. Mde (SW On, D Off): In Figure 4(a), since the switch is turned n, the inductance L stres energy frm the input vltage, and the utput capacitance C is discharged thrugh the utput resistance R. In the ther hand, the inductance L and the capacitance C are discharged. The inductr vltage V L and V L can be derived by Figure 4(a), as shwn in Equatins () and (). V L V ( V V V ) L in c B. Mde (SW Off, D On): In Figure 4(b), since the switch is turned ff, the capacitance C c stres energy frm input vltage, and the inductance L is discharged thrugh the lad R. In the ther hand, the inductance L and the capacitance C are () ()

中華民國第三十一屆電力工程研討會台灣台南 00 年 月 -4 日 charged. The inductr vltage V L and V L can be derived by Figure 4(b), as shwn in Equatins () and (4). V V V L in c V ( V V V ) L c in Iin IC C IL (a) L L C I R V () (4) II. OPEN-LOOP CIRCUIT SIMULATION OF CONSTANT ON-TIME CONTROL The 6V utput vltage f the circuit in this paper can be applied t mnitrs, energy-efficient light bulbs, and LED string drivers. The 4put vltage f the circuit in this paper is supplied by wind turbines r trucks. Tables and shw the specificatins and the cmpnents values f the pen-lp circuit simulatin and analysis. Exercise the parameters in the Table int SIMPLIS simulatin sftware. Add a 0mΩ equivalent series resistance (ESR) in series with L, L, C, and C. When the cnverter perates in steady state, the simulatin wavefrms f the switch trigger signal V gs, the inductr current I L, the capacitr current I c, and the utput vltage V are shwn in Figure 5. Frm Figure 5, the maximum value f inductr current I L is 8.9A, and the minimum value is 5.A. Thus, the cnverter perates in CCM. Besides, the average utput vltage is -5.68V, and the utput vltage ripper is.49mv when the cnverter perates in steady state. Since the switch is turned n, the energy is stred in the inductr, the inductr current I L is increasing. When the switch is turned ff, the inductr L releases energy t the lad, the inductr current I L is decreasing. (b) Figure 4. Circuit peratin :(a) Mde, switch turns n; (b) Mde, switch turns ff. Accrding t Equatins () t (4) and vlt-secnd balance therem, the relatinship fr the vltage rati can be btained, as shwn in Equatin (5). V D (5) V D in Since the cncept f cnservatin f energy, the average inductr current I L and the inductr current variatin ΔI L can be derived, as shwn in Equatins (6) and (7). Vin D I L (6) R ( D) I L V in D T L When the minimum value f the inductr current I L is equal t zer, the minimum value f the inductr L can be derived, as shwn in Equatin (8). R T ( D) L,min Accrding t the cncept f ampere-secnd balance therem, the vltage ripper f capacitr C c can be derived, as shwn in Equatin (9). Vcc D T (9) V C R (7) (8) Table. Specificatins f Buck-Bst cnverter with lw utput-vltage ripple circuit. V ut I ut P ut f s V /V 4 V -6 V 6 A 6 W 00 khz <% Table. Cmpnents values f Buck-Bst cnverter with lw utput-vltage ripple circuit. L L C C R.8μH 0μH 400μF μf Ω Vgs / V IL / A Ic / ma V / V 5 4 0 8.5 7.5 6.5 5.5 - -4-6 -8-0 -5.676-5.68-5.684 5. 5.05 5. 5.5 5. 5.5 time/msecs 5uSecs/div Figure 5. Simulatin wavefrms f Buck-Bst cnverter with lw utput-vltage ripple circuit. Figures 6 and 7 shw the pen-lp circuit tplgy under Cnstant On-Time cntrl and the Bde plt f pen-lp cntrl-t-utput transfer functin at full lad, respectively. Table shws the measured results f the Figure 7.

中華民國第三十一屆電力工程研討會台灣台南 00 年 月 -4 日 C SW D L One-Sht L C VCO V ref R V Figure 6. Open-lp circuit tplgy under Cnstant On-Time cntrl. Figure 8 shws the adpted cmpensatr tplgy in this paper [8], which prvides tw ples and tw zers. In frequency dmain, the zers ffer phase, and the ples reduce the nise f high-frequency. In rder t imprve the system stability, the parameter values f the cmpensatr will be calculated t have desired ple and zer psitins. Table 4 shws the lcatins f desired ples and zers f the cmpensatr fr the cnverter. Since there are tw ples at abut.7khz in the Bde plt f the pen-lp cntrl-t-utput, add tw zers int the system befre.7khz t imprve the phase. Additinally, since a zer is caused by ESR at abut 0kHz in the Bde plt, put a ple int the system befre 0kHz. Finally, lcate a ple at abut 50kHz t reduce the nise f high-frequency. Accrding t the parameters f the Table 4 and Equatins (0) t (), the values f resistrs and capacitrs can be calculated by MathCAD sftware, as shwn in Table 5. Figure 9 shws the Bde plt f the adpted cmpensatr by applying the parameters in Table 5. Figure 8. Adpted cmpensatr tplgy [8]. Table 4. Lcatins f desired ples and zers f the cmpensatr. Figure 7. Bde plt f pen-lp cntrl-t-utput transfer functin at full lad. Table. Parameters f pen-lp cntrl-t-utput Bde plt at full lad. Cnstant On-Time P.M. G.M. BW DC gain @ Hz Ple Zer 4.79 8.90 db.4 khz 8.68 db.7 khz 0 khz Accrding t Table, the pen-lp system at full lad cnditin isn t stable because the phase margin is less than 45. Since the DC gain at Hz is nly 8.90dB, the impact f disturbance n the utput vltage will be increased. f z f z f p f p DC gain @ Hz 796 Hz.06kHz 7.96kHz 48.6 khz 54. db f z C ( R R ) (0) f z f p f p R C R C R ( C // C ) Table 5. Cmpnents values f cmpensatr. R R R C C C 00 kω 0 kω 00 kω nf.5 nf pf () () () III. VOLTAGE-LOOP COMPENSATOR DESIGN In this paper, a vltage-lp cmpensatr fr Cnstant On-Time cntrl based CCM Buck-Bst cnverter with lw utput-vltage ripper will be designed, which satisfy the specificatins and system stability. T analyze the system stability f the pwer cnverter, gain margin (G.M.) and phase margin (P.M.) are utilized. Figure 9. Bde plt f adpted cmpensatr.

中華民國第三十一屆電力工程研討會台灣台南 00 年 月 -4 日 IV. CLOSED-LOOP CIRCUIT SIMULATION OF CONSTANT ON-TIME CONTROL This sectin fcuses n tw parts. At first, put the cmpensatr int pen-lp Cnstant On-Time cntrl circuit t cnstruct clsed-lp systems. Secnd, cmpare with the differences between the pen-lp and clsed-lp systems in terms f the lp gain, line-t-utput, input impedance, and ut impedance as well as line and lad regulatins. Figure 0 shws the clsed-lp circuit f Cnstant On-Time cntrl with the cmpensatr. The pwer f the system is 6W in the full-lad cnditin. The clsed-lp simulatin is perfrmed by SIMPLIS sftware. Figure shws the Bde plts f pen-lp and clsed-lp cntrl-t-utput at full-lad cnditin under Cnstant On-Time cntrl. Frm the figure, after adding the cmpensatr in the system, the DC gain at Hz is increased frm 8.68dB t 55.5dB, the system bandwidth is decreased frm.4khz t.4khz, the G.M. is imprved frm 8.90dB t 5.8dB, and the P.M. is imprved frm 4.79 t 47.6. Table 6 shws the simulatin results f cntrl-t-utput at full-lad cnditin Table 6. Simulatin results f cntrl-t-utput at full-lad cnditin DC gain @ Hz BW G.M. P.M. Open-Lp 8.68 db.4 khz 8.90 db 4.79 Clsed-Lp 55.5 db.4 khz 5.8 db 47.6 Figure shws the Bde plt f cntrl-t-utput at full-lad cnditin Frm the figure, the DC gain at Hz f clsed-lp system has a 46.85dB imprvement, which increases the impact f disturbance fr the utput. Figure. Bde plt f cntrl-t-utput at full-lad cnditin Figure 0. Clsed-lp circuit f Cnstant On-Time cntrl with the cmpensatr. Figure shws the Bde plt f line-t-utput at full-lad cnditin Frm the figure, the DC gain at Hz f clsed-lp system has a 54.78dB imprvement, which reduces the influence perturbatin f surce n the utput vltage. Furthermre, the system has the ability t avid t the lw-frequency attenuatin and high-frequency perturbatin. Figure. Bde plt f line-t-utput at full-lad cnditin under Cnstant On-Time cntrl. Figure. Bde plts f cntrl-t-utput at full-lad cnditin Figure 4 shws the Bde plt f input impedance at full-lad cnditin Frm the figure, the DC gain at Hz f clsed-lp system has a.65db imprvement. When the frequency is higher the 5Hz, the input impedance f the Bde plt f pen-lp and clsed-lp are similar. Thus, impedance matching will be cnsidered when the circuit is acting as a cascaded stage. 4

中華民國第三十一屆電力工程研討會台灣台南 00 年 月 -4 日 Figure 4. Bde plt f input impedance at full-lad cnditin Figure 5 shws the Bde plt f utput impedance at full-lad cnditin Frm the figure, the DC gain at Hz f clsed-lp system has a 55.dB imprvement. When the utput impedance f the clsed-lp system is lwer than the pen-lp nes, the system lks like an ideal vltage surce, which has lw utput impedance. Figure 5. Bde plt f utput impedance at full-lad cnditin Figure 6 shws the line regulatin f Cnstant On-Time cntrl, the system f pen-lp isn t stable with the input vltage variatin frm 0V t 8V. Adding the cmpensatr int the pen-lp system, the utput vltage has been steadily at -6.05V, which t verify the cmpensatr in this paper has the ability t stabilize the system. Figure 6. Line regulatin f Cnstant On-Time cntrl. The system f pen-lp cannt stabilize with the different lads variatin frm 0% t 00%, as shwn in Figure 7. When the cmpensatr is added int the pen-lp system, the utput vltage is steadily at -6.05V, which t verify the cmpensatr has the ability t stabilize the utput vltage f the prpsed circuit. Figure 7. Lad regulatin f PWM and Cnstant On-Time cntrl. V. CONCLUSIONS In real applicatins, cmpensatr has the effect n the slew rate, stability, and nise rejectin ability. In this paper, a vltage-lp cmpensatr fr Buck-Bst cnverter with lw utput-vltage ripple has been designed. Furthermre, the stability f the system thrugh the simulatin f the pen-lp system and the analyses f the DC gain(@hz), G.M., P.M., and the bandwidth have been discussed. In this paper, the imprtance f specificatin as well as the cngruent cmpensatr design is understd. Additinally, verificatin f the crrectness and availability f the cmpensatr is perfrmed by SIMPLIS simulatin sftware and MathCAD calculatin sftware. Furthermre, the imprtance and influences f the cmpensatr parameters such as G.M., P.M., bandwidth and DC gain n the system are evaluated. Suitably parameters are designed fr the cmpensatr can make the system mre stable. ACKNOWLEDGE This wrk was spnsred by the Natinal Science Cuncil, Taiwan, under Award Numbers NSC 97--E-006-75-MY and NSC 99--E-006-. Als, this wrk made use f Shared Facilities supprted by the Prgram f Tp 00 Universities Advancement, Ministry f Educatin, Taiwan. REFERENCES [] Mhan U. Rbbins, 江炫璋譯, 電力電子學 全華科技圖書股份有限公司, 中華民國九十五年六月 [] 梁適安, 交換式電源供給器之理論與實務設計 ( 修訂版 ) 全華科技圖書股份有限公司, 中華民國九十七年九月 [] Daniel W. Hart, 王順忠譯, 電力電子學 東華書局, 中華民國八十七年二月 [4] EPARC, 電力電子學綜論 全華科技圖書股份有限公司, 中華民國九十六年二月 [5] M. H. Rashid, Pwer Electrnics:Cnverters, Applicatins and Design. [6] Rbeert W. Ericksn and Dragan Maksimvic, Fundamentals f Pwer Electrnics, Secnd Editin. [7] R. Tymerski and V. Vrperian, Generatin and Classificatin f PWM DC-t-DC Cnverters, IEEE Trans. n Aerspace and Electrnics Systems, vl. 4, n. 6, pp. 74-754, Nvember 988. [8] R. L. Lin, Special Tpics n Pwer Electrnics, Semester 009. 5