ECE 23 Digital Logic & Computer Organization Spring 28 Combinational Building Blocks Lecture 5:
Announcements Lab 2 prelab due tomorrow HW due Friday HW 2 to be posted on Thursday Lecture 4 to be replayed on Thursday Instructor office hour moved to Friday (2/9) -:3am @ Rhodes 32 (one-time change) Lecture 5: 2
Example: K-Map to Simplify SOP C AB ABC Y C A B Lecture 5: 3
Review: K-Map to Simplify POS F=π A,B,C,D (, 2, 6, 7, 8, ) CD AB Corners: B+D Other: A+B +C F=(B+D) (A+B +C ) Lecture 5: 4
Don t Cares Combinations Sometimes the output for a particular input combination is unspecified or irrelevant Such as an input combination that will never happen Represent as a d (or x ) in the truth table Example: Detect all even decimal digits except 6 Four input bits are still required, but inputs -9 would appear -5 are don t care values Lecture 5: 5
Don t Cares in Karnaugh Map Represent as a d (or x ) in the K-Map Don t cares can be used as - or -cells as needed Only circle if doing so creates a larger prime implicant (and thus a more minimal expression) Lecture 5: 6
Don t-care Example Detect all even decimal digits except 6 Inputs -5 will never occur CD AB d d d d d d F = C D + B D Lecture 5: 7
Multi-Level Logic So far we have primarily focused on two-level representations for combinational logic Multi-level logic is typically more compact (i.e., cost-efficient) in practice Lecture 5: 8
Combinational Building Blocks More complex functions built from basic gates Comparators Multiplexers Decoders Encoders Typically tens to hundreds of transistors Used to be called Medium Scale Integration (MSI) Common building blocks for digital systems Lecture 5: 9
XOR Gate XOR: X Y XÅY (XÅY) F=X Y +X Y Similar to OR gate, except when inputs are Used for comparisons, error checking, etc. XNOR: F=X Y +X Y Complemented version of XOR Lecture 5:
Equality Comparators Using XOR -bit comparator X Y different 4-bit comparator A B A B A2 B2 A3 B3 different Lecture 5:
Multiplexer ( mux ) Connects one of n inputs to the output select control signals pick one of the n sources élog 2 nù select bits Useful when multiple data sources need to be routed to a single destination Often arises from resource sharing Example: select -of-n data inputs to an adder Lecture 5: 2
2-to- Mux Selects one of two inputs to appear at the output Y = S I + S I 2-to- mux I I Y = I I I S Y S= I I Y = I S= Lecture 5: 3
4-to- Mux Selects one of four inputs to appear at the output Y = S S I + S S I + S S I2 + S S I3 I3 I2 I I 4-to- mux I3 I2 Y I I S S I3 I2 I I Lecture 5: 4
Cascading Multiplexers Large multiplexers can be implemented by cascading smaller ones S S S2??? I7 I6 I5 I4 I3 I2 I I 4: mux 4: mux 2: mux 8: mux Y I7 I6 I5 I4 I3 I2 I I 2: mux 2: mux 2: mux 2: mux 4: mux Y Lecture 5: 5
Lecture 5: 6 Any function of n variables can be implemented with a 2 n : multiplexer Logic Functions Using Muxes Cin A B 2 3 4 5 6 7 S2 8: MUX S S Cout Cout S Cin B A Cout S Cin B A Cout S Cin B A Cout S Cin B A Input variables connected to select inputs Data inputs tied to or according to truth table
Getting Away with a Smaller Mux Can use 2 n- : multiplexer and at most one inverter Connect n- input variables to select inputs Data inputs tied to,, n th variable, or inverted n th variable A B C D Y D D 8: MUX 2 3 4 5 6 7 S2 S S A B C Y Lecture 5: 7
Binary decoders n inputs, 2 n outputs Decoder Each output corresponds to a unique input value At most one output asserted at a time Example: A -to-2 decoder A Y Y Lecture 5: 8
2-to-4 Decoder A A 2:4 Decoder Y 3 Y 2 Y Y A A Y 3 A A Y 3 Y 2 Y Y Y3 = A A Y2 = A A Y = A A Y = A A Y 2 Y Y Lecture 5: 9
Logic Functions Using Decoders n:2 n decoder can be used to implement any function of n variables Connect variables to inputs Appropriate minterms summed using extra gates to form the function A B C D 5 4:6 Decoder 4 3 2 I3 I2 9 I 8 I 7 6 5 4 3 2 ABCD ABCD' ABC'D ABC'D' AB'CD AB'CD' AB'C'D AB'C'D' A'BCD A'BCD' A'BC'D A'BC'D' A'B'CD A'B'CD' A'B'C'D A'B'C'D' Lecture 5: 2
Logic Functions Using Decoders F = A B C D + AB CD + ABC D F2 = A B C + A B CD F3 = A+B+C+D = (A B C D ) A B C D 5 4:6 Decoder 4 3 2 I3 I2 9 I 8 I 7 6 5 4 3 2 ABCD ABCD' ABC'D ABC'D' AB'CD AB'CD' AB'C'D AB'C'D' A'BCD A'BCD' A'BC'D A'BC'D' A'B'CD A'B'CD' A'B'C'D A'B'C'D' F3 F F2 Lecture 5: 2
Decoder with Enable A A E 2:4 Decoder Y 3 Y 2 Y Y E A A Y 3 Y 2 Y Y X X X: don t care input Here XX covers,,, Lecture 5: 22
Decoder with Enable (2) E A A Y3 = A A E Y2 = A A E Y = A A E Y = A A E Y 3 Y 2 Y Y Lecture 5: 23
Opposite of decoders Encoders Binary encoders: 2 n inputs and n outputs Decoder Encoder Lecture 5: 24
4-to-2 Encoder Exactly one input is asserted at any given time I3 I2 I I Y Y I3 I2 I I Y Y I2 I3 I Y Y Lecture 5: 25
Priority Encoder Highest numbered inputs have priority when multiple inputs are asserted at the same time Example: 4-to-2 priority encoder I3 I2 I I Y Y None X X X X X X I3 I2 I I Y Y None Y=I3+I3 I2=I3+I2 Y=I3+I3 I2 I=I3+I2 I None=I3 I2 I I Lecture 5: 26
Example: Microprocessor Interrupts In order for devices to get service, they interrupt the microprocessor Most important requests are given priority I/O device requests power failure disk error I7 I6 I5 I4 I3 I2 I I 8:3 Priority Encoder Y2 Y Y None Microprocessor Lecture 5: 27
Before Next Class H&H 3.-3.2 Next Time Sequential Logic: Clocks, Latches, Flip-Flops Lecture 5: 28