SL74HC73 Octal 3-State Noninverting Traparent Latch High-Performance Silicon-Gate CMOS The SL74HC73 is identical in pinout to the LS/ALS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear traparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current: 1. µa High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC73N Plastic SL74HC73D SOIC T A = - to 12 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 2= CC PIN 1 = GND FUNCTION TABLE Output Enable Inputs Latch Enable D Output Q L H H H L H L L L L X no change H X X Z X = don t care Z = high impedance
SL74HC73 MAXIMUM RATINGS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to GND) -. to +7. IN DC Input oltage (Referenced to GND) -1. to CC +1. OUT DC Output oltage (Referenced to GND) -. to CC +. I IN DC Input Current, per Pin ±2 ma I OUT DC Output Current, per Pin ±3 ma I CC DC Supply Current, CC and GND Pi ±7 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -6 to +1 C T L Lead Temperature, 1 mm from Case for 1 Seconds (Plastic DIP or SOIC Package) 7 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 1 mw/ C from 6 to 12 C SOIC Package: : - 7 mw/ C from 6 to 12 C mw C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) IN, OUT DC Input oltage, Output oltage (Referenced to GND) CC T A Operating Temperature, All Package Types - +12 C t r, t f Input Rise and Fall Time (Figure 1) CC = CC = CC = This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range GND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open.
SL74HC73 DC ELECTRICAL CHARACTERISTICS(oltages Referenced to GND) Symbol Parameter Test Conditio 2 C to - C IH IL OH Minimum High-Level Input oltage Maximum Low -Level Input oltage Minimum High-Level Output oltage OUT = or CC - I OUT 2 µa OUT = or CC - I OUT 2 µa IN = IH or IL I OUT 2 µa CC 1. 3.1. 1.3.9 8 C 1. 3.1. 1.3.9 12 C 1. 3.1. 1.3.9 Unit IN = IH or IL I OUT ma I OUT 7.8 ma 3.98.48 3.84.34 3.7.2 OL Maximum Low-Level Output oltage IN = IL or IH I OUT 2 µa I IN I OZ I CC Maximum Input Leakage Current Maximum Three State Leakage Current Maximum Quiescent Supply Current (per Package) IN = IL or IH I OUT ma I OUT 7.8 ma.....4.4 IN = CC or GND ± ±1. ±1. µa Output in High-Impedance State IN = IH or IL OUT = CC or GND IN = CC or GND I OUT =µa ±. ±. ±1 µa 4. 4 16 µa
SL74HC73 AC ELECTRICAL CHARACTERISTICS(C L =pf,input t r =t f = ) Symbol Parameter 2 C to - C t PLH, t PHL t PLH, t PHL t PLZ, t PHZ t PZH, t PZL t TLH, t THL Maximum Propagation Delay, Input D to Q (Figures 1 and ) Maximum Propagation Delay,Latch Enable to Q (Figures 2 and ) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Output Traition Time, Any Output (Figures 1 and ) CC 1 16 32 27 8 C 12 C Unit C IN Maximum Input Capacitance - 1 1 1 pf C OUT Maximum Three-State Output Capacitance (Output in High-Impedance State) 1 1 6 12 1 19 2 4 34 19 19 7 1 22 4 24 48 41 22 4 22 4 9 18 1-1 1 1 pf C PD Power Dissipation Capacitance (Per Enabled Output) Used to determine the no-load dynamic power coumption: P D =C PD CC 2 f+i CC CC Typical @2 C, CC =. 23 pf TIMING REQUIREMENTS (C L =pf,input t r =t f = ) CC Symbol Parameter 2 C to - C t SU t h t w t r, t f Minimum Setup Time, Input D to Latch Enable (Figure 4) Minimum Hold Time, Latch Enable to Input D (Figure 4) Minimum Pulse Width, Latch Enable (Figure 2) Maximum Input Rise and Fall Times (Figure 1) 1 9 7 1 8 C 12 C Unit 6 11 9 19 16 7 1 11 22 19
SL74HC73 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms EXPANDED LOGIC DIAGRAM Figure. Test Circuit Figure 6. Test Circuit