MM54HC373 MM74HC373 TRI-STATE Octal D-Type Latch
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1 MM54HC373 MM74HC373 TRI-STATE Octal D-Type Latch General Description These high speed octal D-type latches utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of standard CMOS integrated circuits as well as the ability to drive 15 LS-TTL loads Due to the large output drive capability and the TRI- STATE feature these devices are ideally suited for interfacing with bus lines in a bus organized system Connection Diagram January 1988 When the LATCH ENABLE input is high the Q outputs will follow the D inputs When the LATCH ENABLE goes low data at the D inputs will be retained at the outputs until LATCH ENABLE returns high again When a high logic level is applied to the OUTPUT CONTROL input all outputs go to a high impedance state regardless of what signals are present at the other inputs and the state of the storage elements The 54HC 74HC logic family is speed function and pin-out compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to V CC and ground Features Dual-In-Line Package Typical propagation delay 18 ns Wide operating voltage range 2 to 6 volts Low input current 1 ma maximum Low quiescent current 80 ma maximum (74 Series) Output drive capability 15 LS-TTL loads MM54HC373 MM74HC373 TRI-STATE Octal D-Type Latch Truth Table Top View Order Number MM54HC373 or MM74HC373 TL F Output Latch 373 Data Control Enable Output L H H H L H L L L L X Q H X X Z H e high level L e low level Q 0 e level of output before steady-state input conditions were established Z e high impedance TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 5335 RRD-B30M105 Printed in U S A
2 Absolute Maximum Ratings (Notes1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (V CC ) b0 5 to a7 0V DC Input Voltage (V IN ) b1 5 to V CC a1 5V DC Output Voltage (V OUT ) b0 5 to V CC a0 5V Clamp Diode Current (I IK I OK ) g20 ma DC Output Current per pin (I OUT ) g35 ma DC V CC or GND Current per pin (I CC ) g70 ma Storage Temperature Range (T STG ) b65 Ctoa150 C Power Dissipation (P D ) (Note 3) 600 mw S O Package only 500 mw Lead Temp (T L ) (Soldering 10 seconds) 260 C Operating Conditions Min Max Units Supply Voltage V CC V DC Input or Output Voltage V CC V V IN V OUT Operating Temp Range (T A ) MM HC b a C MM HC b a C Input Rise or Fall Times t r t f V CC e V ns V CC e V ns V CC e V ns DC Electrical Characteristics 74HC 54HC T A e25 C Symbol Parameter Conditions V CC T A eb40 to 85 C T A eb55 to 125 C Units Typ Guaranteed Limits V IH Minimum High Level V V Input Voltage V V V V V IL Maximum Low Level V V Input Voltage V V V V V OH Minimum High Level V IN ev IH or V IL Output Voltage li OUTl s ma V V V V V V V IN ev IH or V IL V OL Maximum Low Level V IN ev IH or V IL Output Voltage li OUTl s ma V V V V V V V IN ev IH or V IL I IN Maximum Input V IN ev CC or GND V g g g ma Current I OZ Maximum TRI STATE V IN ev IH or V IL OCeV IH V g g g ma Output Leakage V OUT ev CC or GND Current I CC Maximum Quiescent V IN ev CC or GND V ma Supply Current I OUT e ma Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic N package b12 mw C from 65 C to85 C ceramic J package b12 mw C from 100 C to125 C Note 4 For a power supply of 5V g10% the worst case output voltages (V OH and V OL ) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case V IH and V IL occur at V CC e5 5V and 4 5V respectively (The V IH value at 5 5V is 3 85V ) The worst case leakage current (I IN I CC and I OZ ) occur for CMOS at the higher voltage and so the 6 0V values should be used V IL limits are currently tested at 20% of V CC The above V IL specification (30% of V CC ) will be implemented no later than Q1 C 89 2
3 AC Electrical Characteristics V CC e5v T A e25 C t r et f e6ns Symbol Parameter Conditions Typ Guaranteed Limit Units t PHL t PLH Maximum Propagation Delay Data to Q C L e pf ns t PHL t PLH Maximum Propagation Delay LE to Q C L e pf ns t PZH t PZL Maximum Output Enable Time R L e kx ns C L e pf t PHZ t PLZ Maximum Output Disable Time R L e kx ns C L e pf t S Minimum Set Up Time ns t H Minimum Hold Time ns t W Minimum Pulse Width ns AC Electrical Characteristics V CC e V C L e50 pf t r et f e6 ns (unless otherwise specified) 74HC 54HC T A e25 C Symbol Parameter Conditions V CC T A eb40 to 85 C T A eb55 to 125 C Units Typ Guaranteed Limits t PHL t PLH Maximum Propagation C L e pf V ns Delay Data to Q C L e pf V ns t PHL t PLH Maximum Propagation C L e pf V ns Delay LE to Q C L e pf V ns t PZH t PZL Maximum Output Enable R L e kx Time C L e pf V ns C L e pf V ns t PHZ t PLZ Maximum Output Disable R L e kx V ns Time V ns t S Minimum Set Up Time V ns V ns V ns t H Minimum Hold Time V ns V ns V ns t W Minimum Pulse Width V ns V ns V ns t THL t TLH Maximum Output Rise and Fall Time V ns V ns C PD Power Dissipation per latch Capacitance Note OCeV CC pf OCeGND pf C IN Maximum Input Capacitance pf C OUT Maximum Output Capacitance pf Note 5 C PD determines the no load dynamic power consumption P D ec PD V 2 CC fai CC V CC and the no load dynamic current consumption I S ec PD V CC fai CC 3
4 MM54HC373 MM74HC373 TRI-STATE Octal D-Type Latch Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC373J or MM74HC373J NS Package Number J20A LIFE SUPPORT POLIC Molded Dual-In-Line Package (N) Order Number MM74HC373N NS Package Number N20A NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 nsc com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
5 This datasheet has been download from: Datasheets for electronics components.
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