Data sheet acquired from Harris Semiconductor SCHS7A September 997 - Revised May 000 CD/7HC, CD/7HCT High Speed CMOS Logic Quad -Input OR Gate [ /Title (CD HCT, CD7 HC, CD7 HCT ) /Subject High Features Typical Propagation Delay: 7ns at = V, C L = pf, T A = o C Fanout (Over Temperature Range) - Standard Outputs............... 0 LS - Bus Driver Outputs............. LS Wide Operating Temperature Range... - o C to o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - V to 6V Operation - High Noise Immunity: N IL = 0%, N IH = 0% of at = V HCT Types -.V to V Operation - Direct LSTTL Input Logic Compatibility, = 0.8V (Max), V IH = V (Min) - CMOS Input Compatibility, I l µa at V OL, V OH Description The HC and HCT contain four -input OR gates in one package. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 0 LSTTL loads. The HCT logic family is functionally pin compatible with the standard LS logic family. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CDHCFA - to Ld CERDIP CDHCW - to Wafer CD7HCE - to Ld PDIP CD7HCM - to Ld SOIC CDHCTF - to Ld CERDIP CDHCTFA - to Ld CERDIP CD7HCTE - to Ld PDIP CD7HCTM - to Ld SOIC NOTES:. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.. Die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinout CDHC, CDHCT (CERDIP) CD7HC, CD7HCT (PDIP, SOIC) TOP VIEW A B B Y A A Y B 0 B Y 6 9 A 7 8 Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 000, Texas Instruments Incorporated.
Functional Diagram A B B Y A A Y B 0 B Y 6 9 A 7 8 Y TRUTH TABLE S na nb ny L L L L H H H L H H H H NOTE: H = High Level, L = Low Level HC Logic Symbol HCT Logic Symbol na na ny ny nb nb
Absolute Maximum Ratings DC Supply,........................ -0.V to 7V DC Input Diode, I IK For V I < -0.V or V I > + 0.V......................±0mA DC Output Diode, I OK For V O < -0.V or V O > + 0.V....................±0mA DC Output Source or Sink per Output Pin, I O For V O > -0.V or V O < + 0.V....................±mA DC or Ground, I CC or I..................±0mA Operating Conditions Temperature Range (T A )..................... - o C to o C Supply Range, HC Types.....................................V to 6V HCT Types..................................V to V DC Input or Output, V I, V O................. 0V to Input Rise and Fall Time V...................................... 000ns (Max).V...................................... 00ns (Max) 6V....................................... 00ns (Max) Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) PDIP Package................... 00 N/A CERDIP Package................ 0 SOIC Package................... 80 N/A Maximum Junction Temperature (Hermetic Package or Die)... 7 o C Maximum Junction Temperature (Plastic Package)........ 0 o C Maximum Storage Temperature Range..........-6 o C to 0 o C Maximum Lead Temperature (Soldering 0s)............. 00 o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications HC TYPES High Level Input Low Level Input Input Leakage Quiescent Device V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH - -. - -. -. - V.. - -. -. - V 6. - -. -. - V - - - - 0. - 0. - 0. V. - -. -. -. V 6 - -.8 -.8 -.8 V V OH V OL I I I CC V IH or -0.0.9 - -.9 -.9 - V -0.0.. - -. -. - V -0.0 6.9 - -.9 -.9 - V -..98 - -.8 -.7 - V -. 6.8 - -. -. - V V IH or 0.0 - - 0. - 0. - 0. V 0.0. - - 0. - 0. - 0. V 0.0 6 - - 0. - 0. - 0. V or or. - - 0.6-0. - 0. V. 6 - - 0.6-0. - 0. V - 6 - - ±0. - ± - ± µa 0 6 - - - 0-0 µa
DC Electrical Specifications (Continued) HCT TYPES High Level Input Low Level Input Input Leakage Quiescent Device Additional Quiescent Device Per Input Pin: Unit Load (Note ) V IH - -. to - -. to V OH V OL I I I CC I CC V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX - - - - V - - 0.8-0.8-0.8 V V IH or -0.0.. - -. -. - V -..98 - -.8 -.7 - V V IH or -0.0. - - 0. - 0. - 0. V and or -.. - - 0.6-0. - 0. V - - ±0. - ± - ± µa 0 - - - 0-0 µa -. to NOTE:. For dual-supply systems theoretical worst case (V I =.V, = V) specification is.8ma. HCT Input Loading Table - 00 60-0 - 90 µa UNIT LOADS All. NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 60µA max at o C. Switching Specifications Input t r, t f = 6ns HC TYPES Propagation Delay, Input to Output (Figure ) Propagation Delay, Data Input to Output Y (V) MIN TYP MAX MIN MAX MIN MAX t PLH, t PHL C L = 0pF - - 90 - - ns. - - 8 - - 7 ns 6 - - - 0 - ns t PLH, t PHL C L = pf - 7 - - - - - ns Transition Times (Figure ) t TLH, t THL C L = 0pF - - 7-9 - 0 ns. - - - 9 - ns 6 - - - 6-9 ns
Switching Specifications Input t r, t f = 6ns (Continued) Input Capacitance C I - - - - 0-0 - 0 pf Power Dissipation Capacitance C PD - - - - - - - pf (Notes, 6) HCT TYPES Propagation Delay, Input to Output (Figure ) Propagation Delay, Data Input to Output Y t RHL, t PHL C L = 0pF. - - - 0-6 ns t PLH, t PHL C L = pf - 9 - - - - - ns Transition Times (Figure ) t TLH, t THL C L = 0pF. - - - 9 - ns Input Capacitance C I - - - - 0-0 - 0 pf Power Dissipation Capacitance (Notes, 6) C PD - - - - - - - pf NOTES:. C PD is used to determine the dynamic power consumption, per gate. 6. P D = V CC f i (C PD + C L ) where f i = Input Frequency, C L = Output Load Capacitance, = Supply. (V) MIN TYP MAX MIN MAX MIN MAX Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns 0% 0%.7V.V 0.V V t THL t TLH t THL t TLH INVERTING t PHL t PLH 0% 0% INVERTING t PHL t PLH.V 0% FIGURE. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC