NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that utilize advanced silicon gate CMOS technology. It possesses the low power consumption and high noise immunity of standard CMOS integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky device. The outputs are buffered, allowing this circuit to drive 15 LS TTL loads. The large output drive capability and the 3 State feature make this part ideally suited for interfacing with bus lines in a bus oriented system. The four D type flip flops operate synchronously from a common clock. The 3 state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3 state mode when either of the two output disable pins are in the logic 1 level. The input disable allows the flip flops to remain in their present states without having to disrupt the clock. If either of the 2 inputs disables are taken to a logic 1 level, the Q outputs are fed back to the inputs, forcing the flip flops to remain in the same state. Clearing is enabled by taking the CLEAR input to a logic 1 level. The data outputs change state on the positive going edge of the clock. The 74HC logic family is functionally as well as pin out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by diodes to V CC and GND. Features: Typical Propagation Delay: 18ns Wide Power Supply Range: 2V to 6V 3 State Outputs Low Input Current: 1 A (max) Low Quiescent Current: 80 A (max) High Output Drive Current: 6mA (min) Absolute Maximum Ratings: (Note 1, Note 2) Supply Voltage, V CC... 0.5 to +7.0V DC Input Voltage, V IN... 1.5 to V CC +1.5V DC Output Voltage, V OUT... 0.5 to V CC + 0.5V Clamp Diode Current, I IK, I OK... 20mA DC Output Current (Per Pin), I OUT... 35mA DC V CC or GND Current (Per Pin), I CC... 70mA Power Dissipation (Note 3), P D... 600mW Storage Temperature Range, T stg... 65 C to +150 C Lead Temperature (During Soldering, 10sec), T L... +260 C Note 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2. Unless otherwise specified, all voltages are referenced to GND. Note 3. Power Dissipation temperature derating: 12mW/ C from +65 C to +85 C.
Recommended Operating Conditions: Parameter Symbol Min Typ Max Supply Voltage V CC 2.0 6.0 V DC Input or Output Voltage V IN, V OUT 0 V CC V Operating Temperature Range T A 55 +85 C Input Rise or Fall Times V CC = 2.0V t r, t f 1000 ns V CC = 4.5V 500 ns V CC = 6.0V 400 ns DC Electrical Characteristics: (Note 4 unless otherwise specified) Minimum High Level Input Voltage V IH 2.0 1.5 1.5 V 4.5 3.15 3.15 V 6.0 4.2 4.2 V Maximum Low Level Input Voltage V IL 2.0 0.5 0.5 V 4.5 1.35 1.35 V 6.0 1.8 1.8 V Minimum High Level Output Voltage V OH V IN = V IH or V IL I OUT 20 A V CC V CC 0.1 V CC 0.1 V I OUT 6.0mA 4.5 3.98 3.84 V I OUT 7.8mA 6.0 5.48 5.34 V Minimum Low Level Output Voltage V OL V IN = V IH I OUT 20 A 0 0.1 0.1 V I OUT 6.0mA 4.5 0.26 0.33 V I OUT 7.8mA 6.0 0.26 0.33 V Maximum Input Current I IN V IN = V CC or GND 6.0 0.1 1.0 A Maximum 3 State Output I OZ V IN = V CC or GND, Enable = V IH 6.0 0.5 5.0 A Leakage Current Maximum Quiescent Supply Current I CC V IN = V CC or GND, I OUT = 0 A 6.0 8.0 80 A Note 4. For a power supply of 5V 10% the worst case output voltages (V OH and V OL ) occur at 4.5V. Thus, the 4.5V values should be used when designing with this supply. Worst case V IH and V IL occur at V CC = 5.5V and 4.5V respectively (The V IH value at 5.5V is 3.85V). The worst case leakage current (I IN, I CC and I OZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used. AC Electrical Characteristics: (V CC = 5V, t r = t f = 6ns, C L = 15pF, unless otherwise specified) Typ Guaranteed Limits Maximum Operating Frequency f MAX 45 30 ns Maximum Propagation Delay (Clock to Q) t PHL, t PLH 31 ns Maximum Propagation Delay (Clear to Q) t PHL 18 27 ns Maximum Output Enable Time t PZH, t PZL R L = 1k 18 28 ns Maximum Output Disable Time t PHZ, t PLZ R L = 1k, C L = 5pF 16 25 ns Minimum Data Set Up Time t S 20 ns Minimum Data Enable Set Up Time t S 20 ns
AC Electrical Characteristics (Cont d): (V CC = 5V, t r = t f = 6ns, C L = 15pF, unless otherwise specified) Typ Guaranteed Limits Minimum Data Hold Time t H 0 ns Minimum Data Enable Hold Time t H 0 ns Minimum Clock Pulse Width t W 16 ns AC Electrical Characteristics: (t r = t f = 6ns, C L = 50pF unless otherwise specified) Maximum Operating Frequency f MAX 2.0 10 5 4 MHz Maximum Propagation Delay (Clock to Q) Maximum Propagation Delay (Clear to Q) 4.5 45 27 21 MHz 6.0 55 32 25 MHz t PHL, t PLH 2.0 80 175 220 ns 4.5 23 35 44 ns 6.0 21 30 38 ns C L = 150pF 2.0 110 225 280 ns 4.5 28 45 56 ns 6.0 26 38 48 ns t PHL 2.0 70 150 189 ns C L = 150pF 2.0 100 200 252 ns 4.5 25 40 50 ns 6.0 22 34 43 ns Maximum Output Enable Time t PZH, t PZL R L = 1k 2.0 70 150 189 ns C L = 150pF 2.0 100 200 252 ns 4.5 25 40 50 ns 6.0 22 34 43 ns Maximum Output Disable Time t PHZ, t PLZ R L = 1k, 2.0 70 150 189 ns Minimum Data or Data Enable Setup Time t S 2.0 100 125 ns 4.5 20 25 ns 6.0 17 21 ns Minimum Removal Time t REM 2.0 90 112 ns 4.5 18 22 ns Minimum Data or Data Enable Hold Time 6.0 15 19 ns t H 2.0 0 0 ns 4.5 0 0 ns 6.0 0 0 ns Minimum Clear or Clock Pulse Width t W 2.0 30 80 100 ns 4.5 9 16 20 ns 6.0 8 14 17 ns
AC Electrical Characteristics (Cont d): (t r = t f = 6ns, C L = 50pF unless otherwise specified) Maximum Output Rise and Fall Time t THL, t TLH 2.0 25 60 75 ns 4.5 7 12 15 ns 6.0 5 10 13 ns Maximum Input Rise and Fall Time t r, t f 2.0 1000 1000 ns 4.5 500 500 ns 6.0 400 400 ns Power Dissipation Capacitance C PD Per Flop 80 pf Maximum Input Capacitance C IN 5 10 10 pf Maximum Output Capacitance C OUT 10 20 20 pf Note 5. C PD determines the no load dynamic power consumption, P D = C PD V CC 2 f + I CC V CC, and the no load dynamic current consumption, I S = C PD V CC f + I CC. Truth Table: Inputs Data Enable Data Output Clear Clock G1 G2 D Q H X X X X L L L X X X Q O L H X X Q O L X H X Q O L L L L L L L L H H When either M or N (or both) is (are) hig the output is disabled to the high impedance state; however, sequential operation of the flip flops is not affected. H = HIGH Level (Steady State) L = LOW Level (Steady State) X = Irrelevant (any input, including transitions) = Transition from LOW to HIGH level Q O = the level of Q before the indicated steady state input conditions were established. Pin Connection Diagram Output Control M Output Control N Output 1Q Output 2Q Output 3Q Output 4Q Clock GND 1 2 3 4 5 6 7 8 V CC 16 15 Clear 14 Data Input 1D 13 Data Input 2D 12 Data Input 3D 11 Data Input 4D 10 Data Input Enable G2 9 Data Input Enable G1
16 9 1 8.870 (22.0) Max.260 (6.6) Max.200 (5.08) Max.100 (2.54).099 (2.5) Min.700 (17.78)