EE 330 Lecture 6 Improved witch-level Model Propagation elay tick iagrams Technology Files
Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain rain G Gate n-channel MOFET ource G = 0 G = 1 Conceptual view of basic switch-level model
Review from Last Time Pull-up and Pull-down Networks Concept can be extended to arbitrary number of inputs n-input NOR gate V n-input NN gate V X 1 X 1 X 2 X n X 2 X 1 X n X 2 X 1 X 2 X n X n 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time
Review from Last Time Complete Logic Family 1 2 F 1 2 F n n Family of n-input NOR gates forms a complete logic family Family of n-input NN gates forms a complete logic family Having both NN and NOR gates available is a luxury Can now implement any combinational logic function!! If add one flip flop, can implement any Boolean system!! Flip flops easy to design but will discuss sequential logic systems later
Review from Last Time Complex Gates V PUN X n PN Complex Gate esign trategy: 1. Implement in the PN 2. Implement in the PUN (must complement the input variables since p- channel devices are used) ( and often expressed in either OP or PO form)
Pull-up and Pull-down Networks Three key characteristics of tatic CMO Gates 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time X n V PUN Three properties of tatic CMO Gates (based upon simple switch-level model) PN 1. V H =V, V L =0 (too good to be true?) 2. P H =P L =0 (too good to be true?) 3. t HL =t LH =0 (too good to be true?) These 3 properties are inherent in Boolean circuits with these 3 characteristics
Review from Last Time Pass Transistor Logic B R B Requires only 1 transistor (and a resistor) - Pass transistor logic can offer significant reductions in complexity for some functions (particularly noninverting) - Resistor may require more area than several hundred or even several thousand transistors - ignal levels may not go to V or to 0V - tatic power dissipation may not be zero - ignals may degrade unacceptably if multiple gates are cascaded - resistor often implemented with a transistor to reduce area but signal swing and power dissipation problems still persist - Pass transistor logic is widely used
MOFET Modeling rain rain Gate Gate ource imple model of MOFET was developed (termed switch-level model) imple gates designed in CMO Process were introduced ome have zero power dissipation ome have or appeared to have rail to rail logic voltage swings ll appeared to be Infinitely fast Logic levels of some can not be predicted with simple model imple model is not sufficiently accurate to provide insight relating to some of these properties MOFET modeling strategy hierarchical model structure will be developed generally use simplest model that can be justified ource
MO Transistor Models 1, witch-level model rain rain Gate Gate ource ource G = 0 G = 1 G = 0 G = 1 dvantages: imple, does not require understanding of semiconductor properties, does not depend upon process, adequate for understanding basic operation of many digital circuits Limitations: oes not provide timing information (surfaced when looking at static CMO circuits, and several others that have not yet become apparent from the applications that have been considered) and can not support design of resistor used in Pass Transistor Logic
Improved evice Models With the simple switch-level model, it was observed that basic static CMO logic gates have the following three properties: evice Models and Operation Rail to rail logic swings Zero static power dissipation in both =1 and =0 states rbitrarily fast (too good to be true? will consider again with better model) It can be shown that the first two properties are nearly satisfied in actual fabricated circuits but though the circuits are fast, they are observably not arbitrarily fast Will now extend switch-level model to predict speed of basic gates
Recall MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain rain Gate n-channel MOFET ource G = 0 G = 1 This was the first model introduced and was termed the basic switch-level mode
MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain rain G Gate n-channel MOFET ource G = 0 G = 1 Conceptual view of basic switch-level model
MO Transistor Qualitative iscussion of n-channel Operation ource Gate rain Bulk Insulator rain For V G small n-channel MOFET ource Gate rain Gate Bulk Bulk Insulator ource Resistor For V G large n-channel MOFET Region under gate termed the channel When resistor is electrically created, it is termed an inversion region
MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain Insulator rain For V G small n-channel MOFET ource Gate rain Gate Bulk Bulk Insulator ource For V G large n-channel MOFET Electrically created inversion layer forms a thin film resistor Capacitance from gate to channel region is distributed Lumped capacitance much easier to work with
iscrete Resistors often use thin films too though not electrically created Thin-film spiral wound Carbon composition
Improved witch-level Model rain Gate ource G C G R W V G witch closed for V G = 1 witch-level model including gate capacitance and channel resistance till neglect bulk connection and connect the gate capacitance to the source
Improved witch-level Model rain Gate G = 1 G = 0 ource n-channel witch-level model G C G R W V G witch closed for V G = large lt: switch closed for G = 1 witch-level model including gate capacitance and channel resistance
Improved witch-level Model rain Gate G = 0 G =1 ource p-channel witch-level model G C G R W V G witch closed for V G large and neg lt: If near V, closed for G=0 witch-level model including gate capacitance and channel resistance
Improved witch-level Model rain Gate G ource R W C G V G witch closed for G =1 witch-level model including gate capacitance and channel resistance C G and R W dependent upon device sizes and process For minimum-sized devices in a 0.5u process 2KΩ n channel C G 1.5fF R sw 6KΩ p channel Considerable emphasis will be placed upon device sizing to manage C G and R W
Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf.01uf rea allocations shown to relative scale:
Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf 10fF 1fF.01uf 1pf rea allocations shown to relative scale: Not enough information at this point to determine whether this very small capacitance can be neglected Will answer this important question later
rain Model ummary (for n-channel) Gate 1, witch-level model ource G = 1 G = 0 2, Improved switch-level model G C G R W V G witch closed for V G = large witch open for V G = small Other models will be developed later
Example What are t HL and t LH? 1pf ssume V =5V With basic switch level model? With improved switch level model?
Example Inverter with basic switch-level model G p-channel Model G V n-channel Model
Example What are t HL and t LH? G p-channel Model 1pf G V n-channel Model 1pF With basic switch level model t HL =t LH =0
Example (cont) With simple switch-level model t HL =t LH =0 1pf Inverter With improved model? 1pf
Example (cont) Inverter with improved model Inverter with Improved Model G p-channel Model R Wp C Gp Inverter G V n-channel Model R Wn C Gn
Example (cont) With improved model t HL =? G p-channel Model R Wp 1pf G C Gp V n-channel Model 1pF R Wn C Gn To initiate a HL output transisition, assume has been in the high state for a long time and lower switch closes at time t=0 5V C Gp V C Gn R Wn =2K 5V 1pf C L 5V is the initial condition on C L
Example (cont) With improved model R t HL =? Wn =2K 5V C Gp C Gn 5V 1pf C L V Recognize as a first-order RC network Recall: tep response of any first-order network with LHP pole can be written as y(t) F τ I Fe where F is the final value, I is the initial value and τ is the time constant of the circuit (from Chapter 7 of Nilsson and Riedel) t For the circuit above, F=0, I=5 and R C Wn L
Example (cont) With improved model =V OUT t HL =? 5V C Gp V C Gn R Wn =2K 5V 1pf C L OUT t V (t) F I F e τ t V (t) 5e τ OUT I R C Wn L F t HL =? t HL =? t how is t HL defined?
Example (cont) V OUT R t HL =? Wn =2K 5V C Gp C Gn 5V 1pf C L V F I I/e I=5V, F=0V R C Wn L efine t τ I V (t) F F e OUT t HL t HL to be the time taken for output to drop to I/e I e F I F e t HL as defined has proved useful at analytically predicting response time of circuits t HL τ t
Example (cont) With improved model F I I/e I=5V, F=0V R C Wn L t I F e t I HL τ Ie e t 1 HL e τ e t HL τ I Fe t HL t HL t HL =R C Wn L
Example (cont) With improved model t LH =? G p-channel Model R Wp C L 1pf G C Gp V n-channel Model 1pF R Wn C Gn ssume output in low state for a long time and upper switch closes at time t=0 V OUT 5V C Gp C Gn V V =5V R Wp =6K 0V 1pf C L 0V is the initial condition on C L
Example (cont) With improved model t LH =? V OUT 5V C Gp C Gn R Wp =6K 0V 1pf V V =5V C L y(t) F τ I Fe t For this circuit, F=5, I=0 and R C Wp L
Example (cont) With improved model V OUT t LH =? 5V C Gp C Gn R Wp =6K 0V 1pf t τ I V (t) F F e OUT V V =5V C L R C Wp L t V (t) 5 1- e τ OUT F I t LH =? t LH =? t how is t LH defined?
Example (cont) V OUT With improved model F F(1-1/e) I t LH =? efine t LH as shown on figure 5V C Gp C Gn V V =5V I=0V, F=5V R C Wp L R Wp =6K 0V 1pf C L t t LH t LH as defined has proven useful for analytically predicting response time of circuits t τ I V (t) F F e OUT 1 F F Fe e τ 1 I t LH
Example (cont) With improved model t LH =? 1 F F I Fe e t 1 LH τ F1 F Fe e τ 1 t LH F(1-1/e) I F t LH I=0V, F=5V R C Wp L t 1 τ 1 1 e e t LH tlh t =R C LH Wp L
V OUT Example (cont) 5V C Gp C Gn R W 1pf With improved model V C L V OUT 5V C Gp C Gn R Wp =6K 0V 1pf V V =5V C L 2K 1pF 2n sec t R C HL Wn L 6K 1pF 6nsec t R C LH Wp L Note this circuit is quite fast! In the ON 0.5u process Note that t HL is much shorter than t LH Often C L will be even smaller and the circuit will be much faster!!
ummary: What is the delay of a minimum-sized inverter driving a 1pF load? X C L 1pF 2K 1pF 2n sec t R C HL Wn L 6K 1pF 6nsec t R C LH Wp L In the ON 0.5u process
rain Improved switch-level model Gate G ource C G R W V G witch closed for V G = large witch open for V G = small Previous example showed why R W in the model was important But of what use is the C G which did not enter the previous calculations? For minimum-sized devices in a 0.5u process C G 1.5fF R sw 2KΩ 6KΩ n channel p channel
One gate often drives one or more other gates! What are t HL and t LH?
Example: What is the delay of a minimum-sized inverter driving another identical device? X G p-channel Model R Wp? C Gp Load on first inverter C and C both 1.5fF Gn Gp G C Gn V n-channel Model R Wn C C 1.5fF Gn Gp Loading effects same whether C Gp and/or C Gn connected to V or GN C Gp +C Gn 3fF For convenience, will reference both to ground
Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf 10fF 1fF.01uf 1pf rea allocations shown to relative scale: This example will provide insight into the answer of the question
Example: What is the delay of a minimum-sized inverter driving another identical device? ssume V =5V X X 3fF
Generalizing the Previous nalysis to rbitrary Load C L t R C HL Wn L t R C LH Wp L
Example: What is the delay of a minimum-sized inverter driving another identical device? X X 3fF 2K 3 ff 6 p sec t R C HL Wn L 6K 3 ff 18 p sec t R C LH Wp L o gates really operate this fast? What would be the maximum clock rate for acceptable operation?
Example: What is the delay of a minimum-sized inverter driving another identical device? X T CLK t R C HL Wn L t R C LH Wp L 6 p 18 p sec sec What would be the maximum clock rate for acceptable operation? T = t t CLK-min HL LH 1 1 f CLK-max = = = 40GHz TCLK-min 24psec nd much faster in a finer feature process!!?????? What would be the implications of allowing for 10 levels of logic and 10 loads (FanOut=10)?
Example: What is the delay of a minimum-sized inverter driving another identical device? UMMR X X 3fF 2K 3 ff 6 p sec t R C HL Wn L 6K 3 ff 18 p sec t R C LH Wp L Note this is very fast but even the small 1.5fF capacitors are not negligable!
Response time of logic gates C L t R C HL Wn L t R C LH Wp L - Logic Circuits can operate very fast - Extremely small parasitic capacitances play key role in speed of a circuit
End of Lecture 6