ADVANCED 16M (2-Bank x 524,288-Word x 16-Bit) Synchronous DRAM FEATURES OPTIONS GENERAL DESCRIPTION APR. 2007 (Rev.2.9)
F D Read (READ) [RAS = H, CAS = L, WE = H] Write (WRITE) [RAS = H, CAS =WE = L] Chip Select: L=select, h=deselect RAS Com- CAS Com- Define Basic Com- WE Com- Precharge (PRE) [RAS = L, CAS = H, WE = L] A[10] Refresh option @refresh command Precharge Option @ precharge or read/write command Activate (ACT) [RAS = L, CAS = WE = H] Auto-Refresh (REFA) [RAS = CAS = L, WE = = H] RC Command Truth Table [1] Command Mnemonic 1. H = High Level, L = Low Level, V = Valid, X = High or Low, n = cycle number n- 1 n RAS CAS WE BA Deselect DESEL H X H X X X X X X No Operation NOP H X L H H H X X X Row Address Entry & Bank Activate ACT H X L L H H V V V Single Bank Precharge PRE H X L L H L V L X Precharge All Banks PREA H X L L H L V H X Column Address Entry & Write WRITE H X L H L L V L V Column Address Entry & Write with Auto-Precharge WRITEA H X L H L L V H V Column Address Entry & Read READ H X L H L H V L V Column Address Entry & Read with Auto-Precharge READA H X L H L H V H V Auto-Refresh REFA H H L L L H X X X Self-Refresh Entry REFS H L L L L H X X X Self-Refresh Exit REFSX L H H X X X X X X A[10 ] L H L H H H X X X Burst Terminate TBST H X L H H L X X X Mode Register Set MRS H X L L L L X L V A[9: 0]
[1] [2] Function Truth Table Current State RAS CAS WE Address [3] Command Action [4] IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST ILLEGAL [5] L H L X BA, CA, A[10] READ / WRITE ILLEGAL [5] L L H H BA, RA ACT Bank Active, Latch RA L L H L BA, A[10] PRE / PREA NOP [6] L L L H X REFA Auto-Refresh [7] L L L L Op-Code, Mode-Add MRS Mode Register Set [7] ROW ACTIVE H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST NOP L H L H BA, CA, A[10] READ / READA Begin Read, Latch CA, Determine Auto- Precharge L H L L BA, CA, A[10] WRITE / WRITEA Begin Write, Latch CA, Determine Auto- Precharge L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[10] PRE / PREA Precharge / Precharge All L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST Terminate Burst L H L H BA, CA, A[10] READ / READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge [8] L H L L BA, CA, A[10] WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge [8] L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[10] PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST Terminate Burst L H L H BA, CA, A[10] READ / READA Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge [8] L H L L BA, CA, A[10] WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge [8] L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[10] PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL
Function Truth Table [1] [2] (Continued) Current State RAS CAS WE Address [3] Command Action [4] READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A[10] READ / READA ILLEGAL L H L L BA, CA, A[10] WRITE / WRITEA ILLEGAL L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[10] PRE / PREA ILLEGAL [5] L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A[10] READ / READA ILLEGAL L H L L BA, CA, A[10] WRITE / WRITEA ILLEGAL L L H H BA, RA ACT Bank Active / ILLEGAL [5] L L H L BA, A[10] PRE / PREA ILLEGAL [5] L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL PRE -CHARGING H X X X X DESEL NOP (Idle after t RP ) L H H H X NOP NOP (Idle after t RP ) L H H L X TBST ILLEGAL [5] L H L X BA, CA, A[10] READ / WRITE ILLEGAL [5] L L H H BA, RA ACT ILLEGAL [5] L L H L BA, A[10] PRE / PREA NOP [6] (Idle after t RP ) L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING H X X X X DESEL NOP (Row Active after t RCD ) L H H H X NOP NOP (Row Active after t RCD ) L H H L X TBST ILLEGAL [5] L H L X BA, CA, A[10] READ / WRITE ILLEGAL [5] L L H H BA, RA ACT ILLEGAL [5] L L H L BA, A[10] PRE / PREA ILLEGAL [5] L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE RECOVERING H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL [5] L H L X BA, CA, A[10] READ / WRITE ILLEGAL [5] L L H H BA, RA ACT ILLEGAL [5] L L H L BA, A[10] PRE / PREA ILLEGAL [5] L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL
Function Truth Table [1] [2] (Continued) Current State RAS CAS WE Address [3] Command Action [4] REFRESHING H X X X X DESEL NOP (Idle after t RC ) MODE REGISTER SETTING 1. H = High Level, L= Low Level, X = High or Low. 2. All entries assume that was High during the preceding clock cycle and the current clock cycle. 3. BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No OPeration. 4. ILLEGAL = Device operation and/or data-integrity are not guaranteed. 5. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 6. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 7. ILLEGAL if any bank is not idle. L H H H X NOP NOP (Idle after t RC ) L H H L X TBST ILLEGAL L H L X BA, CA, A[10] READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A[10] PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Idle after t RSC ) L H H H X NOP NOP (Idle after t RSC ) L H H L X TBST ILLEGAL L H L X BA, CA, A[10] READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A[10] PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL 8. Must satisfy bus contention, bus turn around, write recovery requirements.
Function Truth Table for [1] Current State n- 1 n RAS CAS WE Add Action SELF-REFRESH [2] H X X X X X X INVALID 1. H = High Level, L= Low Level, X = High or Low. 2. Low to High transition will re-enable and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 4. Must be legal command. L H H X X X X Exit Self-Refresh (Idle after t RC ) L H L H H H X Exit Self-Refresh (Idle after t RC ) L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) POWER DOWN H X X X X X X INVALID L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Self-Refresh) ALL BANKS IDLE [3] H H X X X X X Refer to Function Truth Table ANY STATE other than listed above H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State = Power Down H H X X X X X Refer to Function Truth Table H L X X X X X Begin Suspend at Next Cycle [4] L H X X X X X Exit Suspend at Next Cycle [4] L L X X X X X Maintain Suspend
Power On Sequence RP SELF REFRESH REF REFS MODE REGISTER SET MRS IDLE REF AUTO REFRESH SUSPEND AC T POWER DOWN ROW TBST TBST WRIT REA WRITE READE WRITE READ SUSPEND WRITE WRI TE READ READ SUSPEND WRITE WRITE READE READE WRITE A SUSPEND WRITE A READ A READ A SUSPEND PRE PRE PRE POWER APPLIED POWER ON PRE PRECH ARGE Automatic Sequence Command Sequence
Mode Register RSC BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 WBL 0 Ø LTMODE BT BL LATENC Y MODE A9 ø CL BL BT = 0 BT = 1 0 0 0 1 1 0 0 1 2 2 BURST 0 1 0 4 4 LENGT 0 1 1 8 8 1 0 0 R R 1 0 1 R R 1 1 0 R R 1 1 1 Full Page R BURST 0 SEQUENTIAL Write Burst Length (WBL) TYPE 1 INTERLEAVED Length = BL specified 1 Single bit (BL = CAS 0 0 0 R 0 0 1 R 0 1 0 2 0 1 1 3 1 0 0 R 1 0 1 R 1 1 0 R 1 1 1 R RAS CAS WE BA, A[10:0] CAS Burst Length Burst Length Command READ WRITE Address Y Y DQ Q0 Q1 Q2 Q3 D0 D1 D2 D3 Burst Type Initial Address B L Column Addressing A2 A1 A0 Sequential Interleaved 0 0 0 8 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 0 0 4 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 0 2 0 1 0 1 1 1 0 1 0
OPERATIONAL DESCRIPTION Bank Activate Precharge RRD RP Command ACT ACT REA PRE ACT t RRD t RAS t RP A[9:0] Xa Xb Ya Xb A[10] Xa Xb 0 1 Xb BA 0 1 0 1 DQ Qa0 Qa1 Qa2 Qa3 Precharge All Figure 3. Bank Activation and Precharge All (BL=4, CL=3)
Read RP RCD RP Command ACT REA ACT REA PRE t RCD A[9:0] Xa Ya Xb Yb A[10] Xa 0 Xb 0 0 BA 0 0 1 1 0 Burst Length DQ Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 CAS Latency Figure 4. Dual Bank Interleaving READ (BL=4, CL=3) Command ACT READ A ACT t RCD t RP A[9:0] Xa Y Xa A[10] Xa 1 Xa BA 0 0 0 DQ Qa0 Qa1 Qa2 Qa3 Internal Precharge begins Figure 5. READ with Auto-Precharge (BL=4, CL=3) Command ACT READ A CL=3 DQ Qa0 Qa1 Qa2 Qa3 CL=2 DQ Qa0 Qa1 Qa2 Qa3 Internal Precharge Start Timing
Write RCD RDL WR RP RP Command ACT WRITE ACT WRITE PRE t RCD t RCD A[9:0] Xa Y Xb Y t RDL (1 A[10] Xa 0 Xb 0 0 BA 0 0 1 1 0 Burst Length DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Figure 7. Dual Bank Interleaving WRITE (BL=4) Command ACT WRITE ACT t RCD t RP A[9:0] Xa Y Xa A[10] Xa 1 Xa BA 0 0 0 t RDL DQ Da0 Da1 Da2 Da3 Internal Precharge Begins Figure 8. WRITE with Auto-Precharge (BL=4)
Burst Interruption [Read Interrupted by Read] Command REA REA READ READ A[9:0] Yi Yj Yk Yl A[10] 0 0 0 0 BA 0 0 1 0 DQ Qi0 Qj0 Qj1 Qk0 Qk1 Qk2 Ql0 Ql1 Ql2 Ql3 Internal Precharge Start Timing Figure 9. READ Interrupted by READ (BL=4, CL=3) [Read Interrupted by Write] Command REA WRITE A[9:0] Yi Yj A[10] 0 0 BA 0 0 DQMU, Q D Qi0 DQM U/ DQML control Dj0 Dj1 Dj2 Write control Dj 3
[Read Interrupted by Precharge] Command REA PRE DQ Q 0 Q 1 Q 2 Q 3 CL=3 Command REA PRE DQ Q 0 Q 1 Q 2 Command REA PRE DQ Q 0 Command REA PRE DQ Q 0 Q 1 Q 2 Q 3 CL=2 Command REA PRE DQ Q 0 Q 1 Q 2 Command REA PRE DQ Q 0 Figure 11. READ Interrupted by Precharge (BL=4)
[Read Interrupted by Burst Terminate] Command REA TBST DQ Q 0 Q 1 Q 2 Q 3 CL=3 Command REA TBST DQ Q 0 Q 1 Q 2 Command REA TBST DQ Q 0 Command REA TBST DQ Q 0 Q 1 Q 2 Q 3 CL=2 Command REA TBST DQ Q 0 Q 1 Q 2 Command REA TBST DQ Q 0 Figure 12. READ Interrupted by Burst Terminate (BL=4)
[Write Interrupted by Write] Command WRIT WRIT WRITE WRITE A[9:0] Yi Yj Yk Yl A[10] 0 0 0 0 BA 0 0 1 0 DQ Di0 Dj0 Dj1 Dk0 Dk1 Dk2 Dl0 Dl1 Dl2 Dl3 Figure 13. WRITE Interrupted by WRITE (BL=4) [Write Interrupted by Read] Command WRITE READ WRITE READ A[9:0] Yi Yj Yk Yl A[10] 0 0 0 0 BA 0 0 0 1 DQMU, DQ Di0 Qj0 Qj1 Dk0 Dk1 Ql0 Figure 14. WRITE interrupted by READ (BL=4, CL=3)
[Write Interrupted by Precharge] RDL Command WRITE PRE ACT A[9:0] Ya Xb A[10] 0 0 Xb BA 0 0 0 DQMU, DQ Di0 Di1 This data should be masked to satisfy t RDL requirement. Figure 15. WRITE Interrupted by Precharge (BL=4) [Write Interrupted by Burst Terminate] Command WRITE TBST A[9:0] Ya A[10] 0 BA 0 DQMU, DQ Da0 Da1 Da2
Auto Refresh RC RAS NOP or Deselect CAS WE Minimum t RC A[10:0] BA Auto Refresh on Bank 0 Auto Refresh on Bank 1 Figure 17. Auto Refresh Self Refresh RC RC RAS Stable NOP CAS WE new command A[10:0] X minimum t RC for recovery BA 0 Self Refresh Entry Self Refresh Exit
Suspend ext. int. Standby Power Down Command PRE NOP NOP NOP NOP NOP NOP NOP Active Power Down Command ACT NOP NOP NOP NOP NOP NOP NOP Figure 19. Power Down by Command WRITE REA DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3 Figure 20. DQ Suspend by
DQMU / DQML Control Command WRITE REA DQML DQ[7:0] D0 D2 D3 Q0 Q1 Q3 DQMU Masked by DQML = Disabled by DQML = DQ[15:8] D0 D1 D3 Q0 Masked by DQMU = Disabled by DQMU Figure 21. DQMU / DQML Function Q2 Q3
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings [1] Symbol Parameter Conditions Ratings Unit V DD Supply Voltage with respect to V SS -1.0 to 4.6 V V DDQ Supply Voltage for Output with respect to V SSQ -1.0 to 4.6 V V I Input Voltage with respect to V SS -1.0 to 4.6 V V O Output Voltage with respect to V SSQ -1.0 to 4.6 V I O Output Current 50 ma P D Power Dissipation T A = 25 C 1000 mw T OPR Operating Temperature Commerial 0 to 70 C Extended -25 to 85 C Industrial -40 to 85 C T STG Storage Temperature -65 to 150 C 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress r ating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not im plied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions (T A : noted by temperture options, unless otherwise noted) Symbol Parameter Min Typ Max Unit V DD Supply Voltage 3.0 3.3 3.6 V V DDQ Supply Voltage for Output 3.0 3.3 3.6 V [1] V IH High-Level Input Voltage all inputs 2.0 V DDQ + 0.3 V [2] V IL Low-Level Input Voltage all inputs -0.3 0.8 V 1. V IH (max) = 5.6 V for pulse width less than 3 ns. 2. V IL (min) = -2.0 V for pulse width less than 3 ns. DC Characteristics (V DD = V DDQ = 3.3 ±0.3V, V SS = V SSQ = 0 V, unless otherwise noted) Symbol Parameter Test Conditions Min Max Unit V OH High-Level Output Voltage I OH = -2 ma 2.4 V V OL Low-Level Output Voltage I OL = 2 ma 0.4 V I OZ Off-state Output Current Q floating V O = 0 to V DDQ -10 10!A I I Input Current V IH = 0 to V DDQ + 0.3 V -10 10!A Capacitance (V DD = V DDQ = 3.3 ±0.3 V, V SS = V SSQ = 0 V, unless otherwise noted) Symbol Parameter Test Condition Min Max Unit C I(A) Input Capacitance, address pin V I = V SS 2.5 5 pf C I(C) Input Capacitance, control pin f = 1 MHz 2.5 5 pf C I(K) Input Capacitance, pin V I = 25 mvrms 2.5 5 pf C I/O Input Capacitance, I/O pin 4 7 pf
Average Supply Current from V DD (V DD = V DDQ = 3.3 ±0.3 V, V SS = V SSQ = 0 V, unless otherwise noted) Symbol Parameter Test Conditions AC Characteristics (V DD = V DDQ = 3.3 ±0.3 V, V SS = V SSQ = 0 V, unless otherwise noted) [1] Symbol Parameter 1. Input Pulse Levels: 0.4 V to 2.4 V with t r /t f = +1/+1 ns. Input Timing Measurement Level: 1.4 V. Min -6 Max Rating (Max) I CC1S Operating Current, Single Bank t RC = min, t = min, BL = 1, CL = 3 120 ma I CC1D Operating Current, Dual Bank t RC = min, t = min, BL = 1, CL = 3 170 ma I CC2H Standby Current, = H both banks idle, t = min, = H 20 ma I CC2L Standby Current, = L both banks idle, t = min, = L 2 ma I CC3H Active Standby Current, = H both banks active, t = min, = H 35 ma I CC3L Active Standby Current, = L both banks active, t = min, = L 4 ma I CC4 Burst Current t = min, BL = 4, CL = 3, both banks active t Cycle Time CL=2 - ns CL=3 6 ns t CH High Pulse Width 2.5 ns t CL Low Pulse Width 2.5 ns t T Transition Time of 1 10 ns t IS Input Setup Time (all inputs) 2 ns t IH Input Hold Time (all inputs) 1 ns t RC Row Cycle Time 60 ns t RCD Row to Column Delay 18 ns t RAS Row Active Time 42 100k ns t RP Row Precharge Time 18 ns t CCD Column Address to Column Adress Delay 1 t RRD Act to Act Delay Time 2 t RSC Mode Register Set Cycle Time 1 t RDL Last Data-In to Row Precharge Delay 1 t REF Refresh Interval Time 65.6 ms -6 Unit 180 ma I CC5 Auto-Refresh Current t RC = min, t = min 110 ma I CC6 Self-Refresh Current < 0.2 V 1 ma Low Power 500!A Unit 1.4 Signal 1.4 Any AC timing is referenced to the input signal crossing
Switching Characteristics (V DD = V DDQ = 3.3 ±0.3 V, V SS = V SSQ = 0 V unless otherwise noted) Symbol Parameter Min t AC Access Time from CL=2 - ns -6 Max CL=3 5.5 ns t OH Output Hold Time from 2.5 ns t OLZ Delay Time, Output Low Impedance from 1 ns Unit t OHZ Delay Time, Output High Impedance from CL=2 - ns CL=3 5.5 ns V TT = 1.4V 1.4 t AC t OH t OHZ VOUT 50! V REF = - + t OLZ DQ 1.4 50 pf (1) 1.4 Output Timing Measurement Reference Point 1. For AS4C1M16S, the Output Load is 30 DQ 1.4 Figure 22. Output Load Condition
t RCD t RDL t RAS t RP t RC RAS CAS WE HIG DQMU, A[9:0] Xa Yi Xb A[10] Xa Xb BA B0 B0 B0 B0 DQ Di0 Di1 Di2 Di3 ACT WRITE PRE ACT Figure 23. WRITE Cycle (single bank) BL=4
t RDL t RDL t RCD t RCD t RAS t RRD t RAS RAS CAS WE HIG DQMU, A[9:0] Xa Ya Xb Yb A[10] Xa Xb BA B0 B0 B1 B B0 B1 DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 ACT WRIT ACT WRIT PRE PRE Figure 24. WRITE Cycle (Dual Bank) BL=4
t RCD t RAS t RP t RC RAS CAS WE DQMU, A[9:0] Xa Ya Xb A[10] Xa Xb BA B0 B0 DQ Qa0 Qa1 Qa2 Qa3 ACT READ PRE ACT Figure 25. READ Cycle (Single Bank) BL=4, CL=3
t RCD t RCD t RRD t RAS t RAS t RP t RC RAS CAS WE DQMU, A[9:0] Xa Ya Xb Yb Xc A[10] Xa Xb Xc BA DQ Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 ACT READ ACT READ PRE PRE ACT Figure 26. READ Cycle (Dual Bank) BL=4, CL=3
t RCD t RAS RAS CAS WE DQMU, A[9:0] Xa Ya Yb A[10] Xa BA DQ Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 ACT WRITE READ PRE Figure 27. WRITE to READ (Single Bank) BL=4, CL=3
t RCD t RCD t RRD t RAS t RAS t RP t WR t RC RAS CAS WE DQMU, A[9:0] Xa Ya Xb Yb Xc A[10] Xa Xb Xc BA DQ Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 ACT WRITE ACT REA PRE PRE ACT Figure 28. WRITE to READ (Dual Bank) BL=4, CL=3
t RCD t RAS RAS CAS WE DQML DQMU A[9:0] Xa Ya Yb A[10] Xa BA DQ[7:0] Da0 Da2 Da3 Qb0 Qb1 Qb3 DQ[15:8] Da0 Da1 Da3 Qb0 Qb1 Qb2 ACT WRITE READ PRE
t RCD t RDL t RAS RAS CAS WE for output disable DQMU, A[9:0] Xa Ya Yb A[10] Xa BA DQ Qa0 Qa1 Db0 Db1 Db2 Db3 PRE READ WRITE PRE Figure 30. READ to WRITE (Single Bank) BL=4, CL=3
t RCD t RCD t RRD t RAS t RAS t RP t RC t RDL RAS CAS WE for output disable DQMU, A[9:0] Xa Ya Xb Yb Xc A[10] Xa Xb Xc BA DQ Qa0 Qa1 Db0 Db1 Db2 Db3 ACT READ ACT PRE WRITE ACT PRE Figure 31. READ to WRITE (Dual Bank) BL=4, CL=3
t RCD t RDL + t RP t RC RAS CAS WE DQMU, A[9:0] Xa Ya Xb A[10] Xa Xb BA DQ Da0 Da1 Da2 Da3 ACT WRITE Internal Precharge starts this timing depends on BL ACT Figure 32. Write with Auto-Precharge BL=4
t RCD t RP t RC RAS CAS WE DQMU, A[9:0] Xa Ya Xb A[10] Xa Xb BA DQ Qa0 Qa1 Qa2 Qa3 ACT READ Internal Precharge start s @ CL=3, BL=4 this timing depends on CL and BL ACT Figure 33. Read with Auto-Precharge BL=4, CL=3
t RP t RC RAS CAS WE DC High DQMU, A[9:0] A[10] BA DQ If any bank is active, it PRE must be precharged REF S REF Figure 34. Auto-Refresh
t RP RAS CAS WE DQMU, A[9:0] A[10] BA DQ If any bank is active, it PRE must be precharged REF S Figure 35. Self-Refresh Entry
NOP or desel t RC RAS CAS WE t SRX DQMU, A[9:0] Xa A[10] Xa BA DQ Internal Re-start ACT Figure 36. Self-Refresh Exit
t RP t RSC t RCD RAS CAS WE DQMU, A[9:0] Mode Xa Ya A[10] Xa BA DQ Qa0 Qa1 Qa2 If any bank is PRE active, it must be MRS ACT READ precharged Figure 37. Mode Register Set BL=4, CL=3
PACKAGING INFORMATION V DD DQ0 DQ1 V SSQ DQ2 DQ3 V DDQ DQ4 DQ5 V SSQ DQ6 DQ7 V DDQ DQML WE CAS RAS BA A10 A0 A1 A2 A3 V DD 1 50 2 49 3 48 4 47 5 46 6 45 7 44 8 43 9 42 10 41 11 40 12 39 13 Top View 38 14 37 15 36 16 35 17 34 18 33 19 32 20 31 21 30 22 29 23 28 24 27 25 26 V SS DQ15 DQ14 V SSQ DQ13 DQ12 V DDQ DQ11 DQ10 V SSQ DQ9 DQ8 V DDQ NC DQMU NC A9 A8 A7 A6 A5 A4 V SS Figure 38. 50-Pin 400 mil TSOP II Pin Assignment
unit : mm
Ordering information Extended Temperature Range: -25C to 85C Frequency Speed(ns) Order Part # Package 166MHz 6ns AS4C1M16S-6TE 400-mil 50Pin TSOP II, Lead-Free
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