EEC 118 Lecure #15: Inerconnec Rajeevan Amiraraja Universiy of California, Davis
Ouline Review and Finis: Low Power Design Inerconnec Effecs: Rabaey C. 4 and C. 9 (Kang & Leblebici, 6.5-6.6) Amiraraja, EEC 118 Spring 010 3
Inerconnec Modeling Early days of CMOS, wires could be reaed as ideal for mos digial applicaions, no so anymore! On-cip wires ave resisance, capaciance, and inducance Similar o MOSFET carging, energy depends solely on capaciance Resisance mig impac low power adiabaic carging, saic curren dissipaion, speed Ignore inducance for all bu iges speed designs Inerconnec modeling is wole field of researc iself! Amiraraja, EEC 118 Spring 010 4
Inerconnec Models: Regions of Applicabiliy For iges speed applicaions, wire mus be reaed as a ransmission line Includes disribued series resisance, inducance, capaciance, and sun conducance (RLGC) Many applicaions i is sufficien o use lumped capaciance (C) or disribued series resisancecapaciance model (RC) Valid model depends on raio of rise/fall imes o imeof-flig along wire l: wire leng v: propagaion velociy (speed of lig) l/v: ime-of-flig on wire Amiraraja, EEC 118 Spring 010 5
Inerconnec Models: Regions of Applicabiliy Transmission line modeling (inducance significan): rise ( fall ) <.5 x (l / v) Eier ransmission line or lumped modeling:.5 x (l / v) < rise ( fall ) < 5 x (l / v) Lumped modeling: rise ( fall ) > 5 x (l / v) Amiraraja, EEC 118 Spring 010 6
Resisance Resisance proporional o leng and inversely proporional o cross secion Depends on maerial consan resisiviy ρ (Ω-m) L W ρ L ρ L L ρ R = A = W = R sq W R sq = Amiraraja, EEC 118 Spring 010 7
Parallel-Plae Capaciance Wid large compared o dielecric ickness, eig small compared o wid: E field lines orogonal o subsrae W subsrae L dielecric C = ε r WL Amiraraja, EEC 118 Spring 010 8
Fringing Field Capaciance Wen eig comparable o wid, mus accoun for fringing field componen as well W L dielecric subsrae Amiraraja, EEC 118 Spring 010 9
Toal Capaciance Model Wen eig comparable o wid, mus accoun for fringing field componen as well Model as a cylindrical conducor above subsrae dielecric W subsrae Amiraraja, EEC 118 Spring 010 10
Toal Capaciance Model Toal capaciance per uni leng is parallel-plae (area) erm plus fringing-field erm: c = c pp c fringe = ε r W πε r log ( 1) Model is simple and works fairly well (Rabaey, nd ed.) More sopisicaed numerical models also available Process models ofen give bo area and fringing (also known as sidewall) capaciance numbers per uni leng of wire for eac inerconnec layer Amiraraja, EEC 118 Spring 010 11
Amiraraja, EEC 118 Spring 010 1 Alernaive Toal Capaciance Models For wide lines (w /) Kang & Leblebici Eq. 6.53: For narrow lines (w /) Kang & Leblebici Eq. 6.54: = 1 ln W C r ε r πε r r r W C ε πε ε 1.47 1 ln 0.0543 1 =
Capaciive Coupling Fringing fields can erminae on adjacen conducors as well as subsrae Muual capaciance beween wires implies crossalk, affecs daa dependency of power dielecric subsrae Amiraraja, EEC 118 Spring 010 13
Miller Capaciance Amoun of carge moved ono muual capaciance depends on swicing of surrounding wires Wen adjacen wires move in opposie direcion, capaciance is effecively doubled (Miller effec) A B V C m ΔQ = C = C m m ( V V ) f i ( V ( V )) DD DD V C m =C m V DD C Amiraraja, EEC 118 Spring 010 14
Daa Dependen Swiced Capaciance 1 Wen adjacen wires move in same direcion, muual capaciance is effecively eliminaed A B C OR A B C = 0 C eff A B C OR A B C C = 4C eff m A A B C OR A B C B C OR A B C C = C eff m Amiraraja, EEC 118 Spring 010 15
Daa Dependen Swiced Capaciance Wen adjacen wires are saic, muual capaciance is effecively o ground 0 B 0 OR 1B 1 1B 0 OR 0B 1 0 B 1 OR 1B 0 C = C eff m 1B 1 OR 0B 0 Remember: i is e carging of capaciance were we accoun for energy from supply, no discarging Amiraraja, EEC 118 Spring 010 16
Lumped RC Model R C Simples model used o represen e resisive and capaciive inerconnec parasiics Propagaion delay (same as FET swic model): 0. 69RC PLH Amiraraja, EEC 118 Spring 010 17
RC T-Model R/ R/ C Significanly improves accuracy of ransien beavior over e lumped RC model Useful if simulaion ime is a boleneck, muc simpler an fully disribued model Amiraraja, EEC 118 Spring 010 18
Disribued RC Model R/N R/N R/N C/N C/N C/N Elmore delay approximaion for RC ladder nework: RC DN = as N Amiraraja, EEC 118 Spring 010 19
Repeaer Inserion o Reduce Wire Delay 1 N C / N C / N Inser inverers along long wires a regular inervals Breaks up resisance and capaciance, reducing delay dramaically Amiraraja, EEC 118 Spring 010 0
Summary Many imporan effecs o consider in inerconnec design Resisance, capaciance, inducance can all affec signal performance Long rise/fall ime signals, only resisance and capaciance needs o be considered Several models useful for RC inerconnec delay analysis Simple lumped (1 R, 1 C) model: easy o analyze and/or simulae, will be pessimisic T-model ( R eq = R/, 1 C): more accurae an lumped Disribued model (N R eq = R/N, N C eq = C/N): mos accurae, use Elmore delay approximaion for and analysis Amiraraja, EEC 118 Spring 010 1
Nex Topic: Design for Manufacurabiliy Parameer variaions in CMOS digial circuis Yield maximizaion and wors-case design Amiraraja, EEC 118 Spring 010