DIGITAL LOGIC CIRCUITS Introduction Logic Gates Boolean Algebra Map Specification Combinational Circuits Flip-Flops Sequential Circuits Memor Components Integrated Circuits
BASIC LOGIC BLOCK - GATE - Logic Gates Binar Digital Input Signal. Gate Binar Digital Output Signal Tpes of Basic Logic Blocks - Combinational Logic Block Logic Blocks whose output logic value depends onl on the input logic values - Sequential Logic Block Logic Blocks whose output logic value depends on the input values and the state (stored information) of the blocks Functions of Gates can be described b - Truth Table - Boolean Function - Karnaugh Map
A B COMBINATIONAL GATES Name Smbol Function Truth Table AND OR A B A B X X X X = A B or X = AB X = A + B I A X X = A Buffer A X X = A NAND NOR XOR Eclusive OR XNOR Eclusive NOR or Equivalence A B A B A B X X X X = (AB) X = (A + B) X = A B or X = A B + AB X = (A B) or X = A B + AB A B X A B X A X A X A B X A B X A B X A B X Logic Gates
BOOLEAN ALGEBRA Boolean Algebra Boolean Algebra * Algebra with Binar(Boolean) Variable and Logic Operations * Boolean Algebra is useful in Analsis and Snthesis of Digital Logic Circuits Truth Table - Input and Output signals can be represented b Boolean Variables, and - Function of the Digital Logic Circuits can be represented b Logic Operations, i.e., Boolean Function(s) - From a Boolean function, a logic diagram can be constructed using AND, OR, and INV (NOT) * The most elementar specification of the function of a Digital Logic Circuit is the Truth Table - Table that describes the Output Values for all the combinations of the Input Values, called MINTERMS - n input variables --> 2 n minterms
LOGIC CIRCUIT DESIGN Boolean Algebra Truth Table z F Boolean Function F = + z Logic Diagram z F
BASIC IDENTITIES OF BOOLEAN ALGEBRA [] + = [3] + = [5] + = [7] + = [9] + = + [] + ( + z) = ( + ) + z [3] ( + z) = +z [5] ( + ) = [7] ( ) = [2] = [4] = [6] = [8] X = [] = [2] (z) = ()z [4] + z = ( + )( + z) [6] () = + [5] and [6] : De Morgan s Theorem Usefulness of this Table - Simplification of the Boolean function - Derivation of equivalent Boolean functions to obtain logic diagrams utilizing different logic gates -- Ordinaril ANDs, ORs, and Inverters -- But a certain different form of Boolean function ma be convenient to obtain circuits with NANDs or NORs --> Applications of DeMorgans Theorem = ( + ) + = () I, AND --> NOR I, OR --> NAND Boolean Algebra
EQUIVALENT CIRCUITS Boolean Algebra Man different logic diagrams are possible for a given Function F = ABC + ABC + A C... () = AB(C + C ) + A C [3]... (2) = AB + A C [7] = AB + A C [4].... (3) () A B C F (2) A B C F (3) A B C F
COMPLEMENT OF FUNCTIONS Boolean Algebra A Boolean function of a digital logic circuit is represented b onl using logical variables and AND, OR, and Invert operators. --> Complement of a Boolean function - Replace all the variables and subepressions in the parentheses appearing in the function epression with their respective complements A,B,...,Z,a,b,...,z A,B,...,Z,a,b,...,z (p + q) (p + q) - Replace all the operators with their respective complementar operators AND OR OR AND - Basicall, etensive applications of the DeMorgan s theorem ( + 2 +... + n ) 2... n ( 2... n )' ' + 2 ' +...+ n '
SIMPLIFICATION Map Simplification Truth Table Unique Boolean Function Man different epressions eist Simplification from Boolean function - Finding an equivalent epression that is least epensive to implement - For a simple function, it is possible to obtain a simple epression for low cost implementation - But, with comple functions, it is a ver difficult task Karnaugh Map(K-map) is a simple procedure for simplifing Boolean epressions. Truth Table Boolean function Karnaugh Map Simplified Boolean Function
KARNAUGH MAP Map Simplification Karnaugh Map for an n-input digital logic circuit (n-variable sum-of-products form of Boolean Function, or Truth Table) is - Rectangle divided into 2 n cells - Each cell is associated with a Minterm - An output(function) value for each input value associated with a mintern is written in the cell representing the minterm --> -cell, -cell Each Minterm is identified b a decimal number whose binar representation is identical to the binar interpretation of the input values of the minterm. F Identification of the cell Karnaugh Map value of F F() = () F 2 3 -cell F(,) = (,2)
KARNAUGH MAP Map Simplification z F z 3 2 4 5 7 6 z z F(,,z) = (,2,4) u v w F w w uv 3 2 v 4 5 7 6 2 3 5 4 u 8 9 w uv F(u,v,w,) = (,3,6,8,9,,4)
Map Simplification MAP SIMPLIFICATION - 2 ADJACENT CELLS - Adjacent cells Rule: + = (+ ) = - binar identifications are different in one bit --> minterms associated with the adjacent cells have one variable complemented each other Cells (,) and (,) are adjacent Minterms for (,) and (,) are --> =, = --> =, = F = + can be reduced to F = From the map 2 adjacent cells and --> merge them to a larger cell F(,) = (2,3) = + =
Map Simplification MAP SIMPLIFICATION - MORE THAN 2 CELLS - u v w + u v w + u v w + u v w = u v w ( +) + u v w(+ ) = u v w + u v w = u v (w +w) = u v w uv w vw u u v v uw w uv w u v v u u v w +u v w +u vw +u vw +uvw +uvw +uv w +uv w = u v w ( +) + u vw ( +) + uvw ( +) + uv w ( +) = u (v +v)w + u(v +v)w = (u +u)w = w uv w w uv w w u v u v V u
MAP SIMPLIFICATION Map Simplification uv w (,), (,2), (,4), (,8) Adjacent Cells of Adjacent Cells of (,), (,3), (,5), (,9)...... Adjacent Cells of 5 (5,7), (5,), (5,3), (5,4) w v u F(u,v,w,) = (,,2,9,3,5) Merge (,) and (,2) --> u v w + u v Merge (,9) --> v w Merge (9,3) --> uw Merge (3,5) --> uv F = u v w + u v + v w + uw + uv But (9,3) is covered b (,9) and (3,5) F = u v w + u v + v w + uv
Map Simplification IMPLEMENTATION OF K-MAPS - Sum-of-Products Form - Logic function represented b a Karnaugh map can be implemented in the form of I-AND-OR A cell or a collection of the adjacent -cells can be realized b an AND gate, with some inversion of the input variables. z z F(,,z) = (,2,6) z z z z z z z F z z I AND OR F
Map Simplification IMPLEMENTATION OF K-MAPS - Product-of-Sums Form - Logic function represented b a Karnaugh map can be implemented in the form of I-OR-AND If we implement a Karnaugh map using -cells, the complement of F, i.e., F, can be obtained. Thus, b complementing F using DeMorgan s theorem F can be obtained F(,,z) = (,2,6) z z F = + z F = ( )z = ( + )z z F I OR AND
IMPLEMENTATION OF K-MAPS - Don t-care Conditions - Map Simplification In some logic circuits, the output responses for some input conditions are don t care whether the are or. In K-maps, don t-care conditions are represented b d s in the corresponding cells. Don t-care conditions are useful in minimizing the logic functions using K-map. - Can be considered either or - Thus increases the chances of merging cells into the larger cells --> Reduce the number of variables in the product terms d d d z z z F
COMBINATIONAL LOGIC CIRCUITS Half Adder c s Full Adder c n- c n s c n- c = c n c n- s = + = s c n = + c n- + c n- = + ( )c n- s = c n- + c n- + c n- +c n- = c n- = ( ) c n- S c n Combinational Logic Circuits c n- c s
COMBINATIONAL LOGIC CIRCUITS Combinational Logic Circuits Other Combinational Circuits Multipleer Encoder Decoder Parit Checker Parit Generator etc
MULTIPLEXER Combinational Logic Circuits 4-to- Multipleer Select Output S S Y I I I 2 I 3 I I I 2 Y I 3 S S
ENCODER/DECODER Combinational Logic Circuits Octal-to-Binar Encoder D D 2 D 3 D 4 D 5 D 6 D 7 A A A 2 2-to-4 Decoder D E A A D D D 2 D 3 d d A A E D D 2 D 3
Sequential Circuits SEQUENTIAL CIRCUITS - Registers A A A 2 A 3 Q D C Q D C Q D C Q D C Clock Shift Registers I I I 2 I 3 Serial Input Clock D C Bidirectional Shift Register with Parallel Load Q D C Q D C Q D C A A A 2 A 3 Q Serial Output Q D C Q D C Q D C Q D C 4 MUX 4 MUX 4 MUX 4 MUX Clock S S SeriaI Input I I I 2 I 3 Serial Input
MEMORY COMPONENTS Memor Components Logical Organization words (bte, or n btes) Random Access Memor N - - Each word has a unique address - Access to a word requires the same time independent of the location of the word - Organization n data input lines k address lines Read 2 k Words (n bits/word) Write n data output lines
READ ONLY MEMORY(ROM) Memor Components Characteristics - Perform read operation onl, write operation is not possible - Information stored in a ROM is made permanent during production, and cannot be changed - Organization k address input lines m n ROM (m=2 k ) Information on the data output line depends onl on the information on the address input lines. --> Combinational Logic Circuit address Canonical minterms n data output lines X =A B + B C X =A B C + A BC X 2 =BC + AB C X 3 =A BC + AB X 4 =AB X =A B C + A B C + AB C X =A B C + A BC X 2 =A BC + AB C + ABC X 3 =A BC + AB C + AB C X 4 =ABC + ABC Output ABC X X X 2 X 3 X 4
TYPES OF ROM Memor Components ROM - Store information (function) during production - Mask is used in the production process - Unalterable - Low cost for large quantit production --> used in the final products PROM (Programmable ROM) - Store info electricall using PROM programmer at the user s site - Unalterable - Higher cost than ROM -> used in the sstem development phase -> Can be used in small quantit sstem EPROM (Erasable PROM) - Store info electricall using PROM programmer at the user s site - Stored info is erasable (alterable) using UV light (electricall in some devices) and rewriteable - Higher cost than PROM but reusable --> used in the sstem development phase. Not used in the sstem production due to erasabilit
INTEGRATED CIRCUITS Memor Components Classification b the Circuit Densit SSI - MSI - LSI - VLSI - several (less than ) independent gates to 2 gates; Perform elementar digital functions; Decoder, adder, register, parit checker, etc 2 to few thousand gates; Digital subsstem Processor, memor, etc Thousands of gates; Digital sstem Microprocessor, memor module Classification b Technolog TTL - ECL - MOS - Transistor-Transistor Logic Bipolar transistors NAND Emitter-coupled Logic Bipolar transistor NOR Metal-Oide Semiconductor Unipolar transistor High densit CMOS - Complementar MOS Low power consumption