Characterization and modeling of RF-MOSFETs in the millimeter-wave frequency domain. Sadayuki Yoshitomi, Fumie Fujii

Similar documents
RF CMOS Compact modelling technologies past and future

(S&S ) PMOS: holes flow from Source to Drain. from Source to Drain. W.-Y. Choi. Electronic Circuits 2 (09/1)

The Devices. Devices

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

EKV MOS Transistor Modelling & RF Application

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

Sadayuki Yoshitomi. Semiconductor Company 2007/01/25

Lecture 37: Frequency response. Context

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

ECE 342 Electronic Circuits. 3. MOS Transistors

APPENDIX D: Binning BSIM3v3 Parameters

EE 330 Homework 5 Spring 2017 (This assignment will not be collected or graded)

EE 240B Spring Advanced Analog Integrated Circuits Lecture 2: MOS Transistor Models. Elad Alon Dept. of EECS

APPENDIX A: Parameter List

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

APPENDIX A: Parameter List

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Frequency Response Prof. Ali M. Niknejad Prof. Rikky Muller

Lecture 3: CMOS Transistor Theory

ASM-HEMT Model for GaN RF and Power Electronic Applications: Overview and Extraction

Multistage Amplifier Frequency Response

ECE 546 Lecture 10 MOS Transistors

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

Lecture 4: CMOS Transistor Theory

Simple and accurate modeling of the 3D structural variations in FinFETs

The Miller Approximation

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET )

APPENDIX D: Model Parameter Binning

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices: MOS Transistors

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Study of MOSFET circuit

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Integrated Circuit Design: OTA in 0.5µm Technology

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

MOSFET: Introduction

EE 330 Homework 5 Fall 2018 (This assignment is due Wednesday Sept 19 at 12:00 noon)

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

Different Strategies for Statistical Compact Modeling MOS-AK Dresden

RFIC2017 MO2B-2. A Simplified CMOS FET Model using Surface Potential Equations For Inter-modulation Simulations of Passive-Mixer-Like Circuits

ECE 497 JS Lecture - 12 Device Technologies

Microelectronics Part 1: Main CMOS circuits design rules

The Devices. Jan M. Rabaey

MOS Transistor Properties Review

ESE 570 MOS TRANSISTOR THEORY Part 2

6.012 Electronic Devices and Circuits Spring 2005

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations

Philips Research apple PHILIPS

Introduction and Background

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

CMOS Analog Circuits

Chapter 9 Frequency Response. PART C: High Frequency Response

The PSP compact MOSFET model An update

Transfer Gate and Dynamic Logic Dr. Lynn Fuller Webpage:

MOSFET Capacitance Model

MOS Transistor Theory

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Charge-Storage Elements: Base-Charging Capacitance C b

LEVEL 61 RPI a-si TFT Model

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

EE5311- Digital IC Design

MOS Amplifiers Dr. Lynn Fuller Webpage:

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

Lecture 23 - Frequency Resp onse of Amplifiers (I) Common-Source Amplifier. May 6, 2003

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE105 Fall 2014 Microelectronic Devices and Circuits

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

The HV-EKV MOSFET Model

Chapter 4 Field-Effect Transistors

Practice 7: CMOS Capacitance

MOS Transistor Theory

MOS Transistor I-V Characteristics and Parasitics

EE105 - Fall 2006 Microelectronic Devices and Circuits

Page 1 of (2 pts) What is the purpose of the keeper transistor in a dynamic logic gate?

Section 12: Intro to Devices

CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012

USC-ISI. The MOSIS Service. BSIM3v3.1 Model. Parameters Extraction and Optimization. October 2000

Lecture 04 Review of MOSFET

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

EE105 - Fall 2005 Microelectronic Devices and Circuits

Workshop WMB. Noise Modeling

ECE 546 Lecture 11 MOS Amplifiers

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Effects of Scaling on Modeling of Analog RF MOS Devices

ECEN 326 Electronic Circuits

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

Lecture 12: MOSFET Devices

Thin Film Transistors (TFT)

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

Integrated Circuits & Systems

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

SUPPLEMENTARY INFORMATION

Lecture 23 Frequency Response of Amplifiers (I) Common Source Amplifier. December 1, 2005

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

Transcription:

MOS-AK //03 Characterization and modeling of RF-MOSFETs in the millimeter-wave frequency domain Sadayuki Yoshitomi, Fumie Fujii Semiconductor & Storage Products Company Toshiba Corporation Copyright 03, Toshiba Corporation.

Overview Above 00Hz fmax by advanced CMOS technology is a driving force to realize millimeter-wave CMOS chips. Accurate/Automated 60Hz Measurement is needed to find a devices nature. Environmental-sensitive measurement and large local variation made modeling work very difficult. PVT model linking process and SPICE : a OAL of this work. Accurate Probing Control 3As Automatic Measurements Accurate PVT Model 35.0 L M H 34.5 ) B d ( 34.0 p 33.5 33.0 0.6 0.7 0.8 0.9 0.0 0. 0. Itotal(A)

Contents : :Demonstration of stable S-parameter automated measurement at 60 Hz. : Demonstration of simple PVT model for 60Hz region. -MOSFET - MOM Capacitor 3

Accurate Probing Control Skating Control: Reflects stability of Measurement data. Adjacent S-PAD: used to check stability check. Hz~67Hz/Hz De-embedding check: But How often? Pitch 50um 65nm RF-CMOS inch wafer 30 Dies 4

Automatic Measurement Auto Measurement: Cascade Elite300TM Precise wafer alignment into 3 dimensions And X/Y/Z directional control of prove skating. Auto Data processing:ic-cap Wafer Pro /Data Pro Keep man-power away from time consuming S-parameter measurements. Easy data visualization (ex. Histogram, correlation Matrices) 5

Result of Stability Check (Hz~67Hz) S S 60Hz 60Hz S S 60Hz 60Hz /4/03 43 min 6

Statistical summary of used sample at 60Hz Small sigma indicates the stability of the system. Stable probing contact S S Mean=-9.86dB Sigma=0.5dB Mean=-0.98dB Sigma=0.08dB 7

NMOSFET Lg=50nm, Wg=40um (=um x 40Fingers x 3 Blocks) Measurement condition :Id=50uA/um Vd=0.6V Vg=Vth0.3V Hz~67Hz/Hz FOM at 60Hz Accurate PVT model ft, fmax, gm, gds, Rg, Cgd(s), Cds MOMCAP (M~M5 Stacked) L=0um, NF=0 Hz~69Hz/Hz W L Spacing NF 8

Auto measurement results of Mom CAP S S 30 60Hz 60Hz S 60Hz S 60Hz Stable measurement 9

Frequency dispersion of equivalent circuit parameters CS RS 30 60Hz 60Hz Q CSUB 0

Auto measurement results of NMOS Vd=0.6V Vg~Vth0.4V DC 30

Auto measurement results of NMOS RF S S 30 60Hz 60Hz S 60Hz S 60Hz 90min

Frequency dependence of MOSFETs parameters fmax ft Cgd 30 Cds Rg gm gds Distribution are frequency dependent 3

Measure of components from y-parameters Y Y Y Y C = ω m C ω DS CS R R ω C ω D R CD C C C R gd ds gs jωc C C ( C D C m ) jω( C D C m ) ( C C C C C C ) jω( C C ) R = CB Im jωc Re Im BD D ( Y ) ( Y ) Y Y = Im = Im ( Y Y ) ( Y Y ) D D m g g m ds BD D Y Y = Re = Re ( Y Y ) Starting point the formula (.7a~.7d) : Christian C.Enz, Eric A. Vittoz, Charge-based MOS Transistor Modeling Wiley 006. 4

Inter-wafer distributions of 60Hz fmax and Rg. fmax Rg High Low 5

Accurate PVT Model Challenges oal: give designers a direct insight of the process fluctuation risk on their circuit. Approach: Formulate the SPICE model parameters distribution via physical parameters Conventional Proposed model Circuit Performance VTH0 Circuit Performance Dot=Measurement ateoxide Thickness Channel Implantation Solid=Model 6

PDK Implementation toxe =Tox_par*(T_oxN/T_oxN0) toxp =Tox_par*(T_oxN/T_oxN0) toxm =Tox_par*(T_oxN/T_oxN0) ndep =Ndep0_p*(N_depN/N_depN0) vth0 =VTH0_p * KN_VTH0 k =K_p * KN_AMMA u0 =mu0_p * KN_vsat vsat =vsat_p * KN_vsat nfactor =nfact_p Model *KN_Nfactor Card pclm =pclm_p*kn_cml pdiblc =pdiblc_p * KN_CML pdiblc =pdiblc_p*kn_cml rdsw =rdsw_p * KN_RDSW lint =lint_p* KN_LINT wint =wint_p * KN_WINT cgso =cgso_p *KN_LOV cgdo =cgdo_p *KN_LOV cgbo =cgb0_p *KN_CB cjs =cjs_p *KN_cjsi0 cjsws =cjsws_p*kn_cjsi0 pbs =pbs_p*kn_vdsi0 N_depN =.7e7 T_oxN =.39e-7 LCORR_PERCENT_N=e-3 WCORR_PERCENT_N=e-3 rho_rate=0 statistics { process { vary N_depN dist=gauss std=aa percent=yes vary T_oxN dist=gauss std=bb percent=yes vary LCORR_PERCENT_N dist=gauss std=cc percent=yes vary WCORR_PERCENT_N dist=gauss std=dd percent=yes vary rho_rate dist=gauss std=ee percent=yes } } Monte Carlo Declaration Ndep /- 6% T_ox /- 6% LCORR /- 0% WCORR /- 5% R /- % Thick_Metal /- 0% 7

Overview of Model structure (Front-END) LINT WINT DLC Length of ate-s/d overlap region R ate resistance U0,VSAT Low field mobility, Saturated velocity CJ Junction Capacitancce N _ dep CJ = CJ BSIM N _ dep0 Deviation ( PB ) PB0 PB PB0 = N _ j N _ dep ln N _ i N _ j N _ dep0 ln N _ i 8

µ U0,VSAT i U0 Drift Mobility [cm/v-s] = 0000 000 00 0 U0 BSIM Carrier mobility vs. channel impurity concentration µ u u i µ max min l ( Ndep ) = µ min α α Ndep ( Ndep ) ( Ndep 0) i ref Hole Modulation N N.0E4.0E5.0E6.0E7.0E8.0E9 Impurity Concentration [cm-3] µ ref Ndep Electron Parameter A-As P B µ max (cm V - s - ) 47.0 44.0 470.5 µ min (cm V - s - ) 5. 68.5 44.9 µ l (cm V - s - ) 43.4 56. 9.0 N ref (cm -3 ) 9.68E6 9.0E6.3E7 N ref (cm -3 ) 3.43E0 3.4E0 6.0E0 α 0.68 0.7 0.79 α.0.98.0 Formula for minority carriers. D.B.M. Klaassen,, A Unified Mobility Model for Device Simulation-I. Model Equations and Concentration Dependence, Solid-State Electronics Vol.35, No.7, pp.953-959, 99.. D.B.M. Klaassen,, A Unified Mobility Model for Device Simulation-II. Temperature Dependence of Carrier Mobility and Lifetime, Solid-State Electronics Vol.35, No.7, pp.96-967, 99. 9

0 ( ) ( ) ( ) = = = = = ]. [ 0.5 4 0 0 0 0 0 0 0 0 n n n n L L n n L V I n n L V I n n L V I W I L Cgb Cgsi V I I Cox L W Cgdi Cgsi gm Cgd Cgs gm F T C T C T C T C C Ti µ µ µ µ π µ π µ π π Formulation of ft fluctuation via DLC N (Slope) factor DLC Offset arelength Mobilty LCORR = BSIM DLC DLC ( ) ( ) Ndep 0 u Ndep u i i L L L corr 0 0 n n n n. David M.Binkeley,, Tradeoffs and optimization in Analog CMOS Circuit Design, Wiley

Overview of Model structure (Back-END) ThickMetal_INT ThickMetal_INT Dist_INT ThickMetal_INT Dist_INT Dist_INT ThickMetal_INT Dist_LOC_INT ThickMetal_LOC CS0 CD0 Dist_SUB_LOC Csub Rsub SUB

The formulae of capacitance CS Vertical CDO CSO C vertical = 8.854e = 8.854e ( L W NF ) eps _ l Dist_SUB_L OC Dist_SUB_L OC 3 ( L W NF ) eps _ l Dist_INT Dist_INT Dist_INT Dist_INT Lateral C vertical = 8.854e = 8.854e ( L W ) eps _ w ( NF ) ThickMetal _ LOC ThickMetal _ INT ( L W NF ) eps _ w 3 ThickMetal _ LOC Spacing Spacing ThickMetal _ INT ThickMetal _ INT Spacing Spacing Spacing ThickMetal _ INT Spacing

Model Validation MOSFET 3

Measurement vs. Simulation correlation - fmax Rg 0.4 0.60 fmax Rg Sigma ft Sigma ft Cgd -0.74 Cds -0.56 Cgd Cds Sigma ft Sigma ft gm 0.3 gds 0.43 gm gds Sigma ft Sigma ft ft : principle component 4

Model Validation MOM CAP 5

Measurement vs. Simulation Correlation from measurement Cs Ls -0.88-0.7 Cs Ls Rs Rsub -0.4-0.86 Rs Rsub Csub -0.3 Csub Q: principle component 6

Conclusion Automated 60Hz auto measurement. Thanks to the up-to-date hardware and data processing, we could capture the fluctuation of CMOS technology. Stability in the measurement system used in this work is kept good condition. It sensed that the deviation of MOSFET performance becomes larger as the operating frequency increases. Statistical modeling Our simplified PVT model can provide with reasonable estimation of intra-wafer variation at 60Hz. 7

8