EE 435. Lecture 18. Two-Stage Op Amp with LHP Zero Loop Gain - Breaking the Loop

Similar documents
EE 435. Lecture 16. Compensation Systematic Two-Stage Op Amp Design

EE 435 Lecture 13. Cascaded Amplifiers. -- Two-Stage Op Amp Design

EE 435. Lecture 15. Compensation of Cascaded Amplifier Structures

EE 435. Lecture 16. Compensation of Feedback Amplifiers

EE 435. Lecture 10: Current Mirror Op Amps

EE 435. Lecture 14. Compensation of Cascaded Amplifier Structures

EE 435 Lecture 13. Two-Stage Op Amp Design

V DD. M 1 M 2 V i2. V o2 R 1 R 2 C C

Analysis and Design of Analog Integrated Circuits Lecture 7. Differential Amplifiers

ECEN 326 Electronic Circuits

EE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps

EE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps

Lectures on STABILITY

Sample-and-Holds David Johns and Ken Martin University of Toronto

Ch 14: Feedback Control systems

EE 505. Lecture 27. ADC Design Pipeline

Lecture 25 ANNOUNCEMENTS. Reminder: Prof. Liu s office hour is cancelled on Tuesday 12/4 OUTLINE. General considerations Benefits of negative feedback

Polytech Montpellier MEA M2 EEA Systèmes Microélectroniques. Analog IC Design

Stability and Frequency Compensation

DESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C

Advanced Current Mirrors and Opamps

EE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design

I D based Two-Stage Amplifier Design

EE 330. Lecture 35. Parasitic Capacitances in MOS Devices

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

ELEN 610 Data Converters

EE 330 Lecture 33. Basic amplifier architectures Common Emitter/Source Common Collector/Drain Common Base/Gate. Basic Amplifiers

ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120

University of Toronto. Final Exam

OPERATIONAL AMPLIFIER APPLICATIONS

ECE 546 Lecture 11 MOS Amplifiers

Advanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs

LECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH )

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

EE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design

ECEG 351 Electronics II Spring 2017

Bandwidth of op amps. R 1 R 2 1 k! 250 k!

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

Polytech Montpellier MEA4 M2 EEA Systèmes Microélectroniques. Analog IC Design

Design of CMOS Analog Integrated Circuits. Basic Building Block

6.2 INTRODUCTION TO OP AMPS

EE 434 Lecture 16. Small signal model Small signal applications in amplifier analysis and design

System on a Chip. Prof. Dr. Michael Kraft

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

EE 508 Lecture 22. Sensitivity Functions - Comparison of Circuits - Predistortion and Calibration

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Systematic Design of Operational Amplifiers

ANALYSIS OF POWER EFFICIENCY FOR FOUR-PHASE POSITIVE CHARGE PUMPS

Lecture 6, ATIK. Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters

PI3CH400 4-Bit Bus Switch, Enable Low 1.8V/2.5V/3.3V, High-Bandwidth, Hot Plug

2N5545/46/47/JANTX/JANTXV

Input and Output Impedances with Feedback

EE 435. Lecture 23. Common Mode Feedback Data Converters

EE 508 Lecture 29. Integrator Design. Metrics for comparing integrators Current-Mode Integrators

SWITCHED CAPACITOR AMPLIFIERS

EE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods

EE 230 Lecture 25. Waveform Generators. - Sinusoidal Oscillators The Wein-Bridge Structure

Chapter 10 Feedback. PART C: Stability and Compensation

Electronic Circuits Summary

Differential Amplifiers (Ch. 10)

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1

EE 435. Lecture 22. Offset Voltages

Introduction: the common and the differential mode components of two voltages. differential mode component: v d = v 1 - v 2 common mode component:

Closed-loop system 2/1/2016. Generally MIMO case. Two-degrees-of-freedom (2 DOF) control structure. (2 DOF structure) The closed loop equations become

An Improved Logical Effort Model and Framework Applied to Optimal Sizing of Circuits Operating in Multiple Supply Voltage Regimes

ECEN 610 Mixed-Signal Interfaces

ESE319 Introduction to Microelectronics. Feedback Basics

Homework Assignment 08

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Example: High-frequency response of a follower

Lecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen

An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor. ΔΣ Modulator. Electronic Design Automation Laboratory

CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

388 Facta Universitatis ser.: Elec. and Energ. vol. 14, No. 3, Dec A 0. The input-referred op. amp. offset voltage V os introduces an output off

ESE319 Introduction to Microelectronics. Feedback Basics

Linearized optimal power flow

CE/CS Amplifier Response at High Frequencies

Pipelined multi step A/D converters

Monolithic N-Channel JFET Dual

Feedback Control G 1+FG A

Maxim Integrated Products 1

Modeling of High Voltage AlGaN/GaN HEMT. Copyright 2008 Crosslight Software Inc.

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

Lecture 46 Bode Plots of Transfer Functions:II A. Low Q Approximation for Two Poles w o

Lecture 7, ATIK. Continuous-time filters 2 Discrete-time filters

Analog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras

EE 508 Lecture 24. Sensitivity Functions - Predistortion and Calibration

Control System Design

EE 3CL4: Introduction to Control Systems Lab 4: Lead Compensation

Lecture 7: Transistors and Amplifiers

ECE 6412, Spring Final Exam Page 1

CDS 101/110a: Lecture 8-1 Frequency Domain Design

EE 435. Lecture 22. Offset Voltages Common Mode Feedback

V in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs

Lecture 37: Frequency response. Context

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers

Transcription:

EE 435 Lecture 8 Two-Stae Op Amp with LHP Zero Loop Gain - Breakin the Loop

Review from last lecture Nyquist and Gain-Phase Plots Nyquist and Gain-Phase Plots convey identical information but ain-phase plots often easier to work with Ma 70 60 ω = Im Ma Phase ω Re 50 40 30 0 0 0-0 -0-30 -40 ω -+j0 ω = - ω = 0 0-50 -00 ω -50-00 -50-300 Phase Note: The two plots do not correspond to the same system in this slide

Anle in derees Manitude in db Review from last lecture Gain and Phase Marin Examples 80 60 40 0 0-0 -40-60 -80 β T(s) ω 58 s s 0 0-50 -00 ω -50 Phase Marin -00-50 -300

Review from last lecture Relationship between pole Q and phase marin In eneral, the relationship between the phase marin and the pole Q is dependent upon the order of the transfer function and on the location of the zeros In the special case that the open loop amplifier is second-order lowpass, a closed form analytical relationship between pole Q and phase marin exists and this is independent of A 0 and β.. Q cos(φ sin(φ M M ) ) φ M cos 4Q 4 Q The reion of interest is invariable only for < Q < 0.7 larer Q introduces unacceptable rinin and settlin smaller Q slows the amplifier down too much

Review from last lecture Phase Marin vs Q Second-order low-pass Amplifier Pole Q 7 6 5 4 3 0 0 0 40 60 80 00 Phase Marin

Review from last lecture Phase Marin vs Q Second-order low-pass Amplifier Pole Q.6.4. 0.8 0.6 0.4 0. 0 40 50 60 70 80 Phase Marin

Review from last lecture Manitude Response of nd -order Lowpass Function Q MAX for no peakin =. 707 Q From Laker-Sansen Text

Review from last lecture Step Response of nd -order Lowpass Function Q Q MAX for no overshoot = / From Laker-Sansen Text

Review from last lecture ompensation Summary Gain and phase marin performance often stronly dependent upon architecture Relationship between overshoot and rinin and phase marin were developed only for nd -order lowpass ain characteristics and differ dramatically for hiher-order structures Absolute ain and phase marin criteria are not robust to chanes in architecture or order It is often difficult to correctly break the loop to determine the loop ain Aβ with the correct loadin on the loop (will discuss this more later)

Desin of Two-Stae Op Amps ompensation is critical in two-stae op amps General approach to desinin two-stae op amps is common even thouh sinificant differences in performance for different architectures Will consider initially the most basic two-stae op amp with internal compensation

Natural Parameter Space for the Two-Stae Amplifier Desin DD M 3 M 4 M 5 OUT IN M M IN L I T B M 7 B3 M 6 SS S NATURAL = {W, L, W 3, L 3, W 5, L 5, W 6, L 6, W 7, L 7, I T, I D6, c }

Desin Derees of Freedom Total independent variables: 3 Derees of Freedom: 3 If phase marin is considered a constraint 3 independent variables constraint derees of freedom

Observation: W,L appear as W/L ratio in almost all characterizin equations Implication: Derees of Freedom are Reduced S NATURAL-REDUED = {(W/L),(W/L) 3,(W/L) 5,(W/L) 6,(W/L) 7,I D6,I T, } With phase marin constraint, Derees of freedom: 7

ommon Performance Parameters of Operational Amplifiers Parameter Description Ao Open-loop D Gain GB Gain-Bandwidth Product Φm(or Q) Phase Marin (or pole Q) SR Slew Rate T SETTLE Settlin Time A T Total Area A A Total Active Area P Power Dissipation OS Standard Deviation of Input Referred Offset oltae (often termed the input offset voltae) MRR ommon Mode Rejection Ratio PSRR Power Supply Rejection Ratio imax Maximum ommon Mode Input oltae imin Minimum ommon Mode Output oltae omax Maximum Output oltae Swin omin Minimum Output oltae Swin noise Input Referred RMS Noise oltae Sv Input Referred Noise Spectral Density

Performance Parameters Total: 7

Performance parameters: 7 Derees of freedom: 7 System is Generally Hihly Over onstrained!

Typical Parameter Space for a Two-Stae Amplifier + OUT - d md d Od mo OO L Small sinal model of the two-stae operational amplifier Small sinal desin parameters: S SMALL SIGNAL = { oo, od, mo, md,, o, o4, o5, o6 }

Sinal Swin of Two-Stae Op Amp DD M 3 M 4 M 5 OUT IN M M IN L I T B SS M7 B3 M 6 M6: M5: M: i OUT OUT DD SS DD EB6 EB5 T T3 EB3 M: M7: i ic DD T T5 EB5 T EB EB 7 SS S swin/bias Related = {, EBQ, EB3Q, EB5Q, EB6Q, EB7Q, I T }

Sinal Swin of Two-Stae Op Amp OUT DD EB5 T EB EB7 max{( ( EB3 EB5 T3 T5 T T ), )} SS DD ic OUT DD EB5 OUT SS EB6 EB6 SS ic T EB EB 7 SS i DD T T3 EB3 i DD T T5 EB5

Sinal Swin of Two-Stae Op Amp OUT DD EB5 T EB EB7 max{( ( EB3 EB5 T3 T5 T T ), )} SS DD ic EB6 SS

Typical Parameter Space for a Two-Stae Amplifier DD M 3 M 4 M 5 OUT IN M M IN L I T B M7 B3 M 6 SS + OUT - d md d Od mo OO L Aumented set of desin parameters: S AUGMENTED = { oo, od, mo, md,, EBQ, EB3Q, EB5Q, EB6Q, EB7Q, I T, o, o4, o5, o6 } Parameters in this set are hihly inter-related

ommon Expressions for the Performance Parameters A O GB SR md oo I md T mo od

ommon Expressions for the Performance Parameters (cont) OMAX OMIN DD SS EB5 EB6 inmin T EB EB 7 SS max{( inmax DD EB3 T3 T EB5 T5 T ),( )}

Parameter Inter-dependence A O md GB oo mo od md I T affects SR I T W md OX T μ I L

A Set of Independent Desin Parameters is Needed onsider the Natural Reduced Parameter Set W W3 W5 W6 W 7,,,,,I T, θ L L3 L L 5 6 L7 A A = O I θ= O D6Q OX I T md oo μμ n p mo od WW LL WL 5 5 6 7 n p IT WL 7 6 λ +λ

md GB n 7 6 5 7 6 5 p 7 6 5 7 6 5 p n L L W β L L L W W W W L L L W W W L Q β n OX T μ W I L GB For a iven pole Q and a feedback factor, it can be shown that:

inmin T EB EB7 SS I L I L T T 7 imin T SS μnox W μnox W7 Expressions for sinal swins are particularly complicated!

Observation Even the most elementary performance parameters require very complicated expressions when the natural desin parameter space is used Stron simultaneous dependence on multiple natural desin parameters Interdependence and notational complexity obscures insiht into performance and optimization

Practical Set of Desin Parameters S PRATIAL = {P, θ, EB, EB3, EB5, EB6, EB7 } 7 derees of freedom! P : total power dissipation q = IDQ5/I T, current split factor EBK=GSQK-TK, excess bias voltae for the k th transistor Phase marin constraint assumed (so not shown in DoF)

Basic Two-Stae Op Amp DD M 3 M 4 M 5 OUT IN M M IN L I T B M 7 B3 M 6 SS 7 Derees of Freedom {P, θ, EB, EB3, EB5, EB6, EB7 } W W3 W5 W6 W 7,,,,,I T, θ L L3 L L 5 6 L7

Relationship Between the Practical Parameters and the Natural Desin Parameters {P, θ, EB, EB3, EB5, EB6, EB7 } W W3 W5 W6 W 7,,,,,I T, θ L L3 L L 5 6 L7 I T P +θ DD I I I,,θI T DQi T T W I DQi L i μ i OX EBi

Relationship Between the Practical Desin Parameters and the Performance Parameters (Assumin Q ) A O 4 λ λ n P Pθ EB β EB5 GB θ 4 θβ θ p EB EB5 DD EB L DD EB EB5 Pθ EB β EB5 SR EBGB 4 L θβ DD θ EB EB5 c 4 θβ L EB EB5 θ β EB EB5

Relationship Between the Proposed Desin Parameters and the Performance Parameters OMAX OMIN DD SS EB5 EB6 inmin T EB EB 7 SS max{( inmax DD EB3 T3 T EB5 T5 T ),( )}

haracteristics of the Practical Desin Parameter Space Minimum set of independent parameters Results in major simplification of the key performance parameters Provides valuable insiht which makes performance optimization more practical

Desin Assumptions Assume the followin system parameters: DD = 3.3 L = pf Typical 0.35um MOS process Simulation corner: typ/55/3.3

Example for Desin Procedure Given specifications: A 0 : 66dB GB: 5MHz OMIN = OMAX =3. INMIN =. INMAX =3 P=0.7mw = Assume: TN = 0.6, TP = 0.7, n =0.04, p =0.8 7 constraints (in addition to φ m ) and 7 derees of freedom

Example for Desin Procedure. hoose channel lenth. EB3, EB5, EB6 {P, θ, EB, EB3, EB5, EB6, EB7 } 3. EB imax = DD + EB3 + T + T3 omax = DD + EB5 omin = EB6 A = 4. EB7 imin=eb + EB7 + T O 4 λ +λ n p EB EB5 {P, θ, EB, EB3, EB5, EB6, EB7 } {P, θ, EB, EB3, EB5, EB6, EB7 } 5. hoose P to satisfy power constraint {P, q, EB, EB3, EB5, EB6, EB7 } I T P +θ DD

Example for Desin Procedure 6. hoose q to meet GB constraint GB 7. ompensation capacitance c DD 4 L q EB EB 5 q EB 8. alculate all transistor sizes I = T P +θ DD EB 5 EB5 q P P q EB q EB 4LqDD EB EB5 Wk L k I μ Dk OXEBk {P, q, EB, EB3, EB5, EB6, EB7 } 9. Implement structure, simulate, and make modifications if necessary uided by where deviations may occur Note: It may be necessary or preferable to make some constraints an inequality Note: Specifications may be over-constrained or have no solution k (Assumin Q )

Example for Desin Procedure Desin results: M, W/L M 3,4 W/L M 5 W/L M 6 W/L M 7 W/L P θ 3/ 4.5/ 54/ 7.4/ 7.4/ 0.7mW.06 3.7pF Simulation results: A0 GB P Phase marin 65dB 5.MHz.7mW 45.4 derees

Spreadsheet for Desin Space Exploration Settlin haracteristics of Two-Stae Operational Amplifier Process Parameters 0.0 Power 0.0 ln 9E-05 uoxn E- T 0. lp 5E-05 uoxp 4 dd 0.768 tn 0.774 tp Dev ice Sizin Output Rane Input Rane Performance haracteristics Desin Parameters W/L5 W/L W/L max min max min ISS(mA) GB Ao EB7 EB6 EB5 EB EB 48. 48. 7.5 3.5 4.7.5 4E-.67 8.3E+08 48. 48. 8. 3.5 4.7.0 8.9E-3.67.9E+09 556 48. 37.0 4.5 3.5 3.77 3.0 3.3E-3.67.6E+09 78 48. 37.0 7.5 3.5 3.77.5 4E-.67 8.3E+08 48. 9.3 8. 3.5.77.0 8.9E-3.67.9E+09 556 48. 9.3 4.5 3.5.77 3.0 3.3E-3.67.6E+09 78 37.0 48. 7.5 3 4.7.5 ERR.67 ERR 556 37.0 48. 8. 3 4.7.0 4E-.67 4.E+08 78 37.0 37.0 4.5 3 3.77 3.0 8.9E-3.67 9.4E+08 39 37.0 37.0 7.5 3 3.77.5 ERR.67 ERR 556 37.0 9.3 8. 3.77.0 4E-.67 4.E+08 78 37.0 9.3 4.5 3.77 3.0 8.9E-3.67 9.4E+08 39 9.3 48. 7.5 4.7.5 4E-.67 8.3E+08 78 9.3 48. 8. 4.7.0 ERR.67 ERR 39 W/L7 W/L6 W/L5 579.7 89.9 48. 579.7 89.9 48. 579.7 89.9 48. 579.7 89.9 48. 579.7 89.9 48. 579.7 89.9 48. 579.7 89.9 37.0 579.7 89.9 37.0 579.7 89.9 37.0 579.7 89.9 37.0 579.7 89.9 37.0 579.7 89.9 37.0 579.7 89.9 9.3 579.7 89.9 9.3 Dev ice Sizin W/L7 W/L6 W/L5 W/L

Summary. Determination of Desin Space and Derees of Freedom Often Useful for Understandin the Desin Problem. Analytical Expressions for Key Performance Parameters ive onsiderable Insiht Into Desin Potential 3. Natural Desin Parameters Often Not Most Useful for Providin Insiht or Facilitatin Optimization 4. oncepts Readily Extend to other Widely Used Structures

Basic Two-Stae Op Amp DD M 3 M 4 M 5 OUT IN M M IN L I T B M 7 B3 M 6 A FB (s) SS s L s md m0 sc mo β md β mdmo Riht Half-Plane Zero Limits Performance Why does the RHP zero limit performance? an anythin be done about this problem?

Why does the RHP zero limit performance? Gain Manitude in db 00 80 60 40 0 0-0 -40-60 -80 β All Pole RHP Zero Phase in Derees 0.00E+00 -.00E+0-4.00E+0-6.00E+0-8.00E+0 -.00E+0 -.0E+0 -.40E+0 -.60E+0 -.80E+0 -.00E+0 RHP Zero All Pole p =, p =000, z x ={none,50} In this example: accumulate phase shift and slow ain drop with RHP zeros effects are dramatic

Why does the RHP zero limit performance? Gain Manitude in db 00 80 60 40 0 0-0 -40-60 -80 β All Pole LHP and RHP Zero Phase in Derees 0.00E+00 -.00E+0-4.00E+0-6.00E+0-8.00E+0 -.00E+0 -.0E+0 -.40E+0 -.60E+0 -.80E+0 -.00E+0 RHP Zero LHP Zero All Pole p =, p =000, z x ={none,50,-50} In this example: accumulate phase shift and slow ain drop with RHP zeros loose phase shift and slow ain drop with RHP zeros effects are dramatic

Two-stae amplifier (with RHP Zero ompensation) What causes the Miller compensation capacitor to create a RHP zero? DD M 3 M 4 M 5 s+p s+p A = A p p 0 OUT IN M M IN L with Miller ompensation I T B SS M7 B3 + - d=in-in M 6 A = A 0 pp -s+z z s+p s+p At low frequencies, OUT / d is neative but at hih frequencies it becomes positive Alternately, provides a feed-forward noninvertin sinal from the output of the first stae to the output of the second stae

Two-stae amplifier (with RHP Zero ompensation) What can be done to remove the RHP zero? DD M 3 M 4 M 5 s+p s+p A = A p p 0 IN M M IN L OUT with Miller ompensation B I T M7 B3 M 6 A = A 0 pp -s+z z s+p s+p SS + - d=in-in Alternately, provides a feed-forward noninvertin sinal from the output of the first stae to the output of the second stae Break the feed-forward path from the output of the first stae to the output of the second stae at hih frequencies

Two-stae amplifier with LHP Zero ompensation DD DD M 3 M 4 M 5 M 3 M 4 M 5 IN M M IN L OUT A B R OUT I T IN M M IN L B M7 B3 M 6 SS B M 7 B M 6 Riht Half-Plane Zero Limits Performance Zero can be moved to Left Half-Plane R realized with sinle triode reion device

Two-stae amplifier with LHP Zero ompensation DD IN M 3 M 4 M 5 A B R M M IN OUT L A(s) md s m5 m5 sc c L s m5 oo od B M 7 B M 6 z m5 m5 z location can be prorammed by R If c > m5, z in RHP and if c < m5, z in LHP R has almost no effect on p and p

Two-stae amplifier with LHP Zero ompensation 6 05 5 5 o m o o p od oo m L c m c m md s s s A(s) 5 5 5 5 5 m m z L m p 5 p p X X z where should z be placed?

Two-stae amplifier with LHP Zero ompensation where should z be placed? X X p p X X p p X X p p z z z z p Would make situation worse (because m5 m5 o 05 o5 m5 m5 p ratio between two dominant poles would be reduced! L o6 X X z p p X X p z p

Two-stae amplifier with LHP Zero ompensation where should z be placed? Would make situation worse (because ratio between two dominant poles would be reduced! X X p p z Other parasitic poles, at hiher frequencies are present and not too much larer than p! X X X X p 4 p 3 p p z

Two-stae amplifier with LHP Zero ompensation X X z p p z m5 m5 z often used to cancel p an reduce size of required compensation capacitor a) eliminates RHP zero b) increases spread between p and p 3 Improves phase marin Desin formulations easily extend to this structure

Two-stae amplifier with LHP Zero ompensation X p 3 X X p p z z m5 m5 Analytical formulation for compensation requirements not easy to obtain (must consider at least 3 rd order poles and both T(s) and poles not mathematically tractable) often chosen to meet phase marin (or settlin/overshoot) requirements after all other derees of freedom used with computer simulation from manitude and phase plots

Basic Two-Stae Op Amp with LHP zero DD M 3 M 4 M 5 A B R OUT IN M M IN L B M 7 B M 6 8 Derees of Freedom with zero cancellation of p {P, θ, EB, EB3, EB5, EB6, EB7,R, } constraint (phase marin) 7 Derees of Freedom {P, θ, EB, EB3, EB5, EB6, EB7,R, } constraints (phase marin), z = p = - m5 m5 -

Basic Two-Stae Op Amp with LHP zero DD M 3 M 4 M 5 with zero cancellation of p IN A B M M R IN OUT L 7 Derees of Freedom B M 7 B M 6 {P, θ, EB, EB3, EB5, EB6, EB7,R, } - constraints (phase marin), z m5 = p = m5 - Desin Flow:. Inore R and desin as if RHP zero is present. Pick R to cancel p 3. Adjust p (i.e. chane/reduce ) to achieve desired phase marin

Basic Two-Stae Op Amp with LHP zero DD M 3 M 4 M 5 A B R OUT IN M M IN L B M 7 B M 6 XX Realization of R R = μ OX L W EB R OR YY Transistors in triode reion ery little current will flow throuh transistors (and no dc current) DD or GND often used for XX or YY BQ well-established since it determines I Q5 Usin an actual resistor not a ood idea (will not track m5 over process and temp)

Two-Stae Amplifiers Practical onsiderations Loop Gain Loadin of A and β networks Breakin the Loop (with appropriate terminations) Biasin of Loop Simulation of Loop Gain Open-loop ain simulations Systematic Offset Embeddin in closed loop

End of Lecture 8