Slide Set 6 for ENEL 353 Fall 2017 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2017
SN s ENEL 353 Fall 2017 Slide Set 6 slide 2/44 Contents Multiplexers Decoders Introduction to timing of combinational logic Propagation and contamination delays Overall t pd and t cd calculations Glitches
SN s ENEL 353 Fall 2017 Slide Set 6 slide 3/44 Outline of Slide Set 6 Multiplexers Decoders Introduction to timing of combinational logic Propagation and contamination delays Overall t pd and t cd calculations Glitches
SN s ENEL 353 Fall 2017 Slide Set 6 slide 4/44 Multiplexers Multiplexer is rather a long word, so mux is often used as an abbreviation. Another quite descriptive name for multiplexer is selector. A multiplexer circuit has two or more data inputs; one or more bits of select input; an output. The job of a multiplexer is to copy one of the data inputs to the output. The data input selected for copying is chosen by the select input.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 5/44 The 2:1 multiplexer ( two-to-one mux ) A circuit symbol and truth table: D 0 0 D 1 1 S Y D 1 D 0 S Y 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Let s write out a few sentences to describe exactly what this circuit does.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 6/44 2:1 mux built from NOT, AND and OR gates The truth table from the previous slide results in this K-map and minimal SOP expression... D 1 D 0 S 00 01 11 10 1 1 0 Y = D 0 S + D1 S 1 1 1 S A circuit for this made from NOT, AND, and OR gates... D 0 Y D 1
SN s ENEL 353 Fall 2017 Slide Set 6 slide 7/44 Variations on the tristate buffer (a) A Y non-inverting, active high enable (c) E E A Y inverting, active high enable (b) A (d) E Y non-inverting, active low enable E A Y inverting, active low enable Version (a) is the one we have already looked at. But each of (b), (c), and (d) is sometimes useful as well. Let s make tables to describe all four circuits.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 8/44 2:1 mux implemented with tristate buffers The two schematics describe exactly the same design. The one on the right is from the textbook, and uses a compact notation for showing a common control input wire for the tristate buffers. S S D 0 D 1 T0 T1 Y D 0 D 1 T0 T1 Y Two gate outputs are wired together! Y Is= that D 0 S + adproblem 1 S in this design? Image on right is from Figure 2.56 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 9/44 The 4:1 multiplexer ( four-to-one mux ) S 1 S 0 D 0 00 How many rows would a truth table for this circuit have? D 1 01 D 2 10 D 3 11 Y Let s describe the circuit in a table that is more compact than a truth table.
Let s make some notes on these three designs for 4:1 mux circuits. S 1 S 0 S 1 S 0 D 0 D 0 D 1 S 1 S 0 S 0 S 1 D 2 D 3 D 1 D 2 S 1 S 0 S 1 S 0 Y D 0 D 1 D 2 0 1 0 0 1 Y (a) Y D 3 (b) D 3 (c) 1 Image is Figure 2.58 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 11/44 Base two logarithms: What does log 2 N mean? Base two logarithms are often useful in discussion of digital systems (and also in discussion of computing algorithms and data structures). You should already be familiar with natural (base e) and common logarithms, defined as follows: If y = e x, then ln y = x. If y = 10 x, then log 10 y = x. The definition for the base two logarithm works the same way: If y = 2 x, then log 2 y = x.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 12/44 Wider multiplexers If you understand 2:1 and 4:1 muxes, it s very easier to generalize to N:1, if N is a power of two. The table to the right describes an 8:1 mux. How many select bits would be needed for a 16:1 mux? For a 32:1 mux? What would be a general formula for the number of select bits needed for an N:1 mux? S 2 S 1 S o Y 0 0 0 D 0 0 0 1 D 1 0 1 0 D 2 0 1 1 D 3 1 0 0 D 4 1 0 1 D 5 1 1 0 D 6 1 1 1 D 7
SN s ENEL 353 Fall 2017 Slide Set 6 slide 13/44 Using muxes to implement logic functions Multiplexers have a lot of practical applications. We ll see some of them later in this course and others in ENCM 369 in Winter. For now, we ll just look at one such application: Given a truth table with N rows for a function F, it s very straightforward to make a circuit for F with an N:1 multiplexer as the key component.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 14/44 Textbook graphical notation for HIGH and LOW voltage connections This schematic is an example of the symbols Harris & Harris use... connection to V DD (power supply) connection to ground What is the output of the AND gate? (This is supposed to be an easy question.)
SN s ENEL 353 Fall 2017 Slide Set 6 slide 15/44 Example of using muxes to implement logic functions How can we implement the given function with an 8:1 mux? How can we implement the given function with a 4:1 mux and an inverter? A B C Y 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0
SN s ENEL 353 Fall 2017 Slide Set 6 slide 16/44 N:1 multiplexers with N not a power of two Sometimes a circuit requires selection of one of N signals, where N is not a power of two. This is easy to accommodate. For example, let s describe a 3:1 mux. Let s build a 3:1 mux from two 2:1 muxes. Let s build a 3:1 mux using a 4:1 mux.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 17/44 Outline of Slide Set 6 Multiplexers Decoders Introduction to timing of combinational logic Propagation and contamination delays Overall t pd and t cd calculations Glitches
SN s ENEL 353 Fall 2017 Slide Set 6 slide 18/44 Decoders A decoder has N inputs and 2 N outputs. Here are examples of 2:4 and 3:8 decoders... Y 7 Y 6 A 1 Y 3 2:4 Y 2 A 3:8 1 A 0 decoder decoder Y 1 Y 0 A 2 A 0 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 Let s write a description of the 2:4 decoder, then show how to make one using inverters and AND gates.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 19/44 Building logic functions with decoders Because decoders are minterm generators, decoders can be used to go from truth tables to circuits in a very straightforward way. Let s illustrate this by making a 1-bit full adder out of a 3:8 decoder and some OR gates.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 20/44 Decoders with enable inputs (This topic is not covered in Section 2.8 in the textbook.) A common variation of the decoder is a decoder with an enable input: A 1 A 0 2:4 decoder EN 11 10 01 00 Y 3 Y 2 Y 1 Y 0 This is just like the 2:4 decoder we looked at earlier, except that when EN = 0, all outputs are 0. Let s write a truth table for this.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 21/44 Using small decoders with enable inputs to make bigger decoders Let s build a 3:8 decoder using an inverter and two 2:4 decoder-with-enable circuits. Let s build a 4:16 decoder-with-enable using some 2:4 decoder-with-enable circuits.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 22/44 Outline of Slide Set 6 Multiplexers Decoders Introduction to timing of combinational logic Propagation and contamination delays Overall t pd and t cd calculations Glitches
SN s ENEL 353 Fall 2017 Slide Set 6 slide 23/44 Introduction to timing of combinational logic The definition of combinational logic is that the outputs of a combinational element depend only on the current values of its inputs. In reality, combinational elements have very, very short reaction times. Changes in inputs trigger changes to outputs that are almost but not quite instant. Delays in combinational logic can set important limits on how fast digital systems can operate. We re about to study some simple methods for estimating overall delays when complex combinational elements are built from simpler combinational elements.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 24/44 How short is a picosecond? 1 ps = 1 10 12 s. Every second contains 10 12 = 1 trillion picoseconds. For simple logic gates in today s integrated circuits, propagation delays reaction times to changes in input values are typically tens of picoseconds. An Olympic sprinter is considered to have false-started if she or he has reacted to the starting gun in less than 0.100 seconds. Let s compare logic gates and humans using the same units for time... Typical AND gate reaction time: 60 ps. Very fast human reaction time: 100,000,000,000 ps.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 25/44 Sketching logic levels as functions of time When a logic signal changes value, voltage as a function of time will follow a curve dictated by some complex physics: V DD voltage 0 time In making sketches to illustrate digital circuit timing, the exact shapes of voltage/time curves are not important, and this style of drawing is often used: logic 1 level 0 time
SN s ENEL 353 Fall 2017 Slide Set 6 slide 26/44 Delay in a simple gate A A Y Time delay Y By convention, delay is measured from the time that the input is halfway between LOW and HIGH; to the time that the output is halfway between LOW and HIGH. Image is Figure 2.66 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 27/44 A combinational element will exhibit a range of delays There is no single reaction time for a given combinational element. Here are some of the many reasons for this: HIGH-to-LOW output transitions may be faster or slower than LOW-to-HIGH transitions, depending on the design of the element. Circuits tend to get slower as they get warmer. Supposedly identical gates may perform differently due to due to variations in manufacturing. In elements with multiple output bits, some output bits may switch faster than others.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 28/44 Outline of Slide Set 6 Multiplexers Decoders Introduction to timing of combinational logic Propagation and contamination delays Overall t pd and t cd calculations Glitches
SN s ENEL 353 Fall 2017 Slide Set 6 slide 29/44 Propagation and contamination delays Because any combinational element exhibits a range of delays, delay characteristics of an element are often described by two numbers: t pd, the propagation delay. This is the maximum possible delay under the expected operating conditions for the element. t cd, the contamination delay. This is the minimum possible delay under the expected operating conditions for the element.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 30/44 t pd and t cd illustrated in a timing diagram A Y A Y t cd t pd This is a relatively simple timing diagram, but there is still a lot going on here! Let s make some notes about how to read this diagram. Time Image is Figure 2.67 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 31/44 Example propagation and contamination delays A detailed simulation of a 2-input NAND gate design produces the data shown in the sketch below... 1 A 0 1 B 0 Y 1 0 A B Y 100ps 130ps 220ps 280ps 150ps 200ps 350ps 380ps What does the data tell us about t pd and t cd for this NAND gate design?
SN s ENEL 353 Fall 2017 Slide Set 6 slide 32/44 What are the causes of delays? One major cause is the fact that a node in a logic circuit acts as a capacitor. That puts a limit on the rate of change of voltage at a node. I + V C I = C dv dv, so dt dt = I C. Another important cause is wire delay it takes a small amount of time for a voltage change to get from one end of a wire to the other, even for the tiny wires within integrated circuits. We won t study the physical causes of delay in ENEL 353. It s an important topic in ENCM 467 (Digital Electronics).
SN s ENEL 353 Fall 2017 Slide Set 6 slide 33/44 Outline of Slide Set 6 Multiplexers Decoders Introduction to timing of combinational logic Propagation and contamination delays Overall t pd and t cd calculations Glitches
SN s ENEL 353 Fall 2017 Slide Set 6 slide 34/44 Overall t pd and t cd calculations Suppose a combinational system is built by wiring together some combinational elements. C L C L C L C L If we have t pd and t cd data for each of the elements, how can we find overall values of t pd and t cd for the system as a whole? We ll see that solving this problem involves concepts called the critical path and the short path.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 35/44 A simple example of t pd and t cd calculations A B C D Y gate t pd t cd AND 50 35 OR 60 45 (Times given in ps.) What is the critical path for this circuit? What is the short path? What is the overall t pd? What is the overall t cd?
SN s ENEL 353 Fall 2017 Slide Set 6 slide 36/44 Another simple example of t pd and t cd calculations A B C D E Y Timing data in ps... gate t pd t cd NOT 15 10 4-input AND 50 25 2-input OR 30 22 What is the critical path for this circuit? What is the short path? What are the overall t pd and t cd? What important point is being made in this example?
SN s ENEL 353 Fall 2017 Slide Set 6 slide 37/44 A third simple example of t pd and t cd calculations A B C D E n1 n2 Y Timing data in ps... gate t pd t cd NOT 15 10 2-input AND 31 25 3-input AND 40 30 2-input OR 42 32 What are the overall t pd and t cd?
SN s ENEL 353 Fall 2017 Slide Set 6 slide 38/44 Timing data for textbook 4:1 mux examples Gate t pd (ps) NOT 30 2-input AND 60 3-input AND 80 4-input OR 90 tristate (A to Y ) 50 tristate (EN to Y ) 35 Sometimes a gate can respond faster to one of its inputs than to another. The tristate buffer is an example of that. All of the data is made up for the purpose of setting up the mux design examples. (That s also true about other examples in the textbook and in lecture slides.) Real timing depends on dimensions and chemical composition of transistors, layout of gates, and other factors. A EN Y
For these 4:1 mux designs, find t pd from the S inputs to the output, and also from the D inputs to the output. S 1 S 0 S 1 S 0 D 0 D 0 D 1 D 2 D 3 D 1 D 2 Out Out D 3 t pd_sy = t pd_inv + t pd_and3 + t pd_or4 t pd_sy = t pd_inv + t pd_and2 + t pd_tri_sy Image is taken= from 30 ps Figure + 80 ps + 2.73 90 ps from Harris D. = 30 M. ps and + 60 ps Harris + 35 ps S. L., Digital Design (a) = and 200 Computer ps Architecture, (b) 2nd = 125 ed., psc 2013, Elsevier, Inc. tpd_dy = t pd_and3 + t pd_or4 tpd_dy = t pd_tri_ay = 170 ps = 50 ps
SN s ENEL 353 Fall 2017 Slide Set 6 slide 40/44 One more 4:1 mux example D 0 S 0 S 1 For these 4:1 mux designs, find t pd from the S inputs to Y, and also from the D inputs to Y. D 1 D 2 D 3 2:1 mux 2:1 mux 2:1 mux t pd_s0y = t pd_trlsy + t pd_tri_ay = 85 ns Y Image is taken from Figure 2.74 from Harris D. M. and Harris S. L., Digital Design and Computer Architecture, 2nd ed., c 2013, Elsevier, Inc. Note: The textbook gives answers in nanoseconds, but clearly they should be in picoseconds.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 41/44 Outline of Slide Set 6 Multiplexers Decoders Introduction to timing of combinational logic Propagation and contamination delays Overall t pd and t cd calculations Glitches
SN s ENEL 353 Fall 2017 Slide Set 6 slide 42/44 Glitches A C n1 n2 Y B n3 What is Y when (A,B,C) = (1,1,1)? What about (A,B,C) = (1,1,0)? Suppose the delays are 30 ps for NOT, 50 ps for AND, and 60 ps for OR. Let s make a timing diagram to show what happens to Y when (A,B,C) goes from (1,1,1) to (1,1,0).
SN s ENEL 353 Fall 2017 Slide Set 6 slide 43/44 Timing diagram for glitch example 1 A 0 1 B 0 1 C 0 1 n1 0 1 n2 0 1 n3 0 1 Y 0 t = 0ps 30ps 50ps 80ps 110ps 140ps Let s write down a few remarks about this diagram.
SN s ENEL 353 Fall 2017 Slide Set 6 slide 44/44 Are glitches bad? In certain specialized digital design problems, avoidance of glitches in combinational outputs is very important. Usually, though, glitches are not a concern, and what really matters in timing of combinational logic is making sure that overall propagation delay is not long. (Sometimes low power consumption is even more important than small propagation delay.) In Section 2.9.2, Harris & Harris present a method based on K-maps that can sometimes be used to make circuits glitch-free. We re not going to study that in ENEL 353.