CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements
Adders 2
Circuit Delay Transistors have instrinsic resistance and capacitance Signals take time to propagate from the input to the output of a gate Sometimes delays are labeled as @<delay_value> in circuit drawings 3
-Bit & Multi-bit Adders Half Adder A C out + S B C out Full Adder A + S B C in Types of multi-bit adders Ripple-carry (slow) Carry-lookahead (faster) Two-level logic adder (even faster) A B C out S = A B C out = AB S C in A B C out S C out Symbol A B N N + S N C in S = A B C in C out = AB + AC in + BC in
Ripple-Carry Adder Chain -bit adders together Carry ripples through entire chain Disadvantage: slow A 3 B 3 A 3 B 3 A B A B C out + C + 3 C 29 C + C + C in S 3 S 3 S S Ripple-carry adder delay t ripple = Nt FA where t FA is the delay of a full adder
Two-level Logic Adder No matter how many inputs you have, look at the truth table, convert to Kmap, apply the algorithm for two-level logic minimization Very fast adder, but. Beyond 8 inputs, a shockingly large amount of gates! Number of gates increases exponentially Ripple carry adder Carry-lookahead adder (next slide) FAST Two-level logic adder COMPLEX
Carry-lookahead adders c4 c3 c2 c c a3 a2 a a b3 b2 b b s3 s2 s s Carries First operand Second operand From the very beginning I can look ahead into the value of carries
Carry-lookahead adders Adder with propagate (P) and generate (G) outputs: Ci+ = Ai Bi + Ci (Ai xor Bi) Generate Propagate Ci+ = Gi + Ci Pi The carry at some level is equal to if either the generate signal is equal to one or if the propagate and the previous carry are both
Carry-lookahead adders Ci+ = Ai Bi + Ci (Ai xor Bi) Carry a b Sum
Carry-lookahead adders Example: 4-bit CLA adder c = G + P c c2 = G + P c c3 = G2 + P2 c2 c4 = G3 + P3 c3 Gi = ai bi Pi = ai xor bi generate propagate All G and P are immediately available, but c are not (except the c). So you need to make substitutions: c = G + P c c2 = G + P (G + P c) c3 = G2 + P2 c2 c4 = G3 + P3 c3 = G + PG + PPc = (derive at home) = (derive at home)
Carry-lookahead adders Propagate/Generate circuit (one per each input bit) Ai Bi Ci Pi @ gate delay Si @ 2 gate delays Gi @ gate delay Carry circuits (implement the equations derived in the previous slide) C P G C P P G P G C @ 3 C2 @ 3 C P P P2 G P P2 G P2 G2 C3 @ 3 Note: this approach of looking ahead for building multi-bit operations is not limited to adders! C P P P2 P3 G P P2 P3 G P2 P3 G2 P3 G3 C4 @ 3
Combining Adders Example: connect CLAs in a ripple-carry style (6-bit adder) 4-bit 4-bit 4-bit 4-bit CLA CLA CLA cout CLA Example: connect ripple-carry in CLA style (4-bit adder) B[3:2] A[3:2] S[5:2] S[:8] S[7:4] S[3:] CL logic B[:] A[:] c2 Ripplecarry 2-bit S[3:2] Ripplecarry 2-bit S[:] c Connect carries in a chain cin c2 = G + PG + PPc Where: G = AB G = AB P = A xor B P = A xor B 2
Subtractors 3
2s complement If N is a positive number, then the negative of N (its 2s complement or N* ) is bit-wise complement plus The most significant bit represent the sign: for positive and for negative N bit can represent [ 2 N ] integer positive numbers In 2s complement, you can represent the interval (2 N (2 N )] 4
2s Complement: Examples A 8-bit example (positive) = (complement) (add ) A 5-bit example (negative) = -4 (complement) (add ) 5
Subtraction If you are using 4 bit numbers, what is the result of the following equation in 2s complement: y = 4-7 A. B. C. D. E. None of the above 6
Detecting Overflow: Method Assuming 4-bit two s complement numbers, one can detect overflow by detecting when the two numbers sign bits are the same but are different from the result s sign bit If the two numbers sign bits are different, overflow is impossible Adding a positive and negative can t exceed the largest magnitude positive or negative Simple circuit overflow = a3 b3 s3 + a3b3s3 sign bits + + + overflow (a) overflow (b) no overflow (c) If the numbers sign bits have the same value, which differs from the result s sign bit, overflow has occurred. 7
Detecting Overflow: Method 2 Detect a difference between carry-in to sign bit and carry-out from it Yields a simpler circuit: overflow = c3 xor c4 = c3 c4 + c3 c4 + + + overflow (a) overflow (b) no overflow (c) If the carry into the sign bit column differs from the carry out of that column, overflow has occurred. 8
Subtractor A subtraction between A and B is the same as the sum between the first value and the negative of the second value: (A - B) = A + (-B) Represent numbers in 2s complement and use a normal adder! Symbol A B N N - Y N Implementation A B N N N + Y N
Adder/subtractor A3 B3B3' A2 B2B2' A BB' A BB' Sel Sel Sel Sel A B A B A B A B Cout Cin Cout Cin Cout Cin Cout Cin Sel Sum Sum Sum Sum S3 S2 S S Overflow In this schematic addition occurs when Sel signal is: A. True B. False 2
More ALU Components 2
Comparator: Equality Two numbers are equal if each digit at each position is equal (this is true for any base: decimal, binary, etc). The bit-to-bit equality can be evaluated with the XNOR gate. Symbol Implementation A 3 B 3 A 4 = B 4 A 2 B 2 A Equal Equal B A B
Comparator: Less Than If a number A is less than B and you consider the difference A B, this is: negative. So comparing numbers is equivalent to check the sign of the difference. In 2s complement representation, the sign of the result corresponds to: the most significant bit A N B N - N [N-] A < B 5-<23>
Shifters Logical shifter: shifts value to left or right and fills empty spaces with s Ex: >> 2 = Ex: << 2 = Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old most significant bit Ex: >>> 2 = Ex: <<< 2 = Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end Ex: ROR 2 = Ex: ROL 2 = Useful for 2- complement numbers https://en.wikipedia.org/wiki/circular_shift
General Shifter Design A 3 A 2 A A shamt : 2 S : Y 3 Based on the value of the selection input (shamt = shift amount) S : Y 2 The chain of multiplexers determines how many bits to shift S : S : Y Example: if S = then Y3 = Y2 = A3 Y = A2 Y = A Y
Multiplication of positive binary numbers Generalized representation of multiplication by hand Example: in decimal, 32 * 4 = (3+2)*4 = 3*4 + 2*4 Basically: sum up the partial products (pp) The binary multiplier is based on the same idea: For demo see: http://courses.cs.vt.edu/~cs4/buildingblocks/multiply..html 26
pp4 pp3 pp2 pp Multiplier design array of AND gates Multiplier Array Style a3 a2 a a b b b2 + (5-bit) b3 + (6-bit) A * P B If the multiplier has two N-bit inputs, how many bits are required for the output? + (7-bit) p7..p Block symbol 27
Division of positive binary numbers Repeated subtraction Set quotient to Repeat while dividend >= divisor Subtract divisor from dividend Add to quotient When dividend < divisor: Reminder = dividend uotient is correct For demo see: http://courses.cs.vt.edu/~cs4/buildingblocks/binary.divide.html B A Example: Dividend: ; Divisor: Dividend DIVIDER uotient - + - + OUT 28
ALU: Arithmetic Logic Unit 29
Zero Extend 2 3 Arithmetic Logic Unit Example A N N N B N F 2 A N ALU N Y B N 3 F F 2: Function A & B A B A + B Not used A & ~B A ~B C out + [N-] S A - B Not used N N N N 2 F : Implement the ALU using as few components as possible Y N
Transistors Summary of what we have seen so far Boolean algebra Basic gates Logic functions and truth tables Canonical forms (SOP and POS) Two-level logic minimization Kmaps Multiplexers (behavior and how to implement logic functions with them) Decoders (behavior and how to implement logic functions with them) Today: Adders, subtractors, and other ALU components SO FAR: only COMBINATIONAL logic (i.e. no memory elements) 3
CSE4: Components and Design Techniques for Digital Systems Sequential Circuit Introduction Latches and Flip-Flops Tajana Simunic Rosing
What is a sequential circuit? A circuit whose output depends on current inputs and past outputs A circuit with memory Memory / Time steps x i s i y i Clock y i =f i (S t,x) s i t+ =g i (S t,x) 33
Why do we need circuits with memory? Circuits with memory can be used to store data Systems have circuits that run a sequence of tasks Memory Hierarchy Registers Cache Main Memory Hard disk
Flight attendant call button Flight attendant call button Press call: light turns on Stays on after button released Press cancel: light turns off Logic circuit to implement this? Call button Cancel button Bit Storage Blue light. Call button pressed light turns on SR latch implementation Call= : sets to and keeps it at Cancel= : resets to Call button Cancel button Bit Storage Blue light 2. Call button released light stays on a Call button S Call button Cancel button Bit Storage Blue light Cancel button R Blue light 3. Cancel button pressed light turns off 35
SR Latch Analysis S =, R = : then = and = R N S N2 S =, R = : then = and = R N S N2
SR Latch Analysis S =, R = : prev = prev = then = prev Memory! R N R N S N2 S N2 S =, R = : then =, = Invalid State NOT R S N N2
What if a kid presses both call and cancel Call but ton Cancel but ton & then releases them? S R If S= and R= at the same time and then released, =? Can also occur also due to different delays of different paths may oscillate and eventually settle to or due to diff. path delay 38 Blue light S R hold not allowed S R t
SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output (S =, R =, = ) Reset: Make the output (S =, R =, = ) Hold: Keep data stored (S =, R =, = previous ) SR Latch Symbol R S
SR Latch Characteristic Equation To analyze, break the feedback path SR Latch Symbol R (t) R S ' S R (t+ ) S S R (t) (t+ ) S hold X reset (t) X R set X characteristic equation not allowed X (t+ ) = S + R (t) State Diagram 4 SR
Add input C Avoiding S=R= Part : Level-Sensitive SR Latch Change C to only after S and R are stable C is usually a clock (CLK) S Level-sensitive SR latch S C R R
Clocks Freq GHz GHz GHz MHz MHz Period. ns. ns ns ns ns Clock -- Pulsing signal for enabling latches; ticks like a clock Synchronous circuit: sequential circuit with a clock Clock period: time between pulse starts Above signal: period = 2 ns Clock cycle: one such time interval Above signal shows 3.5 clock cycles Clock duty cycle: time clock is high 5% in this case Clock frequency: /period Above : freq = / 2ns = 5MHz; 42
Clock question The clock shown in the waveform below has: ns CLK A. Clock period of 4ns with 25MHz frequency B. Clock duty cycle 75% C. Clock period of ns with GHz frequency D. A. & B. E. None of the above 43
Avoiding S=R= Part 2: Level-Sensitive D Latch D C D S D latch S C R R SR latch requires careful design so SR= never occurs D latch helps by inserting the inverter between S & R inputs Inserted inverter ensures R is always the opposite of S when C= 44
D Latch Truth Table CLK D R R D S S CLK D X D X S R prev prev
D Latch Summary Two inputs: CLK, D CLK: controls when the output changes D (the data input): controls what the output changes to Function When CLK =, D passes through to (transparent) When CLK =, holds its previous value (opaque) (Mostly) avoids invalid case = D Latch Symbol D CLK
Level-Sensitive D Latches Assume that data in all latches is initially. Input Y= and Clk transitions from ->. When Clk= again, the stored values in latches are: Y D D2 2 D3 3 D4 4 C C2 C3 C4 Clk Clk_A Clk_B A. =, 2=, 3=, 4= for both clock A & B B. =, 2=, 3=, 4= for clock A =, 2=, 3=, 4= for clock B C. =, 2=, 3=, 4= for both clocks D. More information is needed to determine the answer E. None of the above 47
D Flip-Flop Design & Timing Diagram D flip-flop D Dm D latch m Ds D latch s Cm Cs s master servant Clk Flip-flop: Bit storage that stores on the clock edge, not level Master-slave design: master loads when Clk=, then slave when Clk= 48
D Flip-Flop: Characteristic Equation D CLK Id D (t) (t+) 2 3 Characteristic Equation (t+) = D(t)